MC74LVX259M [ONSEMI]
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter; 8位/ 1 -OF- 8解码器CMOS寻址锁存逻辑电平转换器
| 型号： | MC74LVX259M |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter |
| 文件： | 总11页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74LVX259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology.
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MARKING DIAGRAMS
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The LVX259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table.. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non–addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one–of–eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
16
9
LVX259
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
8
16
9
LVX
259
TSSOP–16
DT SUFFIX
CASE 948F
AWLYWW
1
8
16
9
LVX259
ALYW
The MC74LVX259 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5 V circuits to 3 V
circuits.
SOIC EIAJ–16
M SUFFIX
1
8
CASE 966
• High Speed: t = 7.0 ns (Typ) at V = 3.3 V
PD
CC
A
= Assembly Location
• Low Power Dissipation: I = 2 µA (Max) at T = 25°C
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• CMOS–Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
ORDERING INFORMATION
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
Device
Package
SO–16
Shipping
MC74LVX259D
MC74LVX259DR2
MC74LVX259DT
48 Units/Rail
SO–16
2500 Units/Reel
TSSOP–16 96 Units/Rail
MC74LVX259DTR2 TSSOP–16 2000 Units/Reel
MC74LVX259M
SO EIAJ–16 48 Units/Rail
SO EIAJ–16 2000 Units/Reel
MC74LVX259MEL
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
April, 2001 – Rev. 1
MC74LVX259/D
MC74LVX259
4
5
A0
A1
A2
1
2
3
16
15
14
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
A0
RESET
ADDRESS
INPUTS
6
A1
A2
7
NONINVERTING
OUTPUTS
ENABLE
9
Q0
Q1
4
5
13
12
DATA IN
Q7
10
11
12
13
DATA IN
Q2
Q3
6
7
11
10
Q6
Q5
PIN 16 = V
PIN 8 = GND
15
14
CC
RESET
GND
8
9
Q4
ENABLE
Figure 1. Pin Assignment
Figure 2. Logic Diagram
BIN/OCT
DMUX
1
1
2
3
4
5
6
7
8
4
A0
A1
A2
A0
A1
A2
1
2
4
0
1
2
3
4
5
Q0
Q1
Q2
Q3
Q4
0
2
0
1
2
3
Q0
0
7
5
6
7
8
2
3
G
Q1
Q2
Q3
Q4
4
5
10
11
12
13
14
15
10
11
12
13
14
15
ID
EN
R
ID
Q5
Q6
Q7
Q5
Q6
Q7
EN
R
6
7
6
7
Figure 3. IEC Logic Symbol
MODE SELECTION TABLE
Enable Reset Mode
LATCH SELECTION TABLE
Address Inputs
Latch
A
Addressed
C
B
L
H
Addressable Latch
H
L
H
L
Memory
L
L
L
L
L
Q0
Q1
8–Line Demultiplexer
H
H
L
Reset
L
L
H
H
L
Q2
Q3
H
H
H
H
H
L
L
L
H
L
Q4
Q5
Q6
Q7
H
H
H
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2
MC74LVX259
13
4
5
D
D
DATA INPUT
Q0
Q1
6
D
Q2
7
9
D
D
D
Q3
Q4
Q5
A0
3 TO 8
DECODER
ADDRESS
INPUTS
A1
A2
10
14
ENABLE
11
12
D
D
Q6
Q7
15
RESET
Figure 4. Expanded Logic Diagram
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3
MC74LVX259
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
Digital Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
IN
V
DC Output Voltage
–0.5 to V +0.5
V
OUT
CC
I
I
I
I
Input Diode Current
–20
$20
$25
$75
mA
mA
mA
mA
mW
IK
Output Diode Current
DC Output Current, per Pin
OK
OUT
CC
DC Supply Current, V and GND Pins
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
Storage Temperature Range
ESD Withstand Voltage
–65 to +150
°C
STG
V
Human Body Model (Note 2.)
Machine Model (Note 3.)
>2000
>200
V
ESD
Charged Device Model (Note 4.)
>2000
I
Latch–Up Performance
Above V and Below GND at 125°C (Note 5.)
$300
143
164
mA
LATCH–UP
CC
q
Thermal Resistance, Junction to Ambient
SOIC Package
TSSOP
°C/W
JA
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
3.6
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
V
0
V
CC
V
OUT
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
–40
0
85
100
°C
ns/V
A
t , t
r
V
= 3.3 V + 0.3 V
CC
f
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4
MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
–40°C ≤ T ≤ 85°C
A
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Unit
V
V
V
Minimum High–Level
Input Voltage
2.0
3.0
3.6
0.75 V
0.7 V
0.7 V
0.75 V
0.7 V
0.7 V
V
IH
CC
CC
CC
CC
CC
CC
Maximum Low–Level
Input Voltage
2.0
3.0
3.6
0.25 V
0.3 V
0.3 V
0.25 V
0.3 V
0.3 V
V
V
IL
CC
CC
CC
CC
CC
CC
I
= –50 µA
= –50 µA
= –4 mA
2.0
3.0
1.9
2.9
2.0
3.0
1.9
2.9
High–Level Output
Voltage
OH
OH
I
OH
I
3.0
2.58
2.48
OH
I
= 50 µA
2.0
0.0
0.0
0.1
0.1
0.1
0.1
V
OL
Low–Level Output
Voltage
V
OL
I
OL
= 50 µA
3.0
I
= 4 mA
3.0
0.36
±0.1
2.0
0.44
±1.0
OL
I
I
Input Leakage Current
V
V
= 5.5 V or GND
0 to 3.6
3.6
µA
µA
IN
IN
IN
Maximum Quiescent
Supply Current
= V or GND
1.0
1.0
CC
CC
(per package)
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
–40°C ≤ T ≤ 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
C = 15pF
C = 50pF
L
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
t
t
,
,
,
Maximum Propagation Delay,
Data to Output
(Figures 5 and 9)
ns
L
PLH
PHL
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
C = 15pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
t
t
Maximum Propagation Delay,
Address Select to Output
(Figures 6 and 9)
ns
ns
ns
L
PLH
PHL
C = 50pF
L
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
C = 15pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
t
t
Maximum Propagation Delay,
Enable to Output
(Figures NO TAG and 9)
L
PLH
PHL
C = 50pF
L
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
C = 15pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
t
Maximum Propogation Delay,
Reset to Output
(Figures 7 and 9)
L
PHL
C = 50pF
L
= 3.3 V ± 0.3 V
C = 15pF
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
C
C
Maximum Input Capacitance
6
10
10
pF
pF
IN
Typical @ 25°C, V = 3.3 V
CC
30
Power Dissipation Capacitance (Note 6.)
PD
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no–load dynamic
PD CC in CC PD
CC(OPR
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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5
MC74LVX259
TIMING REQUIREMENTS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T = ≤ 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
= 2.7 V
4.5
5.0
t
Minimum Pulse Width,
Reset or Enable
(Figure 8)
ns
CC
w
su
h
V
V
V
V
= 3.3 V ± 0.3 V
4.5
4.0
3.0
2.0
2.0
5.0
4.0
3.0
2.0
2.0
CC
CC
CC
CC
V
CC
= 2.7 V
t
t
Minimum Setup Time,
Address or Data to Enable
(Figure 8)
ns
ns
ns
= 3.3 V ± 0.3 V
= 2.7 V
V
CC
Minimum Hold Time,
Enable to Address or Data
(Figure 7 or 8)
= 3.3 V ± 0.3 V
= 2.7 V
V
CC
400
300
300
300
t t
r,
Maximum Input,
Rise and Fall Times
(Figure 5)
f
= 3.3 V ± 0.3 V
V
CC
DATA
IN
GND
t
f
t
r
V
ADDRESS
SELECT
CC
V
CC
50%
50%
50%
DATA
IN
GND
GND
t
t
PLH
PHL
V
CC
GND
50%
t
t
PHL
PHL
OUTPUT
Q
OUTPUT
Q
50%
Figure 5. Switching Waveform
Figure 6. Switching Waveform
V
CC
V
CC
GND
DATA IN
ENABLE
DATA IN
RESET
GND
t
t
w
w
t
w
V
CC
V
CC
50%
50%
50%
50%
GND
GN
D
t
t
PHL
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 7. Switching Waveform
Figure 8. Switching Waveform
TEST POINT
OUTPUT
DATA IN OR
ADDRESS
SELECT
V
CC
50%
DEVICE
UNDER
TEST
GND
t
h(H)
t
C *
L
h(H)
t
su
t
su
ENABLE
V
CC
50%
GND
*Includes all probe and jig capacitance
Figure 9. Switching Waveform
Figure 10. Test Circuit
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6
MC74LVX259
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008”)
P
0
K
t
P
2
D
TOP
COVER
TAPE
E
SEE NOTE 7.
A
0
F
W
+
+
+
K
0
B
0
B
1
SEE
NOTE 7.
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER
LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004”) MAX.
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS “R”
WITHOUT DAMAGE
EMBOSSED
CARRIER
EMBOSSMENT
BENDING RADIUS
100 mm
(3.937”)
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039”) MAX
250 mm
(9.843”)
TYPICAL
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
COMPONENT
CENTER LINE
7. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
Figure 11. Carrier Tape Specifications
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7
MC74LVX259
EMBOSSED CARRIER DIMENSIONS (See Notes 8. and 9.)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
8 mm
4.35 mm
(0.179”)
1.0 mm
Min
3.5 mm
±0.5
2.4 mm
Max
4.0 mm
±0.10
25 mm
(0.98”)
8.3 mm
(0.327)
1.5 mm
+ 0.1
1.75 mm
±0.1
4.0 mm
±0.1
2.0 mm
±0.1
0.6 mm
(0.024)
(0.179”)
(1.38
±0.002”)
(0.094”)
(0.157
±0.004”)
–0.0
(0.069
±0.004”)
(0.157
±0.004”)
(0.079
±0.004”)
(0.059”
+0.004
–0.0)
12 mm
8.2 mm
(0.323”)
5.5 mm
±0.5
6.4 mm
Max
4.0 mm
±0.10
12.0 mm
±0.3
1.5 mm
Min
30 mm
(1.18”)
(0.217
±0.002”)
(0.252”)
(0.157
(0.470
±0.012”)
(0.060)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
16 mm 12.1 mm
(0.476”)
7.5 mm
±0.10
7.9 mm
Max
4.0 mm
±0.10
16.3 mm
(0.642)
(0.295
(0.311”)
(0.157
±0.004”)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.0 mm
±0.10
(0.472
±0.004”)
24 mm 20.1 mm
(0.791”)
11.5 mm
±0.10
11.9 mm
Max
16.0 mm
±0.10
24.3 mm
(0.957)
(0.453
(0.468”)
(0.63
±0.004”)
±0.004”)
8. Metric Dimensions Govern–English are in parentheses for reference only.
9. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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8
MC74LVX259
t MAX
13.0 mm ±0.2 mm
(0.512” ±0.008”)
1.5 mm MIN
(0.06”)
20.2 mm MIN
(0.795”)
50 mm MIN
(1.969”)
A
FULL RADIUS
G
Figure 12. Reel Dimensions
REEL DIMENSIONS
Tape Size
T&R Suffix
A Max
G
t Max
8 mm
T1, T2
178 mm
(7”)
8.4 mm, +1.5 mm, –0.0
(0.33” + 0.059”, –0.00)
14.4 mm
(0.56”)
8 mm
T3, T4
R2
330 mm
(13”)
8.4 mm, +1.5 mm, –0.0
(0.33” + 0.059”, –0.00)
14.4 mm
(0.56”)
12 mm
16 mm
24 mm
330 mm
(13”)
12.4 mm, +2.0 mm, –0.0
(0.49” + 0.079”, –0.00)
18.4 mm
(0.72”)
R2
360 mm
(14.173”)
16.4 mm, +2.0 mm, –0.0
(0.646” + 0.078”, –0.00)
22.4 mm
(0.882”)
R2
360 mm
(14.173”)
24.4 mm, +2.0 mm, –0.0
(0.961” + 0.078”, –0.00)
30.4 mm
(1.197”)
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 13. Reel Winding Direction
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9
MC74LVX259
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 14. Tape Ends for Finished Goods
User Direction of Feed
Figure 15. TSSOP and SOIC R2 Reel Configuration/Orientation
TAPE UTILIZATION BY PACKAGE
SC88A / SOT–353
SC88/SOT–363
Tape Size
8 mm
SOIC
TSSOP
QFN
5–, 6–Lead
12 mm
16 mm
24 mm
8–Lead
8–, 14–, 16–Lead
20–, 24–Lead
48–, 56–Lead
8–, 14–, 16–Lead
20–, 24–Lead
48–, 56–Lead
14–, 16–Lead
18–, 20–, 24–, 28–Lead
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10
MC74LVX259
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
B
–U–
SECTION N–N
L
J
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
PIN 1
IDENT.
8
1
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
N
0.25 (0.010)
S
0.15 (0.006) T U
A
M
–V–
N
F
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
A
B
4.90
4.30
---
0.193
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
–W–
C
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
0.10 (0.004)
J1
K
H
DETAIL E
SEATING
PLANE
–T–
D
G
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
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11
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