MC74VHC08MEL [ONSEMI]
Quad 2−Input AND Gate; 四2输入与门
| 型号： | MC74VHC08MEL |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2−Input AND Gate |
| 文件： | 总6页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC08
Quad 2−Input AND Gate
The MC74VHC08 is an advanced high speed CMOS 2−input AND
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
Features
• High Speed: t = 4.3 ns (Typ) at V = 5.0 V
PD
CC
14
1
• Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C
CC
A
SOIC−14
D SUFFIX
CASE 751A
VHC08G
AWLYWW
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
14
OLP
VHC
08
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
TSSOP
DT SUFFIX
CASE 948G
ALYW
ꢀ
ꢀ
• ESD Performance:
1
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
14
• Pb−Free Packages are Available*
SOEIAJ−14
M SUFFIX
CASE 965
74VHC08
ALYWG
1
A1
3
Y1
2
1
B1
4
A2
A
= Assembly Location
WL, L = Wafer Lot
= Year
6
Y2
5
B2
Y
Y = AB
9
WW, W = Work Week
G or ꢀ = Pb−Free Package
A3
8
Y3
10
B3
12
A4
(Note: Microdot may be in either location)
11
Y4
13
FUNCTION TABLE
B4
Inputs
Output
Figure 1. Logic Diagram
A
B
Y
V
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
CC
L
L
L
H
L
L
L
14
H
H
L
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2 GND
(Top View)
Figure 2. Pinout: 14−Lead Packages
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2005 − Rev. 6
MC74VHC08/D
MC74VHC08
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
–0.5 to V +0.5
V
out
IK
CC
I
−20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
I
in
OK
V
out
should be constrained to the
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
out
CC
range GND v (V or V ) v V
.
CC
in
out
Unused inputs must always be
tied to an appropriate logic voltage
I
50
CC
†
†
P
Power Dissipation in Still Air,
SOIC Packages
TSSOP Package
500
450
D
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
–65 to +150
ꢁ
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — SOIC Packages: – 7 mW/ꢁ C from 65ꢁ to 125ꢁ C
TSSOP Package: − 6.1 mW/ꢁ C from 65ꢁ to 125ꢁ C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
in
5.5
V
V
out
0
V
V
CC
T
Operating Temperature
Input Rise and Fall Time
−40
+85
ꢁ
C
A
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
ns/V
f
CC
CC
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
1.50
V
IH
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
Minimum High−Level
Output Voltage
V
= V or V
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
OH
in
IH
IL
IL
I
OH
V
in
= V or V
IH
I
I
= −4.0 mA
= −8.0 mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
Maximum Low−Level
Output Voltage
V
= V or V
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IH
IL
I
OL
V
in
= V or V
IH
IL
I
I
= 4.0 mA
= 8.0 mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
I
Maximum Input Leakage
Current
V
V
= 5.5 V or GND
0 to 5.5
0.1
1.0
mA
mA
in
in
I
Maximum Quiescent
Supply Current
= V or GND
5.5
2.0
20.0
CC
in
CC
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2
MC74VHC08
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Unit
t
,
Maximum Propagation Delay,
A or B to Y
V
V
6.2
8.7
8.8
12.3
1.0
1.0
10.5
14.0
ns
PLH
CC
CC
L
t
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
4.3
5.8
5.9
7.9
1.0
1.0
7.0
9.0
L
C = 50 pF
L
C
Maximum Input Capacitance
4
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
18
C
PD
Power Dissipation Capacitance (Note 1)
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
CC
D
PD
CC
in
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Characteristic
Unit
V
Quiet Output Maximum Dynamic V
0.3
0.8
−0.8
3.5
V
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
V
V
V
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
IHD
V
1.5
ILD
TEST
POINT
V
CC
A or B
50%
OUTPUT
DEVICE
UNDER
TEST
GND
C *
L
t
t
PLH
PHL
Y
50% V
CC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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3
MC74VHC08
ORDERING INFORMATION
†
Device
MC74VHC08DR2
Package
Shipping
SOIC−14
2500 Units / Tape & Reel
2500 Units / Tape & Reel
MC74VHC08DR2G
SOIC−14
(Pb−Free)
MC74VHC08DTR2
MC74VHC08DTR2G
MC74VHC08MEL
MC74VHC08MELG
TSSOP−14*
TSSOP−14*
SOEIAJ−14
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2000 Units / Tape & Reel
2000 Units / Tape & Reel
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHC08
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45ꢁ
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
1.27 BSC
0.19
0.10
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T B
A
0 ꢁ
5.80
0.25
7ꢁ
0 ꢁ
7ꢁ
6.20 0.228 0.244
0.50 0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
0 ꢁ
8 ꢁ
0 ꢁ
8 ꢁ
D
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5
MC74VHC08
PACKAGE DIMENSIONS
SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
H
E
E
ꢁ
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
7
1
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
A
e
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
A
−−−
0.05
0.35
0.10
9.90
5.10
b
A
1
A
1
b
c
0.002
0.008
0.020
0.008
0.413
0.215
0.014
0.004
0.390
0.201
M
0.13 (0.005)
0.10 (0.004)
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
0.50
L
E
10ꢁ
0.90
1.42
ꢁ
M
0
0.70
0
0.028
10ꢁ
0.035
−−− 0.056
ꢁ
Q
1
Z
−−−
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MC74VHC08/D
相关型号：
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