MC74VHCT139AMG [ONSEMI]
Dual 2−to−4 Decoder/ Demultiplexer; 双路2至4解码器/多路解复用器
| 型号： | MC74VHCT139AMG |
| 厂家： | 
ONSEMI |
| 描述： | Dual 2−to−4 Decoder/ Demultiplexer |
| 文件： | 总7页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT139A
Dual 2−to−4 Decoder/
Demultiplexer
The MC74VHCT139A is an advanced high speed CMOS 2−to−4
decoder/demultiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL devices while maintaining CMOS low power
dissipation.
When the device is enabled (E = low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device output is compatible with TTL−type input thresholds
and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic
to 3.0 V CMOS logic while operating at the high−voltage power
supply
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MARKING
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
VHCT139AG
AWLYWW
1
16
VHCT
139A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
The MC74VHCT139A input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHCT139A to be used to interface 5.0 V circuits to
3.0 V circuits. The output structures also provide protection when
1
1
16
V
CC
= 0 V. These input and output structures help prevent device
SOEIAJ−16
M SUFFIX
CASE 966
destruction caused by supply voltage−input/output voltage mismatch,
battery backup, hot insertion, etc.
74VHCT139
ALYWG
1
1
Features
• High Speed: t = 5.0 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 4 mΑ (Max) at T = 25°C
CC
A
A
WL, L
Y
= Assembly Location
= Wafer Lot
= Year
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
FUNCTION TABLE
Inputs
A1 A0
Outputs
• ESD Performance:
E
Y0 Y1 Y2 Y3
Human Body Model > 2000 V;
Machine Model > 200 V
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
• Chip Complexity: 100 FETs or 25 Equivalent Gates
• Pb−Free Packages are Available*
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
January, 2006 − Rev. 4
MC74VHCT139A/D
MC74VHCT139A
2
4
5
6
7
A0a
A1a
Y0a
Y1a
Y2a
Y3a
ADDRESS
INPUTS
3
ACTIVE−LOW
OUTPUTS
Ea
1
2
16
15
V
CC
A0a
Eb
3
4
14
13
A1a
Y0a
Y1a
Y2a
A0b
A1b
Y0b
1
Ea
5
6
7
8
12
11
10
9
14
13
12
11
10
9
Y1b
Y2b
Y3b
ADDRESS
INPUTS
A0b
A1b
Y0b
Y1b
Y2b
Y3b
Y3a
ACTIVE−LOW
OUTPUTS
GND
Figure 1. Pin Assignment
15
Eb
Figure 2. Logic Diagram
En
A0
Y0
Y1
Y2
Y3
A1
Figure 3. Expanded Logic Diagram
(1/2 of Device)
X/Y
DMUX
3
2
1
3
2
1
4
5
4
5
A1a
A0a
Ea
Y0a A1a
Y1a A0a
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
1
2
0
1
2
3
0
1
0
1
2
3
0
3
G
6
7
6
7
Y2a
Y3a
Y0b
Ea
EN
INPUT
12
11
10
9
12
11
10
9
13
14
15
13
14
15
A1b
A0b
Eb
Y1b A1b
A0b
Eb
Y2b
Y3b
Figure 5. IEC Logic Diagram
Figure 4. Input Equivalent Circuit
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2
MC74VHCT139A
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
CC
V
V
IN
V
DC Output Voltage
Output in 3−State
V
OUT
High or Low State
−0.5 to V +0.5
CC
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
I
Output Diode Current
DC Output Current, per Pin
OK
I
OUT
I
DC Supply Current, V and GND Pins
CC
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
V
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
Human Body Model (Note 2)
Machine Model (Note 3)
>2000
>200
V
ESD
Charged Device Model (Note 4)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
$300
143
164
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
°C/W
JA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
4.5
0
Max
5.5
5.5
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
CC
V
V
IN
V
DC Output Voltage Output in 3−State
High or Low State
0
0
V
OUT
V
CC
T
Operating Temperature Range, all Package Types
−55
0
125
20
°C
A
t , t
r
Input Rise or Fall Time
V = 5.0 V + 0.5 V
CC
ns/V
f
DEVICE JUNCTION TEMPERATURE VERSUS TIME
TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 6. Failure Rate vs. Time Junction Temperature
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3
MC74VHCT139A
DC CHARACTERISTICS (Voltages Referenced to GND)
V
T
A
= 25°C
T
A
≤ 85°C
T = − 55 to
A
CC
125°C
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
Minimum High−Level Input
Voltage
4.5 to 5.5
2
2
2
V
IH
V
Maximum Low−Level Input
Voltage
4.5 to 5.5
0.8
0.8
0.8
V
V
IL
V
= V or V
= −50 mA
V
Maximum High−Level
Output Voltage
IN
IH
IL
IL
IL
IL
OH
I
4.5
4.5
4.5
4.4
4.5
0
4.4
3.8
4.4
OH
V
= V or V
IN
IH
I
= −8 mA
3.94
3.66
OH
V
= V or V
V
Maximum Low−Level
Output Voltage
V
IN
IH
OL
I
= 50 mA
0.1
0.1
0.1
OL
V
= V or V
IN
IH
I
= 8 mA
4.5
0 to 5.5
5.5
0.36
0.1
0.44
1.0
0.52
1.0
OH
I
Input Leakage Current
V
V
= 5.5 V or GND
mA
mA
IN
IN
IN
I
Maximum Quiescent
Supply Current
= V or GND
4.0
40.0
40.0
CC
CC
I
Additional Quiescent
Supply Current (per Pin)
Any one input:
= 3.4 V
All other inputs:
5.5
1.35
0.5
1.5
5
1.5
5
mA
CCT
V
IN
V
= V or GND
IN
CC
I
Output Leakage Current
V
= 5.5 V
0
mA
OPD
OUT
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= − 55 to
125°C
T
A
= 25°C
T ≤ 85°C
A
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Min
Typ
Max
Min
Max
Min
Max
Unit
t
,
Maximum Propagation
Delay, A to Y
V
V
V
V
7.2
9.7
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
13.0
16.5
ns
PLH
CC
CC
CC
CC
L
t
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
5.0
6.5
7.2
9.2
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
L
C = 50 pF
L
t
,
Maximum Propagation
Delay, E to Y
= 3.3 0.3 V C = 15 pF
6.4
8.9
9.2
12.7
1.0
1.0
11.0
14.5
1.0
1.0
11.0
14.5
ns
PLH
L
t
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
4.4
5.9
6.3
8.3
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
L
C = 50 pF
L
C
Maximum Input
Capacitance
4
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0V
CC
26
C
PD
Power Dissipation Capacitance (Note 6)
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /2 (per decoder). C is used to determine the
CC(OPR
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
in
.
CC
D
PD
CC
CC
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4
MC74VHCT139A
3.0 V
GND
3.0 V
GND
A
Y
E
1.5 V
1.5 V
t
PHL
t
t
PLH
t
PHL
PLH
V
V
OH
OH
1.5 V
1.5 V
Y
V
V
OL
OL
Figure 7. Switching Waveform
Figure 8. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 9. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHCT139AD
MC74VHCT139ADG
SOIC−16
48 Units / Rail
48 Units / Rail
SOIC−16
(Pb−Free)
MC74VHCT139ADR2
MC74VHCT139ADR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74VHCT139ADT
MC74VHCT139ADTG
MC74VHCT139ADTR2
MC74VHCT139ADTRG
MC74VHCT139AM
TSSOP−16*
TSSOP−16*
TSSOP−16*
TSSOP−16*
SOEIAJ−16
96 Units / Rail
96 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
50 Units / Rail
MC74VHCT139AMG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74VHCT139AMEL
MC74VHCT139AMELG
SOEIAJ−16
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74VHCT139A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T B
A
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
F
D
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
−T−
D
PLANE
G
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6
MC74VHCT139A
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
F
D
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHCT139A/D
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