MMBT4126LT1 [ONSEMI]
General Purpose Transistor PNP Silicon; 通用晶体管PNP硅
| 型号： | MMBT4126LT1 |
| 厂家： | 
ONSEMI |
| 描述： | General Purpose Transistor PNP Silicon |
| 文件： | 总8页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MMBT4126LT1
Preferred Device
General Purpose Transistor
PNP Silicon
• Moisture Sensitivity Level: 1
• ESD Rating – Human Body Model: >4000 V
ESD Rating – Machine Model: >400 V
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MAXIMUM RATINGS
COLLECTOR
3
Rating
Symbol
Value
–25
Unit
Vdc
Collector–Emitter Voltage
Collector–Base Voltage
Emitter–Base Voltage
V
CEO
V
CBO
V
EBO
1
BASE
–25
Vdc
–4
Vdc
Collector Current–Continuous
THERMAL CHARACTERISTICS
Characteristic
I
–200
mAdc
C
2
EMITTER
Symbol
Max
Unit
Total Device Dissipation FR–5 Board
(Note 1.)
P
D
225
mW
3
T = 25°C
A
Derate above 25°C
1.8
mW/°C
°C/W
1
Thermal Resistance,
R
556
q
2
JA
Junction to Ambient (Note 1.)
SOT–23
CASE 318
STYLE 6
Total Device Dissipation
Alumina Substrate, (Note 2.)
T = 25°C
A
P
D
300
mW
Derate above 25°C
2.4
mW/°C
°C/W
MARKING DIAGRAM
C3 M
Thermal Resistance,
R
417
q
JA
Junction to Ambient (Note 2.)
Junction and Storage
Temperature Range
T , T
–55 to
+150
°C
J
stg
1. FR–5 = 1.0 ꢀ 0.75 ꢀ 0.062 in.
2. Alumina = 0.4 ꢀ 0.3 ꢀ 0.024 in. 99.5% alumina.
C3 = Device Code
M
= Date Code
ORDERING INFORMATION
Device
MMBT4126LT1
Package
Shipping
3000/Tape & Reel
SOT–23
Preferred devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
March, 2001 – Rev. 0
MMBT4126LT1/D
MMBT4126LT1
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Max
Unit
Collector–Emitter Breakdown Voltage (Note 3.)
V
Vdc
Vdc
(BR)CEO
(BR)CBO
(BR)EBO
(I = –1.0 mAdc, I = 0)
–25
–25
–4
–
–
C
B
Collector–Base Breakdown Voltage
(I = –10 mAdc, I = 0)
V
V
C
E
Emitter–Base Breakdown Voltage
(I = –10 mAdc, I = 0)
Vdc
–
E
C
Collector Cutoff Current
(V = –30 Vdc, V = –3.0 Vdc)
I
nAdc
CEX
–
–50
CE
EB
ON CHARACTERISTICS (Note 3.)
DC Current Gain
H
–
FE
(I = –2.0 mAdc, V = –1.0 Vdc)
120
60
300
–
C
CE
(I = –50 mAdc, V = –1.0 Vdc)
C
CE
Collector–Emitter Saturation Voltage
(I = –50 mAdc, I = –5.0 mAdc)
V
Vdc
Vdc
CE(sat)
–
–
–0.4
C
B
Base–Emitter Saturation Voltage
(I = –50 mAdc, I = –5.0 mAdc)
V
BE(sat)
–0.95
C
B
SMALL–SIGNAL CHARACTERISTICS
Current–Gain – Bandwidth Product
f
MHz
pF
pF
–
T
(I = –10 mAdc, V = –20 Vdc, f = 100 MHz)
250
–
–
C
CE
Output Capacitance
C
obo
(V = –5.0 Vdc, I = 0, f = 1.0 MHz)
4.5
10
CB
E
Input Capacitance
C
ibo
(V = –0.5 Vdc, I = 0, f = 1.0 MHz)
–
EB
C
Small–Signal Current Gain
(I = –2.0 mAdc, V = –10 Vdc, f = 1.0 kHz)
h
fe
120
2.5
480
–
C
CE
(I = 10 mAdc, V = 20 Vdc, f = 100 MHz)
C
CE
Noise Figure
NF
dB
(I = –100 mAdc, V = –5.0 Vdc, R = 1.0 kΩ, f = 1.0 kHz)
–
4.0
C
CE
S
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
TYPICAL TRANSIENT CHARACTERISTICS
T = 25°C
J
T = 125°C
J
10
5000
V
CC
I /I = 10
= 40 V
3000
2000
7.0
C B
C
5.0
obo
1000
700
C
ibo
500
3.0
2.0
300
200
Q
T
Q
A
100
70
1.0
0.1
50
0.2 0.3 0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
20 30 40
1.0
2.0 3.0 5.0 7.0 10
20 30 50 70 100
200
REVERSE BIAS (VOLTS)
I , COLLECTOR CURRENT (mA)
C
Figure 1. Capacitance
Figure 2. Charge Data
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2
MMBT4126LT1
TYPICAL AUDIO SMALL–SIGNAL CHARACTERISTICS
NOISE FIGURE VARIATIONS
(VCE = –5.0 Vdc, TA = 25°C, Bandwidth = 1.0 Hz)
5.0
4.0
3.0
2.0
1.0
0
12
SOURCE RESISTANCE = 200 W
= 1.0 mA
f = 1.0 kHz
I
= 1.0 mA
C
I
C
10
8
I
C
= 0.5 mA
SOURCE RESISTANCE = 200 W
= 0.5 mA
I
C
SOURCE RESISTANCE = 2.0 k
= 50 mA
6
I
C
4
I
= 50 mA
C
SOURCE RESISTANCE = 2.0 k
= 100 mA
I
= 100 mA
C
2
I
C
0
0.1 0.2
0.4
1.0 2.0 4.0
10
20
40
100
0.1 0.2
0.4
1.0 2.0
4.0
10
20
40
100
f, FREQUENCY (kHz)
R , SOURCE RESISTANCE (k OHMS)
g
Figure 3.
Figure 4.
h PARAMETERS
(VCE = –10 Vdc, f = 1.0 kHz, TA = 25°C)
300
200
100
70
50
30
20
100
70
10
7
50
30
5
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 5. Current Gain
Figure 6. Output Admittance
20
10
10
7.0
5.0
7.0
5.0
3.0
2.0
3.0
2.0
1.0
0.7
0.5
1.0
0.7
0.5
0.3
0.2
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 7. Input Impedance
Figure 8. Voltage Feedback Ratio
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3
MMBT4126LT1
TYPICAL STATIC CHARACTERISTICS
2.0
1.0
T = +125°C
J
V
CE
= 1.0 V
+25°C
-ā55°C
0.7
0.5
0.3
0.2
0.1
0.1
0.2
0.3
0.5 0.7
1.0
2.0
3.0
5.0 7.0 10
20
30
50
70 100
200
I , COLLECTOR CURRENT (mA)
C
Figure 9. DC Current Gain
1.0
0.8
0.6
0.4
T = 25°C
J
I
C
= 1.0 mA
10 mA
30 mA
100 mA
0.2
0
0.01
0.02
0.03
0.05 0.07 0.1
0.2
0.3
0.5
0.7
1.0
2.0
3.0
5.0
7.0
10
I , BASE CURRENT (mA)
B
Figure 10. Collector Saturation Region
1.0
0.8
0.6
1.0
T = 25°C
J
V
@ I /I = 10
BE(sat) C B
0.5
0
+25°C TO +125°C
-ā55°C TO +25°C
q
FOR V
CE(sat)
VC
V
BE
@ V = 1.0 V
CE
-ā0.5
-ā1.0
+25°C TO +125°C
-ā55°C TO +25°C
0.4
0.2
0
V
@ I /I = 10
C B
CE(sat)
q
FOR V
BE(sat)
VB
-ā1.5
-ā2.0
1.0
2.0 5.0
10
20
50
100
200
0
20
40
60
80 100 120 140 160 180 200
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 11. “ON” Voltages
Figure 12. Temperature Coefficients
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4
MMBT4126LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
drain pad size. This can vary from the minimum pad size
for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
into the equation for an ambient temperature T of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
A
150°C – 25°C
556°C/W
PD =
= 225 milliwatts
determined by T
, the maximum rated junction
J(max)
temperature of the die, R , the thermal resistance from
the device junction to ambient, and the operating
θJA
The 556°C/W for the SOT–23 package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts.
There are other alternatives to achieving higher power
dissipation from the SOT–23 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad . Using a board material such
as Thermal Clad, an aluminum core board, the power
dissipation can be doubled using the same footprint.
temperature, T . Using the values provided on the data
A
sheet for the SOT–23 package, P can be calculated as
D
follows:
TJ(max) – TA
PD =
Rθ
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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5
MMBT4126LT1
PACKAGE DIMENSIONS
SOT–23
TO–236AB
CASE 318–09
ISSUE AF
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
ąă2. CONTROLLING DIMENSION: INCH.
ąă3. MAXIUMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
L
3
B
S
INCHES
DIM MIN MAX
MILLIMETERS
1
2
MIN
2.80
1.20
0.99
0.36
1.70
0.10
MAX
3.04
1.40
1.26
0.50
2.10
0.25
0.177
0.60
1.02
2.50
0.60
A
B
C
D
G
H
J
0.1102 0.1197
0.0472 0.0551
0.0385 0.0498
0.0140 0.0200
0.0670 0.0826
0.0040 0.0098
V
G
0.0034 0.0070 0.085
K
L
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
0.45
0.89
2.10
0.45
C
S
V
J
H
K
D
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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6
MMBT4126LT1
Notes
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7
MMBT4126LT1
Thermal Clad is a registered trademark of the Bergquist Company
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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CENTRAL/SOUTH AMERICA:
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For additional information, please contact your local
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MMBT4126LT1/D
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