MMBT5089LT1 [ONSEMI]
Low Noise Transistors; 低噪声晶体管
| 型号： | MMBT5089LT1 |
| 厂家： | 
ONSEMI |
| 描述： | Low Noise Transistors |
| 文件： | 总8页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductort
MMBT5088LT1
Low Noise Transistors
NPN Silicon
MMBT5089LT1
MMBT5089LT1 is a Preferred Device
3
MAXIMUM RATINGS
1
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Symbol
5088LT1 5089LT1
Unit
Vdc
2
V
CEO
V
CBO
V
EBO
30
35
25
30
Vdc
CASE 318–08, STYLE 6
SOT–23 (TO–236AF)
Emitter–Base Voltage
4.5
50
Vdc
Collector Current — Continuous
THERMAL CHARACTERISTICS
Characteristic
I
C
mAdc
COLLECTOR
3
Symbol
Max
Unit
1
(1)
Total Device Dissipation FR–5 Board
P
225
mW
D
BASE
T
= 25°C
A
Derate above 25°C
1.8
556
300
mW/°C
°C/W
mW
2
Thermal Resistance, Junction to Ambient
Total Device Dissipation
R
qJA
EMITTER
P
D
(2)
Alumina Substrate,
T
A
= 25°C
Derate above 25°C
2.4
mW/°C
°C/W
°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
R
417
qJA
T , T
J stg
–55 to +150
MMBT5088LT1 = 1Q; MMBT5089LT1 = 1R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
V
Vdc
(BR)CEO
(I = 1.0 mAdc, I = 0)
MMBT5088
MMBT5089
30
25
—
—
C
B
Collector–Base Breakdown Voltage
(I = 100 mAdc, I = 0)
V
Vdc
nAdc
nAdc
(BR)CBO
MMBT5088
MMBT5089
35
30
—
—
C
E
Collector Cutoff Current
I
CBO
(V
CB
(V
CB
= 20 Vdc, I = 0)
MMBT5088
MMBT5089
—
—
50
50
E
= 15 Vdc, I = 0)
E
Emitter Cutoff Current
I
EBO
(V
EB(off)
(V
EB(off)
= 3.0 Vdc, I = 0)
MMBT5088
MMBT5089
—
—
50
100
C
= 4.5 Vdc, I = 0)
C
1. FR–5 = 1.0 ꢀ 0.75 ꢀ 0.062 in.
2. Alumina = 0.4 ꢀ 0.3 ꢀ 0.024 in. 99.5% alumina.
Preferred devices are ON Semiconductor recommended choices for future use and best overall value.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
March, 2001 – Rev. 1
MMBT5088LT1/D
MMBT5088LT1 MMBT5089LT1
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
ON CHARACTERISTICS
Symbol
Min
Max
Unit
DC Current Gain
(I = 100 µAdc, V
C
h
FE
—
= 5.0 Vdc)
= 5.0 Vdc)
= 5.0 Vdc)
MMBT5088
MMBT5089
300
400
900
1200
CE
CE
CE
(I = 1.0 mAdc, V
C
MMBT5088
MMBT5089
350
450
—
—
(I = 10 mAdc, V
C
MMBT5088
MMBT5089
300
400
—
—
Collector–Emitter Saturation Voltage
(I = 10 mAdc, I = 1.0 mAdc)
V
V
Vdc
Vdc
CE(sat)
—
—
0.5
0.8
C
B
Base–Emitter Saturation Voltage
(I = 10 mAdc, I = 1.0 mAdc)
BE(sat)
C
B
SMALL–SIGNAL CHARACTERISTICS
Current–Gain — Bandwidth Product
f
C
C
MHz
pF
T
(I = 500 µAdc, V
C CE
= 5.0 Vdc, f = 20 MHz)
50
—
—
—
4.0
10
Collector–Base Capacitance
(V = 5.0 Vdc, I = 0, f = 1.0 MHz emitter guarded)
cb
eb
CB
Emitter–Base Capacitance
(V = 0.5 Vdc, I = 0, f = 1.0 MHz collector guarded)
E
pF
EB
C
Small Signal Current Gain
h
fe
—
(I = 1.0 mAdc, V
C
= 5.0 Vdc, f = 1.0 kHz)
MMBT5088
MMBT5089
350
450
1400
1800
CE
Noise Figure
NF
dB
(I = 100 mAdc, V
= 5.0 Vdc, R = 10 kΩ, f = 1.0 kHz)
MMBT5088
MMBT5089
—
—
3.0
2.0
C
CE
S
R
S
i
n
e
n
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
http://onsemi.com
2
MMBT5088LT1 MMBT5089LT1
NOISE CHARACTERISTICS
(V
= 5.0 Vdc, T = 25°C)
CE
A
NOISE VOLTAGE
30
20
30
BANDWIDTH = 1.0 Hz
BANDWIDTH = 1.0 Hz
20
I
C
= 10 mA
R
S
≈ 0
R
S
≈ 0
f = 10 Hz
10 kHz
3.0 mA
1.0 mA
10
7.0
5.0
10
7.0
5.0
100 Hz
1.0 kHz
300 µA
100 kHz
5.0
3.0
3.0
0.01 0.02
10 20 50 100 200 500 1Ăk 2Ăk 5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
f, FREQUENCY (Hz)
0.05 0.1
0.2
0.5 1.0
2.0
10
I , COLLECTOR CURRENT (mA)
C
Figure 2. Effects of Frequency
Figure 3. Effects of Collector Current
10
20
16
BANDWIDTH = 1.0 Hz
7.0
5.0
I
C
= 10 mA
3.0
2.0
BANDWIDTH = 10 Hz to 15.7 kHz
3.0 mA
12
8.0
4.0
0
1.0 mA
300 µA
100 µA
30 µA
1.0
0.7
0.5
I
C
= 1.0 mA
500 µA
100 µA
10 µA
0.3
0.2
10 µA
R
S
≈ 0
0.1
10 20 50 100 200 500 1Ăk 2Ăk 5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
f, FREQUENCY (Hz)
10 20
50 100 200 500 1Ăk 2Ăk
5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
R , SOURCE RESISTANCE (OHMS)
S
Figure 4. Noise Current
Figure 5. Wideband Noise Figure
100 Hz NOISE DATA
300
200
20
BANDWIDTH = 1.0 Hz
I = 10 mA
C
3.0 mA
16
12
I
C
= 10 mA
100 µA
3.0 mA
1.0 mA
100
70
1.0 mA
50
30
20
300 µA
300 µA
8.0
30 µA
100 µA
30 µA
10
10 µA
4.0
0
7.0
5.0
10 µA
BANDWIDTH = 1.0 Hz
3.0
10 20
50 100 200 500 1Ăk 2Ăk 5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
10 20
50 100 200 500 1Ăk 2Ăk 5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
R , SOURCE RESISTANCE (OHMS)
S
R , SOURCE RESISTANCE (OHMS)
S
Figure 6. Total Noise Voltage
Figure 7. Noise Figure
http://onsemi.com
3
MMBT5088LT1 MMBT5089LT1
4.0
3.0
V
CE
= 5.0 V
2.0
T
A
= 125°C
25°C
1.0
0.7
-ā55°C
0.5
0.4
0.3
0.2
0.01
0.02
0.03
0.05
0.1
0.2
0.3
0.5
1.0
2.0
3.0
5.0
10
I , COLLECTOR CURRENT (mA)
C
Figure 8. DC Current Gain
1.0
-ā0.4
-ā0.8
T
= 25°C
J
0.8
0.6
0.4
0.2
0
V
BE
@ V = 5.0 V
CE
-ā1.2
-ā1.6
-ā2.0
-ā2.4
T
= 25°C to 125°C
J
-ā55°C to 25°C
V
CE(sat)
@ I /I = 10
C B
0.01 0.02 0.05 0.1 0.2
1.0 2.0 5.0
0.01 0.02 0.05 0.1 0.2
1.0 2.0 5.0
0.5
10 20
50 100
0.5
10 20
50 100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 11. “On” Voltages
Figure 9. Temperature Coefficients
8.0
6.0
500
T
= 25°C
J
300
200
C
ob
C
ib
4.0
3.0
C
eb
C
cb
2.0
100
V
= 5.0 V
CE
70
50
T
= 25°C
J
1.0
0.8
0.1
0.2
1.0
2.0
5.0
1.0
2.0 3.0
5.0 7.0
0.5
10
20
50 100
10
20 30
50 70 100
V , REVERSE VOLTAGE (VOLTS)
R
I , COLLECTOR CURRENT (mA)
C
Figure 12. Capacitance
Figure 10. Current–Gain — Bandwidth Product
http://onsemi.com
4
MMBT5088LT1 MMBT5089LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
SOLDERING PRECAUTIONS
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
mined byT
of the die, R
, the maximum rated junction temperature
, the thermal resistance from the device
J(max)
θJA
junction to ambient, and the operating temperature, T .
A
Using the values provided on the data sheet for the SOT–23
package, P can be calculated as follows:
• Always preheat the device.
D
• The delta temperature between the preheat and
soldering should be 100°C or less.*
T
– T
A
J(max)
P
=
D
R
θJA
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T of 25°C,
A
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
150°C – 25°C
556°C/W
P
=
= 225 milliwatts
D
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
http://onsemi.com
5
MMBT5088LT1 MMBT5089LT1
PACKAGE DIMENSIONS
SOT–23 (TO–236)
CASE 318–08
ISSUE AF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
INCHES
DIM MIN MAX
MILLIMETERS
S
C
B
MIN
2.80
1.20
0.89
0.37
1.78
MAX
3.04
1.40
1.11
1
2
A
B
C
D
G
H
J
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
V
G
0.50
2.04
0.100
0.177
0.69
1.02
2.64
0.60
0.0005 0.0040 0.013
0.0034 0.0070 0.085
K
L
0.0140 0.0285
0.0350 0.0401
0.0830 0.1039
0.0177 0.0236
0.35
0.89
2.10
0.45
S
V
H
J
D
K
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
http://onsemi.com
6
MMBT5088LT1 MMBT5089LT1
Notes
http://onsemi.com
7
MMBT5088LT1 MMBT5089LT1
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
MMBT5088LT1/D
相关型号：
©2020 ICPDF网 联系我们和版权申明