N24S128C4DYT3G [ONSEMI]
128 Kb I2C CMOS Serial EEPROM with Software Write Protect and Programmable Device Address;
| 型号： | N24S128C4DYT3G |
| 厂家： | 
ONSEMI |
| 描述： | 128 Kb I2C CMOS Serial EEPROM with Software Write Protect and Programmable Device Address 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
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N24S128
128 Kb I2C CMOS Serial
EEPROM with Software
Write Protect and
Programmable Device
Address
www.onsemi.com
Description
The N24S128 is a 128 Kb Serial CMOS EEPROM, internally
organized as 816,384 words of 8 bits each.
WLCSP−4
C4 SUFFIX
CASE 567VY
They feature a 64-byte page write buffer and support both the
2
Standard (100 kHz), Fast (400 kHz) and Fast-Plus (1 MHz) I C
protocol.
PIN CONFIGURATION
The devices also feature a 128-bit factory-set read-only Unique ID,
a 64-byte Secure Data Page that can be permanently locked against
future changes, and Software Write Protection of the entire array.
A Device Configuration Register enables the user to specify the last
3 bits of the Device Address, allowing up to eight N24S128 devices to
be addressed on the same bus.
1
2
A
B
V
SCL
CC
SDA
V
SS
Features
(Top View)
2
• Supports Standard, Fast and Fast-Plus I C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 64-byte Page Write Buffer
PIN FUNCTION
Pin Name
SDA
Function
• Lockable Secure Data Page
• User Programmable Write Protection
• User Programmable Device Address
Serial Data Input/Output
Serial Clock Input
Power Supply
SCL
2
V
CC
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
V
SS
Ground
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
MARKING DIAGAM
X
YW
• Industrial Temperature Range: −40°C to +85°C
• Ultra-thin 4-ball WLCSP Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant*
X
= Specific Device Code
(See Ordering Information Table)
= Production Year (Last Digit)
= Production Week Code
Y
W
V
CC
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
N24S128
SCL
SDA
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
April, 2019 − Rev. 2
N24S128/D
N24S128
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 1.0 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Unit
Program/Erase Cycles
Years
N
Endurance
END
T
(Note 4)
Data Retention
DR
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25_C
CC
4. T = 55_C
A
Table 3. DC AND AC OPERATING CONDITIONS
Supply Voltage / Temperature Range
Operation
READ / WRITE
READ
V
CC
V
CC
V
CC
= 1.7 V to 5.5 V / T = −40°C to +85°C
A
= 1.6 V to 5.5 V / T = −40°C to +85°C
A
= 1.6 V to 5.5 V / T = 0°C to +85°C
WRITE
A
Table 4. D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Unit
mA
mA
mA
Read, f
= 400 kHz/1 MHz
Read Current
1
I
SCL
CCR
Write Current
2
I
CCW
All I/O Pins at GND or V
V
V
< 2.5 V
Standby Current
1
2
I
SB
CC
CC
> 2.5 V
CC
Pin at GND or V
I/O Pin Leakage
2
mA
V
I
CC
L
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
≥ 2.5 V
< 2.5 V
≥ 2.5 V
< 2.5 V
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
−0.5
−0.5
0.3 V
V
V
V
CC
IL1
IL2
0.25 V
V
CC
0.7 V
V
+ 1
V
CC
CC
CC
IH1
IH2
0.75 V
V
+ 1
V
V
CC
0.4
0.2
V
V
≥ 2.5 V, I = 3.0 mA
OL1
OL
V
V
< 2.5 V, I = 1.0 mA
OL2
OL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 5. PIN IMPEDANCE CHARACTERISTICS
Symbol
Parameter
Conditions
Max
8
Unit
pF
C
C
(Note 5)
(Note 5)
SDA I/O Pin Capacitance
Input Capacitance (other pins)
V
V
= 0 V
= 0 V
IN
IN
IN
6
pF
IN
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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2
N24S128
Table 6. A.C. CHARACTERISTICS (Note 6)
Standard
= 1.7 to 5.5
Fast
= 1.7 to 5.5
Fast−Plus
V = 1.7 to 5.5
CC
V
CC
V
CC
T
= −40 to 855C
T
= −40 to 855C
T
= −40 to 855C
A
A
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
kHz
ms
Clock Frequency
100
400
1,000
F
SCL
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
0.26
0.5
0.26
0.26
0
t
HD:STA
ms
t
LOW
ms
t
HIGH
ms
4.7
0
t
SU:STA
HD:DAT
ms
t
ns
Data In Setup Time
250
100
20
50
t
SU:DAT
ns
t
(Note 7)
SDA and SCL Rise Time
SDA and SCL Fall Time
1,000
300
300
300
100
100
R
ns
t (Note 7)
F
20
ms
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
4
0.6
1.3
0.25
0.5
t
SU:STO
ms
4.7
t
BUF
ms
3.5
0.9
0.40
t
AA
ns
100
100
50
t
DH
ns
T (Note 7)
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
100
5
50
5
50
5
i
ms
ms
t
WR
Power-up to Ready Mode
0.35
0.35
0.35
T
PU
(Notes 7, 8)
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 7. A.C. TEST CONDITIONS
Parameter
Condition
Input Levels
0.2 × V to 0.8 × V
CC CC
≤ 50 ns
0.3 × V , 0.7 × V
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
CC
CC
0.5 × V
CC
Current Source: I = 3 mA (V ≥ 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
Output Load
OL
CC
OL
CC
L
V
CC
10
1
R
P
300 ns Rise Time
SDA
120 ns Rise Time
C
L
V
SS
0.1
100
Load Capacitance (pF)
10
Figure 2. Maximum Pull-up Resistance vs. Load Capacitance
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3
N24S128
Power-On Reset (POR)
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
The N24S128 incorporates Power-On Reset (POR)
circuitry which protects the device against powering up in
the wrong state.
The N24S128 will power up into Standby mode after V
exceeds the POR trigger level and will power down into
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 3). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake-up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
CC
Reset mode when V drops below the POR trigger level.
CC
This bi-directional POR feature protects the device against
‘brown-out’ failure following a temporary loss of power.
Pin Description
• SCL: The Serial Clock input pin accepts the Serial
Clock generated by the Master.
Device Addressing
• SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode,
this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations, and to 1011
for special Read/Write operations (Figure 4). The next 3 bits
must match the A2, A1, A0 bits in the Device Configuration
Register. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.
Functional Description
The N24S128 supports the Inter-Integrated Circuit (I C)
2
Bus data transmission protocol, which defines a device that
sends data to the bus as a transmitter and a device receiving
data as a receiver. Data flow is controlled by a Master device,
which generates the serial clock and all START and STOP
conditions. The N24S128 acts as a Slave device. Master and
Slave alternate as either transmitter or receiver. Up to 8
devices may be connected to the bus as determined by the
The factory default for the A2, A1, A0 bits is 0.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
th
during the 9 clock cycle (Figure 5). The Slave will also
Device Address bits A , A , and A in the Device
0
1
2
acknowledge all address bytes and every data byte presented
in Write mode if the addressed location is not write
protected. In Read mode the Slave shifts out a data byte, and
Configuration Register.
I2C Bus Protocol
th
then releases the SDA line during the 9 clock cycle. As
2
The I C bus consists of two ‘wires’, SCL and SDA. The
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 6.
two wires are connected to the V supply via pull-up
CC
resistors. Master and Slave devices connect to the 2-wire bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 3. START/STOP Conditions
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4
N24S128
DEVICE ADDRESS
Memory Array Access
1
1
0
0
1
1
0
1
A2
A2
A1
A1
A0
A0
R/W
R/W
Secure Data Page ,
UID, Device Config.
Figure 4. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
(RECEIVER)
SCL FROM
MASTER
1
8
9
DAT A OUTPUT
FROM TRANSMITTER
DAT A OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 5. Acknowledge Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
t
DH
AA
SDA OUT
Figure 6. Bus Timing
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5
N24S128
Write Operations
Configuration register. The second byte consists of xxxx
x00x, where x is don’t care. The third byte indicates the
address within the Secure Data Page. Since the page is
64-bytes wide, the first 2 bits of the address are don’t care.
The remainder of the instruction is identical to a normal
Page Write.
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address (Table 8) and data to be
written (Figure 7). The Slave, N24S128 acknowledges all
4 bytes, and the Master then follows up with a STOP, which
in turn starts the internal Write operation (Figure 8). During
Secure Data Page Lock
the internal Write cycle (t ), the N24S128 will not
acknowledge any Read or Write request from the Master.
The Secure Data Page Lock instruction is similar to a Byte
Write instruction. To lock the Secure Data Page against
future changes, the user must address the device with the
header 1011 followed by the A2 A1 A0 bits that match the
bits in the Device Configuration register. The second byte
consists of xxxx x10x, where x is don’t care. The third byte
is don’t care.
The data byte following the address bytes must be all 1s
(FFh). After this instruction is sent, the user will be able to
read, but not to write the content of the Secure Data Page.
Any write instructions to the Secure Data Page will return
No ACK from the device.
WR
Page Write
The N24S128 contains 16,384 bytes of data, arranged in
256 pages of 64 bytes each. A two byte address word
(Table 8), following the Slave address, points to the first byte
to be written into the memory array. The most significant 8
bits from the address active bits (a13 to a6) identify the page
and the last 6 bits (a5 to a0) identify the byte within the page.
Up to 64 bytes can be written in one Write cycle (Figure 9).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap-around’ fashion (within
the selected page). The internal Write cycle starts
immediately following the STOP.
Device Configuration Register Write
The Device Configuration Register Write instruction is
similar to a Byte Write instruction. The user must address the
device with the header 1011b followed by the A2 A1 A0 bits
that match the bits in the Device Configuration register. The
second byte consists of xxxx x11x, where x is don’t care. The
third byte is don’t care.
The data byte following the address will be written into the
Device Configuration Register (see Table 9 for the position
of each bit.) The A2, A1, A0 bits determine the Device
Address.
The SWP bit is the Software Write Protection bit. When
SWP is set to 1, the memory array, the Secure Data Page and
the Device Configuration Register are protected against
write operations. The A2, A1, A0 bits cannot be overwritten
during a Device Configuration Register write operation if
SWP is set to 1. The SWP bit alone can be changed to 0.
The Device Configuration Register Write instruction does
not support acknowledge polling.
Acknowledge Polling
The ready/busy status of the N24S128 can be ascertained
by sending Read or Write requests immediately following
the STOP condition that initiated the internal Write cycle. As
long as internal Write is in progress, the N24S128 will not
acknowledge the Slave address.
The Device Configuration Register Write instruction does
not support acknowledge polling. Following this
instruction, the master must wait t
a new instruction.
= 5 ms before sending
WR
Secure Data Page Write
The Secure Data Page Write instruction is similar to a
Page Write instruction. To address the Secure Data Page, the
user must address the device with the header 1011 followed
by the A2 A1 A0 bits that match the bits in the Device
Table 8. MEMORY ADDRESS BYTES
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Memory Array
x
x
x
x
x
x
x
x
a13 a12 a11 a10
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
Secure Data Page
x
x
x
x
x
x
x
x
x
0
1
0
0
0
1
x
x
x
x
x
x
x
x
x
a5
x
a4
x
a3
x
a2
x
a1
x
a0
x
Secure Page Lock Bit
Unique ID Number
(read−only)
x
x
0
0
0
0
Device Configuration
x
x
x
x
x
1
1
x
x
x
x
x
x
x
x
x
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6
N24S128
Table 9. DEVICE CONFIGURATION REGISTER
b7
b6
b5
b4
b3
b2
b1
b0
A2
A1
A0
x
x
x
SWP
x
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE
a −a
7 0
S
T
O
P
DATA
BYTE
SLAVE
ADDRESS
a
−a
13
8
S
* *
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
Figure 7. Byte Write Sequence
SCL
SDA
ACK
8th Bit
Byte n
t
WR
ADDRESS
STOP
CONDITION
START
CONDITION
Figure 8. Write Cycle Timing
BUSACTIVITY: S
ADDRESS
BYTE
ADDRESS
BYTE
a −a
7 0
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
T
A
S
T
SLAVE
R
O
P
ADDRESS
MASTER
a
−a
13
8
T
S
* *
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
P ≤ 63
Figure 9. Page Write Sequence
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7
N24S128
Read Operations
the device header and two address bytes as for a Device
Configuration Register Write instruction. This dummy write
instruction is followed by an Immediate Read with the
device header 1011b, and the device will shift back the
content of the Device Configuration Register. Don’t care
bits are read as 1s.
If the master acknowledges the data byte, requesting more
data, the device will continue to return the content of the
Device Configuration Register until the Master responds
with a NoACK.
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the N24S128 will interpret this as a request for data residing
at the current byte address in memory. The N24S128 will
acknowledge the Slave address, will immediately shift out
the data residing at the current address, and will then wait for
the Master to respond. If the Master does not acknowledge
the data (NoACK) and then follows up with a STOP
condition (Figure 10), the N24S128 returns to Standby
mode.
Unique ID Number Read
The Unique ID Number Read instruction is similar to
a Sequential Read instruction. The user must send the device
header starting with 1011b followed by the A2 A1 A0 bits
that match the bits in the Device Configuration register. As
specified in Table 8, the second byte consists of xxxx x01x
and the third byte of xxxx 0000, where x is don’t care. This
dummy write instruction is followed by an Immediate Read
with the device header 1011b, and the device will shift back
the Unique ID byte by byte. The Unique ID is 16 bytes
(128 bits) long. After the last byte of the Unique ID has been
shifted, if the master acknowledges (requesting more data),
the device will wrap-around and start returning the Unique
ID from the beginning.
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described under
Byte Write. If rather than following up the two address bytes
with data, the Master instead follows up with an Immediate
Read sequence, then the N24S128 will use the 14 active
address bits to initialize the internal address counter and will
shift out data residing at the corresponding location. If the
Master does not acknowledge the data (NoACK) and then
follows up with a STOP condition (Figure 11), the N24S128
returns to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the 1
st
Secure Data Page Lock Status Read
data byte, then the N24S128 will continue transmitting data
residing at subsequent locations until the Master responds
with a NoACK, followed by a STOP (Figure 12). In contrast
to Page Write, during Sequential Read the address count
will automatically increment to and then wrap-around at end
of memory (rather than end of page).
There are two ways to check the lock status of the Security
Sector. The first way is to initiate a Secure Data Page Write.
The EEPROM will acknowledge if the Secure Data Page is
unlocked, and it will not acknowledge if the Secure Data
Page is locked. After the acknowledge bit, it is
recommended to generate a Start condition followed by
a Stop condition, to reset the interface.
Secure Data Page Read
The second way is to use a Lock Status Read instruction.
This instruction is similar to a Selective Read instruction,
but requires the use of the device address 1011b followed by
the A2, A1, A0 bits. The master first sends a dummy write
instruction followed by the address bytes specified in Table
8 (xxxx x10x xxxx xxxx, where x is don’t care). This is
followed by a read instruction using the same device address
as above. The device will return a data byte where Bit 1
indicates the lock status. If the lock is active this bit is “1”,
otherwise it is “0”.
The Secure Data Page Read instruction is similar to
a Sequential Read instruction. To read data from a specific
location within the Secure Data Page, the address counter is
initialized by sending the device header and two address
bytes as for a Secure Data Page Write instruction. This
dummy write instruction is followed by an Immediate Read
with the device header 1011b, and the device will shift back
data from Secure Data Page. When the end of the Secure
Data Page is reached, the address counter will wrap-around
to zero, and the next byte returned will be the first byte in the
page.
Delivery State
The N24S128 is shipped erased, i.e., all memory array
bytes are FFh, and the settable Device Configuration bits set
to 0 (1Dh).
Device Configuration Register Read
The Device Configuration Register Read instruction is
similar to a Selective Read instruction. The user must send
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8
N24S128
BUS ACTIVITY:
MASTER
N
O
A
C
K
S
T
A
R
T
S
T
SLAVE
ADDRESS
O
P
S
P
A
C
K
DATA
SLAVE
8
BYTE
9
SCL
SDA
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVIT Y:
MASTER
S
T
S
N
O
A
C
K
T
A
R
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
A
R
SLAVE
ADDRESS
SLAVE
ADDRESS
a
−a
13
a −a
0
8
7
T
T
S
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Selective Read Sequence
N
BUS ACTIVITY:
MASTER
O
S
SLAVE
ADDRESS
A T
O
C
K P
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+x
DATA
BYTE
n+2
SLAVE
Figure 12. Sequential Read Sequence
Table 10. ORDERING INFORMATION (Notes 9 thru 11)
Device
Order Number
Specific
Device Marking
Package
Type
Temperature
Range
†
Lead Finish
N/A
Shipping
N24S128C4DYT3G
P
WLCSP 4-ball
Industrial
(−40°C to +85°C)
5,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
9. All packages are RoHS-compliant (Lead-free, Halogen-free).
10.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
11. Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light the
EEPROM cells lose their stored data.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP4, 0.84x0.84x0.3
CASE 567VY
SCALE 4:1
ISSUE O
DATE 21 FEB 2018
GENERIC
MARKING DIAGRAM*
X
YW
X
Y
= Specific Device Code
= Year
W
= Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON83936G
WLCSP4, 0.84x0.84x0.3
PAGE 1 OF 1
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相关型号：
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