NB3N206SDR2G [ONSEMI]
3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver;
| 型号： | NB3N206SDR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总19页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3N201S, NB3N206S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
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MARKING
The NB3N20XS SERIES are pure 3.3 V supply differential
Multipoint Low Voltage (M−LVDS) line Drivers and Receivers.
Devices NB3N201S and NB3N206S are TIA/EIA−899 compliant.
NB3N201S offers the Type 1 receiver threshold at 0.0 V. NB3N206S
offers the Type 2 receiver threshold at 0.1 V.
These devices have Type−1 and Type−2 receivers that detect the bus
state with as little as 50 mV of differential input voltage over a
common−mode voltage range of −1 V to 3.4 V. The Type−1 receivers
have near zero thresholds ( 50 mV) and exhibit 25 mV of differential
input voltage hysteresis to prevent output oscillations with slowly
changing signals or loss of input. Type−2 receivers include an offset
threshold to provide a detectable voltage under open−circuit, idle−bus,
and other faults conditions.
8
DIAGRAMS
1
8
NB20x
AYWW
SOIC−8
D SUFFIX
CASE 751
G
1
NB20x = Specific Device Code
x
A
Y
= 1, 6
= Assembly Location
= Year
= Work Week
= Pb−Free Package
WW
G or G
NB3N201S supports Simplex bus configurations. NB3N206S
supports Simplex or Half Duplex bus configurations.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
Features
• Low−Voltage Differential 30 W to 55 W Line Drivers
and Receivers for Signaling Rates Up to 200 Mbps
• Type−1 Receivers Incorporate 25 mV of Hysteresis
• Type−2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open−Circuit and Idle−Bus
Conditions
• M−LVDS Bus Power Up/Down Glitch Free
• Operating range: VCC = 3.3 10% V( 3.0 to 3.6 V)
• Operation from –40°C to 85°C.
• These are Pb−Free Devices
Applications
• Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
• Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
• Backplane or Cabled Multipoint Data and Clock
Transmission
• Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
• Cellular Base Stations
• −1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
• Bus Pins High Impedance When Disabled or VCC ≤
1.5 V
• Central−Office Switches
• Network Switches and Routers
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
September, 2012 − Rev. 0
NB3N201S/D
NB3N201S, NB3N206S
R
1
2
3
4
8
7
6
5
V
B
CC
RE
DE
D
A
GND
SOIC−8
NB3N201S, NB3N206S
Figure 1. Logic Diagram
Figure 2. Pinout Diagram
(Top View)
Table 1. PIN DESCRIPTION
Number
Name
R
I/O Type
Open Default
Description
1
2
LVCMOS Output
LVCMOS Input
Receiver Output Pin
RE
High
Low
Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
3
4
5
DE
D
LVCMOS Input
LVCMOS Input
Driver Enable Input Pin (LOW = High Z Output, HIGH=Active)
Driver Input Pin
GND
Ground Supply pin. Pin must be connected to power supply to
guarantee proper operation.
6
7
8
A
B
M−LVDS Input
Transceiver Invert Input /Output Pin
/Output
M−LVDS Input
Transceiver True Input /Output Pin
/Output
VCC
Power Supply pin. Pin must be connected to power supply to
guarantee proper operation.
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2
NB3N201S, NB3N206S
Table 2. DEVICE FUNCTION TABLE
Inputs
Output
V
ID
= V − V
B
RE
R
A
V
ID
w 50 mV
L
H
−50 mV < V < 50 mV
L
L
?
ID
TYPE 1 Receiver
(NB3N201/NB3N203)
V
ID
≤ −50 mV
L
X
X
H
Z
Open
L
Z
Open
?
Inputs
Output
V
ID
= V − V
B
RE
R
A
V
ID
w 150 mV
L
H
50 mV < V < 150 mV
L
?
ID
TYPE 2 Receiver
(NB3N206/NB3N207)
V
ID
≤ 50 mV
L
L
X
X
H
Open
L
Z
Z
L
Open
Input
D
Enable
DE
H
Output
A / Y
B / Z
H
L
L
H
L
H
H
L
DRIVER
Open
X
H
H
Open
L
Z
Z
Z
X
Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate
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NB3N201S, NB3N206S
Table 3. ATTRIBUTES (Note 1)
Characteristics
Value
Human Body Model (JEDEC
Standard 22, Method A114−A)
A, B, Y, Z
All Pins
6 kV
2 kV
ESD
Protection
Machine Model
All Pins
All Pins
200 V
Charged –Device Model (JEDEC
Standard 22, Method C101)
1500 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index
UL−94 code V−0 A 1/8”
28 to 34
Transistor Count
917 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol Parameter
Condition 1
Condition 2
Rating
−0.5 ≤ V ≤ 4.0
Unit
V
V
CC
Supply Voltage
Input Voltage
CC
V
IN
D, DE, RE
−0.5 ≤ V ≤ 4.0
V
IN
A, B (201, 206)
−1.8 ≤ V ≤ 4.0
IN
I
Output Voltage
R
A, B
−0.3 ≤ I
−1.8 ≤ I
≤ 4.0
≤ 4.0
V
OUT
OUT
OUT
T
Operating Temperature Range, Industrial
Storage Temperature Range
−40 to ≤ +85
−65 to +150
°C
°C
A
T
stg
θ
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
190
130
°C/W
°C/W
θ
θ
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
(Note 3)
SOIC−8
41 to 44
80
°C/W
JC
0 lfpm
500 lfpm
SOIC−14
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Wave Solder
(Note 3)
SOIC−14
36
°C/W
°C
JC
T
sol
265
P
D
Power Dissipation (Continuous)
T = 25°C
725
5.8
377
mW
mW/°C
mW
A
25°C < T < 85°C
A
T = 85°C
A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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4
NB3N201S, NB3N206S
Table 5. DC CHARACTERISTICS VCC = 3.3 10% V( 3.0 to 3.6 V), GND = 0 V, T = −40°C to +85°C (See Notes 4, 5)
A
Symbol
Characteristic
Min
Typ
Max
Unit
ICC
Power Supply Current
Receiver Disabled Driver Enabled RE and DE at V , R = 50 W, All others open
mA
13
1
16
22
4
24
13
CC
L
Driver and Receiver Disabled RE at VCC, DE at 0 V, R = No Load, All others open
L
Driver and Receiver Enabled RE at 0 V, DE at V , R = 50 W, All others open
CC
L
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, R = 50 W, All others open
L
V
Input HIGH Voltage
2
V
V
V
V
IH
CC
V
Input LOW Voltage
GND
−1.4
0.05
0.8
3.8
IL
VBUS
|VID|
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
V
CC
DRIVER
|V
|
Differential output voltage magnitude (see Figure 4)
480
−50
0.8
650
50
mV
mV
V
AB
D|V
|
Change in Differential output voltage magnitude between logic states (see Figure 4)
Steady state common mode output voltage (see Figure 5)
AB
OS(SS)
V
1.2
50
DV
Change in Steady state common mode output voltage between logic states (see
Figure 5)
−50
mV
OS(SS)
V
Peak−to−peak common−mode output voltage (see Figure 5)
Maximum steady−state open−circuit output voltage (see Figure 9)
150
2.4
mV
V
OS(PP)
V
0
0
AOC
V
Maximum steady−state open−circuit output voltage (see Figure 9)
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
2.4
V
V
BOC
V
1.2 V
P(H)
SS
V
−0.2 V
V
P(L)
SS
I
High−level input current (D, DE) V = 2 V
0
0
10
10
24
10
uA
uA
mA
uA
IH
IH
I
Low−level input current (D, DE) V = 0.8 V
IL
IL
JI
OS
I
OZ
J
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−15
−10
−1.4 V ≤ (VA or VB) ≤ 3.8 V, other output at 1.2 V
I
Power−off output current (0 V ≤ V ≤ 1.5 V)
10
uA
O(OFF)
CC
−1.4 V ≤ (VA or VB) ≤ 3.8 V, other output at 1.2 V
RECEIVER
V
Positive−going Differential Input voltage Threshold (See Figure 11 & Tables 8 and 9)
Type 1
Type 2
Negative−going Differential Input voltage Threshold (See Figure 11 & Tables 8 and 9)
mV
mV
mV
IT+
50
150
V
IT−
Type 1
Type 2
−50
50
V
HYS
Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
Type 1
Type 2
25
0
VOH
VOL
High−level output voltage (IOH = –8 mA
Low−level output voltage (IOL = 8 mA)
RE High-level input current (VIH = 2 V)
RE Low-level input current (VIL = 0.8 V)
2.4
V
0.4
0
V
I
IH
−10
−10
−10
mA
mA
mA
pF
I
IL
0
I
High−impedance state output current (VO = 0 V of 3.6 V)
15
OZ
6
C
/ C
Input Capacitance VI = 0.4 sin(30E πt) + 0.5 V, other outputs at 1.2 V using HP4194A
3
A
B
impedance analyzer (or equivalent)
6
C
Differential Input Capacitance VAB = 0.4 sin(30E πt) V, other outputs at 1.2 V using
2.5
pF
%
AB
HP4194A impedance analyzer (or equivalent)
C
Input Capacitance Balance, (CA/CB)
99
101
A/B
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NB3N201S, NB3N206S
Table 5. DC CHARACTERISTICS VCC = 3.3 10% V( 3.0 to 3.6 V), GND = 0 V, T = −40°C to +85°C (See Notes 4, 5)
A
Typ
(Note
5)
Symbol
Characteristic
Min
Max
Unit
BUS INPUT AND OUTPUT
I
A
Input Current Receiver or Transceiver with Driver Disabled
uA
V = 3.8 V, V = 1.2 V
0
−20
−32
32
20
0
A
B
V = 0.0 V or 2.4 V, V = 1.2 V
A
B
V = −1.4 V, V = 1.2 V
A
B
I
B
Input Current Receiver or Transceiver with Driver Disabled
uA
V
= 3.8 V, V = 1.2 V
0
−20
−32
32
20
0
B
A
V
B
= 0.0 V or 2.4 V, V = 1.2 V
A
V
B
= −1.4 V, V = 1.2 V
A
I
Differential Input Current Receiver or Transceiver with driver disabled (I −I )
uA
uA
AB
A
B
V = V , −1.4 ≤ V ≤ 3.8 V
−4
4
A
B
A
I
I
Input Current Receiver or Transceiver Power Off 0V ≤ V ≤ 1.5 and:
CC
A(OFF)
V = 3.8 V, V = 1.2 V
0
−20
−32
32
20
0
A
B
V = 0.0 V or 2.4 V, V = 1.2 V
A
B
V = −1.4 V, V = 1.2 V
A
B
Input Current Receiver or Transceiver Power Off 0V ≤ V ≤ 1.5 and:
uA
B(OFF)
CC
V
= 3.8 V, V = 1.2 V
0
−20
−32
32
20
0
B
A
V
B
= 0.0 V or 2.4 V, V = 1.2 V
A
V
B
= −1.4 V, V = 1.2 V
A
I
Receiver Input or Transceiver Input/Output Power Off Differential Input Current; (I −I )
A B
uA
AB(OFF)
V = V , 0 ≤ V ≤ 1.5 V, −1.4 ≤ V ≤ 3.8 V
−4
4
A
B
CC
A
6
C
C
Transceiver Input Capacitance with Driver Disabled VA = 0.4 sin(30E πt) + 0.5 V using
HP4194A impedance analyzer (or equivalent); V = 1.2 V
5
5
pF
pF
pF
A
B
B
6
Transceiver Input Capacitance with Driver Disabled VB = 0.4 sin(30E πt) + 0.5 V using
HP4194A impedance analyzer (or equivalent); V = 1.2 V
A
6
C
Transceiver Differential Input Capacitance with Driver Disabled VA = 0.4 sin(30E pt) +
3.0
AB
0.5 V using HP4194A impedance analyzer (or equivalent);
V
B
= 1.2 V
C
Transceiver Input Capacitance Balance with Driver Disabled, (CA/CB)
99
101
%
A/B
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. See Figure 3. DC Measurements reference.
5. Typ value at 25°C and 3.3 VCC supply voltage.
Table 6. DRIVER AC CHARACTERISTICS VCC = 3.3 10% V( 3.0 to 3.6 V), GND = 0 V, T = −40°C to +85°C (Note 6)
A
Symbol
/ t
Characteristic
Propagation Delay (See Figure 7)
Min
Typ
Max
2.4
7
Unit
ns
t
1.0
1.5
PLH PHL
t
t
/ t
Disable Time HIGH or LOW state to High Impedance (See Figure 8)
Enable Time High Impedance to HIGH or LOW state (See Figure 8)
ns
PHZ PLZ
/ t
7
ns
PZH PZL
t
Pulse Skew (|t
− t |) (See Figure 7)
PHL
0
100
1
ps
SK(P)
PLH
t
Device to Device Skew similar path and conditions (See Figure 7)
ns
SK(PP)
t
Period Jitter RMS, 100 MHz (Source tr/tf 0.5 ns, 10 and 90 % points, 30k
samples. Source jitter de−embedded from Output values ) (See Figure 10)
2
3
ps
JIT(PER)
15
t
Peak−to−peak Jitter, 200 Mbps 2 −1 PRBS (Source tr/tf 0.5 ns, 10 and 90%
30
130
ps
JIT(PP)
points, 100k samples. Source jitter de−embedded from Output values) (See
Figure 10)
tr / tf
Differential Output rise and fall times (See Figure 7)
1
1.6
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Typ value at 25°C and 3.3 V supply voltage.
CC
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NB3N201S, NB3N206S
Table 7. RECEIVER AC CHARACTERISTICS VCC = 3.3 10% V( 3.0 to 3.6 V), GND = 0 V, T = −40°C to +85°C (Note 7)
A
Symbol
/ t
Characteristic
Min
Typ
Max
6
Unit
ns
t
Propagation Delay (See Figure 12)
2
4
PLH PHL
t
t
/ t
Disable Time HIGH or LOW state to High Impedance (See Figure 13)
Enable Time High Impedance to HIGH or LOW state (See Figure 13)
10
15
ns
PHZ PLZ
/ t
ns
PZH PZL
t
Pulse Skew (|t
− t
PHL
|) (See Figure 14) C = 5 pF
ps
SK(P)
PLH
L
Type 1
Type 2
100
300
300
500
t
Device to Device Skew similar path and conditions (See Figure 12) C = 5 pF
1
7
ns
ps
SK(PP)
L
t
Period Jitter RMS, 100 MHz (Source: VID = 200 mV for 201 and 203, VID =
4
JIT(PER)
pp
400 mV for 206 and 207, V
=1 V, tr/tf 0.5 ns, 10 and 90 % points, 30k samples.
pp
CM
Source jitter de−embedded from Output values ) (See Figure 14)
15
t
Peak−to−peak Jitter, 200 Mbps 2 −1 PRBS (Source tr/tf 0.5 ns, 10% and 90% points,
100k samples. Source jitter de−embedded from Output values) (See Figure 14)
ps
ns
JIT(PP)
Type 1
Type 2
300
450
700
800
tr / tf
Differential Output rise and fall times (See Figure 14) C = 15 pF
1
2.3
L
7. Typ value at 25°C and 3.3 VCC supply voltage. .
Figure 3. Driver Voltage and Current Definitions
A. All resistors are 1% tolerance.
Figure 4. Differential Output Voltage Test Circuit
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NB3N201S, NB3N206S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 500 kHz,
duty cycle = 50 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20% tolerance.
C. R1 and R2 are metal film, surface mount, 1% tolerance, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Test Circuit and Definitions for the Driver Common−Mode Output Voltage
Figure 6. Driver Short−Circuit Test Circuit
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 7. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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NB3N201S, NB3N206S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 8. Driver Enable and Disable Time Circuit and Definitions
V or V
A
B
Figure 9. Maximum Steady State Output Voltage
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NB3N201S, NB3N206S
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
D. Peak−to−peak jitter is measured using a 200 Mbps 215−1 PRBS input.
Figure 10. Driver Jitter Measurement Waveforms
Figure 11. Receiver Voltage and Current Definitions
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NB3N201S, NB3N206S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 50 MHz, duty cycle = 50
5%. CL is a combination of a 20%−tolerance, low−loss ceramic, surface−mount capacitor and fixture capacitance within 2 cm of the
D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 12. Receiver Timing Test Circuit and Waveforms
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NB3N201S, NB3N206S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz, duty cycle = 50
5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.
Figure 13. Receiver Enable/Disable Time Test Circuit and Waveforms
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NB3N201S, NB3N206S
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
15
D. Peak−to−peak jitter is measured using a 200 Mbps 2 −1 PRBS input.
Figure 14. Receiver Jitter Measurement Waveforms
Table 8. TYPE−1 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Resulting Differential
Input Voltage
Resulting Common−
Mode Input Voltage
Applied Voltages
VIA
VIB
VID
VIC
Receiver Output
2.400
0.000
3.800
3.750
–1.350
–1.400
0.000
2.400
3.750
3.800
–1.400
–1.350
2.400
–2.400
0.050
–0.050
0.050
–0.050
1.200
1.200
3.775
3.775
–1.375
–1.375
H
L
H
L
H
L
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 9. TYPE−2 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Resulting Differential
Resulting Common−
Input Voltage
Mode Input Voltage
Applied Voltages
Receiver Output
(Note )
VIA
VIB
VID
VIC
2.400
0.000
3.800
3.800
–1.250
–1.350
0.000
2.400
3.650
3.750
–1.400
–1.400
2.400
1.200
1.200
3.725
3.775
–1.325
–1.375
H
L
–2.400
0.150
H
L
0.050
0.150
H
L
0.050
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
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NB3N201S, NB3N206S
A or B
Figure 15. Equivalent Input and Output Schematic Diagrams
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
Type 2 receivers have their differential input voltage
thresholds offset from zero volts to detect the absence of a
voltage difference. The impact to receiver output by the
offset input can be seen in Table 10 and Figure 16.
The MLVDS standard defines a type 1 and type 2 receiver.
Type 1 receivers include no provisions for failsafe and have
their differential input voltage thresholds near zero volts.
Table 10. RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS
Receiver Type
Type 1
Output Low
Output High
–2.4 V ≤ VID ≤ –0.05 V
–2.4 V ≤ VID ≤ 0.05 V
0.05 V ≤ VID ≤ 2.4 V
0.15 V ≤ VID ≤ 2.4 V
Type 2
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NB3N201S, NB3N206S
Figure 16. Receiver Differential Input Voltage Showing Transition Regions by Type
LIVE INSERTION/GLITCH−FREE POWER UP/DOWN
While the M−LVDS interface for these devices is glitch
free on power up/down, the receiver output structure is not.
Figure 17 shows the performance of the receiver output pin,
The NB3N201/206 family of products provides a
glitch−free power up/down feature that prevents the
M−LVDS outputs of the device from turning on during a
power up or power down event. This is especially important
in live insertion applications, when a device is physically
R (CHANNEL 2), as V (CHANNEL 1) is ramped. The
CC
glitch on the R pin is independent of the RE voltage. Any
complications or issues from this glitch are easily resolved
in power sequencing or system requirements that suspend
connected to an M−LVDS multipoint bus and V
is
CC
ramping.
operation until V has reached a steady state value.
CC
http://onsemi.com
15
NB3N201S, NB3N206S
Figure 17. M−LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
Simplex Theory Configurations: Data flow is
high amplitude levels. Parallel terminated interconnects
yield typical MLVDS amplitude levels and minimizes
reflections. See Figures 18 and 19. A NB3N201SDG and
NB3N206SDG can be used as the driver or as a receiver.
unidirectional and Point−to−Point from one Driver to one
Receiver. NB3N201SDG and NB3N206SDG devices
provide a high signal current allowing long drive runs and
high noise immunity. Single terminated interconnects yield
Figure 19. Parallel−Terminated Simplex
Figure 18. Point−to−Point Simplex Single
Termination
Simplex Multidrop Theory Configurations: Data flow is
unidirectional from one Driver with one or more Receivers
Multiple boards required. Single terminated interconnects
yield high amplitude levels. Parallel terminated
interconnects yield typical MLVDS amplitude levels and
minimizes reflections. On the Evaluation Test Board,
Headers P1, P2, and P3 may be used as need to interconnect
transceivers to a each other or a bus. See Figures 20 and 21.
A NB3N201SDG and NB3N206SDG can be used as the
driver or as a receiver.
http://onsemi.com
16
NB3N201S, NB3N206S
Figure 20. Multidrop or Distributed Simplex with Single Termination
Figure 21. Multidrop or Distributed Simplex with Double Termination
Half
Duplex
Multinode
Multipoint
Theory
levels and minimizes reflections. Parallel terminated
interconnects yield typical LMVDS amplitude levels and
minimizes reflections. On the Test Board, Headers P1, P2,
and P3 may be used as need to interconnect transceivers to
each other or a bus. See Figure 22. A NB3N206SDG can be
used as the driver or as a receiver.
Configurations: Data flow is unidirectional and selected
from one of multiple possible Drivers to multiple Receivers.
One “Two Node” multipoint connection can be
accomplished with a single evaluation test board. More than
Two Nodes requires multiple evaluation test boards. Parallel
terminated interconnects yield typical MLVDS amplitude
Figure 22. Multinode Multipoint Half Duplex (requires Double Termination)
Figure 23.
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17
NB3N201S, NB3N206S
ORDERING INFORMATION
Device
†
Receiver
Pin 1 Quadrant
Package
Shipping
NB3N201SDG
Type 1
Q1
SOIC*8
98 Units / Rail
2500 / Tape & Reel
98 Units / Rail
(Pb−Free)
NB3N201SDR2G
NB3N206SDG
Type 1
Type 2
Type 2
Q1
Q1
Q1
SOIC*8
(Pb−Free)
SOIC*8
(Pb−Free)
NB3N206SDR2G
SOIC*8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
18
NB3N201S, NB3N206S
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
M
S
S
X
0.25 (0.010)
Z
Y
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NB3N201S/D
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