NB7L216MN [ONSEMI]
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination; 2.5V / 3.3V ， 12GB / s的多级时钟/数据输入到RSECL ，高增益接收器/缓冲器/转换器具有内部端接
| 型号： | NB7L216MN |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination |
| 文件： | 总12页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7L216
2.5V/3.3V, 12Gb/s Multi
Level Clock/Data Input to
RSECL, High Gain
Receiver/Buffer/Translator
with Internal Termination
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MARKING DIAGRAM*
Description
16
The NB7L216 is a differential receiver/driver with high gain output
targeted for high frequency applications. The device is functionally
equivalent to the NBSG16 but with much higher gain output. This
highly versatile device provides 35 dB of gain up to 7 GHz.
Inputs incorporate internal 50 W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV.
1
NB7L
216
QFN−16
MN SUFFIX
CASE 485G
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
The V pin is an internally generated voltage supply available to
BB
= Year
this device only. V is used as a reference voltage for single−ended
= Work Week
= Pb−Free Package
BB
NECL or PECL inputs. For all single−ended input conditions, the
(Note: Microdot may be in either location)
unused complementary differential input should be connected to V
BB
as a switching reference voltage. V may also rebias AC coupled
BB
*For additional marking information, refer to
Application Note AND8002/D.
inputs. When used, decouple V via a 0.01 mF capacitor and limit
BB
current sourcing or sinking to 0.5 mA. When not used, V output
should be left open.
BB
VTD
Application notes, models and support documentation are available
at www.onsemi.com.
50 W
Q
Q
D
D
Features
• High Gain of 35 dB from DC to 7 GHz Typical
• High IIP3: 0 dBm Typical
50 W
• 20 mV Minimum Input Voltage Swing
• Maximum Input Clock Frequency up to 8.5 GHz
• Maximum Input Data Rate up to 12 Gb/s Typical
• <0.5 ps of RMS Clock Jitter
VTD
Figure 1. Functional Block Diagram
• <9 ps of Data Dependent Jitter
• 120 ps Typical Propagation Delay
• 30 ps Typical Rise and Fall Times
Device DDJ = 3 ps
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V
CC
with V = 0 V
EE
• RSNECL Output with RSNECL or NECL Inputs with Operating
Range: V = 0 V with V = −2.375 V to −3.465 V
CC
EE
• RSECL Output Level (400 mV Peak−to−Peak Output),
• 50 W Internal Input Termination Resistors (Temperature−Coefficient
of < 6.38 mW/°C)
• VBB – ECL Reference Voltage Output
• Pb−Free Packages are Available
TIME (17 ps/div)
Figure 2. Typical Output Waveform at
12 Gb/s with PRBS 223−1 (VINPP = 400 mV,
Input Signal DDJ = 12 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
August, 2006 − Rev. 2
NB7L216/D
NB7L216
V
V
V
V
Exposed Pad (EP)
EE
EE
BB
EE
16
15
14
13
VTD
1
2
3
4
12
11
10
9
V
CC
D
D
Q
Q
NB7L216
VTD
V
CC
5
6
7
8
V
V
V
V
EE EE
EE
EE
Figure 3. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
1
Name
VTD
D
I/O
Description
−
Internal 50 W termination pin. See Table 7. Note 1
2
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted differential input. Note 1.
3
D
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted differential input. Note 1.
4
15
VTD
−
−
−
Internal 50 W termination pin. See Table 7. Note 1.
V
V
Internally generated ECL reference voltage supply.
BB
EE
5, 6, 7, 8, 13, 14
Negative supply voltage. All V pins must be externally connected to power
EE
supply to guarantee proper operation.
9, 12
10
V
−
Positive supply voltage. All V pins must be externally connected to power
supply to guarantee proper operation
CC
CC
Q
Q
RSECL Output
RSECL Output
−
Noninverted differential output. Typically receiver terminated with 50 W resistor
to V = V − 2.0 V.
TT
CC
11
Inverted differential output. Typically receiver terminated with 50 W resistor to
= V − 2.0 V.
V
TT
CC
−
EP
Exposed pad (EP). Thermally exposed pad on the package bottom must be
attached to a heat sinking conduit. It is recommended to connect the EP to the
lower potential, V
.
EE
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal
is applied on D/D input then the device will be susceptible to self−oscillation.
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2
NB7L216
Table 2. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 500 kV
> 10 V
Charged Device Model
> 4 kV
Moisture Sensitivity (Note 2)
Pb Pkg
Level 1
Pb−Free Pkg
Level 1
QFN−16
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS (Note 3)
Symbol Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
3.6
Unit
V
V
V
V
V
V
CC
EE
I
EE
CC
Negative Power Supply
= 0 V
−3.6
V
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V = V
3.6
−3.6
V
V
EE
CC
I
I
CC
EE
V = V
V
Differential Input Voltage
|D − D|
2.8
V
INPP
I
I
I
Input Current Through R (50 W Resistor)
Static
Surge
45
80
mA
mA
IN
T
Output Current
Continuous
Surge
25
50
mA
mA
OUT
V
Sink/Source
0.5
mA
°C
BB
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Wave Solder
1S2P (Note 4)
QFN−16
4
°C/W
°C
JC
T
sol
Pb
Pb−Free
265
265
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB7L216
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS V = 2.375 V to 3.465 V, V = 0 V
CC
EE
−40 5C
Typ
25 5C
Typ
27
85 5C
Typ
27
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
I
Power Supply Current (VTD/VTD
open)
27
35
35
35
mA
EE
V
V
Output HIGH Voltage
(Note 5 and 6)
V
V
V
V
V
V
−900
V
–950
V
−900
V
CC
−850
mV
mV
OH
OL
CC
CC
CC
CC
CC
CC
CC
CC
−1040 −980
−940 −1000 −950
Output LOW Voltage
(Note 5 and 6)
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
−1520 −1430 −1320 −1470 −1370 −1270 –1440 −1340 −1240
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 14 and 16)
V
V
V
Input Threshold Reference Voltage
Range (Note 7 and 8)
1100
V
−10
1100
V
−10
1100
V
CC
−10
mV
mV
mV
TH
IH
IL
CC
CC
Single−ended Input HIGH Voltage
(Note 8)
V
V
V
V
V
V
CC
th
CC
th
CC
th
+10
+ 10
+10
Single−ended Input LOW Voltage
(Note 8)
V
V
−10
V
V
−10
V
V
th
−10
EE
th
EE
th
EE
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 15 and 17)
V
V
V
Differential Input HIGH Voltage
(Note 9)
1105
V
1105
V
V
1105
V
V
mV
mV
mV
IHD
CC
CC
CC
CC
CC
Differential Input LOW Voltage
(Note 9)
V
V
−10
V
V
EE
ILD
EE
CC
EE
−10
−10
Input Common Mode Range
(Differential Configuration,
Note 9 and 10)
1100
V
−5
1100
V
–5
1100
V
CC
–5
CMR
CC
CC
V
Differential Input Voltage
10
−5
2500
+5
10
−5
2500
+5
10
−5
2500
+5
mV
ID
(V
− V )
ILD
IHD
V
V
Input Offset Voltage (Note 11)
0
0
0
mV
mV
IO
Internally Generated Reference
Voltage Supply
V
V
V
V
V
V
V
V
V
CC
BB
CC
CC
CC
CC
CC
CC
CC
CC
−1425 −1345 −1265 −1425 −1345 −1265 −1425 −1345 −1265
(Only 3 V – 3.6 V Supply Load with
−100 mA)
I
I
Input HIGH Current
D/Db (VTD/VTD Open)
0
20
10
100
75
0
20
10
100
75
0
20
10
100
75
mA
mA
IH
Input LOW Current
D/Db (VTD/VTD Open)
−25
45
−25
45
−25
45
IL
R
R
Internal Input Termination Resistor
50
55
50
55
50
55
W
TIN
Internal Input Termination Resistor
Temperature Coefficient
6.38
6.38
6.38
mW/°C
T_Coef
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs evaluated with 50 W resistors to V = V − 2.0 V for proper operation.
TT
CC
6. Input and output parameters vary 1:1 with V
.
CC
7. V is applied to the complementary input when operating in single−ended mode.
TH
8. V , V and V parameters must be complied simultaneously.
IH
IL
TH
9. V , V
and V
parameters must be complied simultaneously.
IHD
ILD
CMR
10.V
min varies 1:1 with V , V
max varies 1:1 with V
.
CC
CMR
EE
CMR
11. Typical standard deviation of input offset voltage is 1.76 mV.
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NB7L216
Table 5. AC CHARACTERISTICS V = 2.375 V to 3.465 V, V = 0 V; (Note 12)
CC
EE
−40°C
25°C
85°C
Min Typ Max Min Typ
Max Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
(See Figure 4)
)f ≤ 7.0 GHz 275 380
INPPmin in
275 380
100 250
275
100
380
250
mV
OUTPP
f ≤ 8.5 GHz 100 250
in
f
Maximum Operating Data Rate
Power Gain DC to 7 GHz
Input Return Loss @ 7 GHz
Output Return Loss @ 7 GHz
10
12
35
10
12
35
10
12
35
Gb/s
dB
DATA
|S21|
|S11|
|S22|
|S12|
IIP3
−10
−5
−10
−5
−10
−5
dB
dB
Reverse Isolation (Differential Configuration)
Input Third Order Intercept
−25
0
−25
0
−25
0
dB
dBm
ps
t
t
,
Propagation Delay to Output Differential @ 1 GHz
60
120
180
60
120
180
60
120
180
PLH
PHL
t
Duty Cycle Skew (Note 12)
Device to Device Skew (Note 17)
2
5
10
20
2
5
10
20
2
5
10
20
ps
ps
SKEW
t
RMS Random Clock Jitter
(Note 15)
f
v 8.5 GHz
in
0.1
0.5
0.1
0.5
0.1
0.5
JITTER
Peak−to−Peak Data Dependent Jitter (Note 16)
f
f
f
f
= 3.5 Gb/s
= 5.0 Gb/s
= 10 Gb/s
= 12 Gb/s
1
3
4
4
7
9
9
9
1
3
4
4
7
9
9
9
1
3
4
4
7
9
9
9
DATA
DATA
DATA
DATA
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14 and Figure 12)
20
2500
20
2500
20
2500
mV
ps
INPP
t
t
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q, Q
30
45
30
45
30
45
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
12.Measured by forcing V
from a 50% duty cycle clock source. All loading with an external R = 50 W to V =V − 2.0 V. Input edge
INPPmin
L TT CC
rates 40 ps (20% − 80%).
13.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
14.V (MAX) cannot exceed V − V . Input voltage swing is a single−ended measurement operating in differential mode.
INPP
CC
EE
15.Additive RMS jitter with 50% duty cycle clock signal.
16.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2 −1.
17.Device to device skew is measured between outputs under identical transition @ 1 GHz.
23
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
−40°C
−40°C
85°C
25°C
85°C
25°C
0
0
0
2
4
6
7
8
9
10
11
12
0
2
4
6
7
8
9
10
11
12
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fIN) and Temperature
(VINPP = 400 mV, VCC = 3.3 V and VEE = 0 V)
Figure 5. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fIN) and Temperature
(VINPP = 20 mV, VCC = 3.3 V and VEE = 0 V)
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5
NB7L216
Device DDJ = 1 ps
Device DDJ =1 ps
TIME (66 ps/div)
TIME (54 ps/div)
Figure 6. Typical Output Waveform at 2.488 Gb/s with
Figure 7. Typical Output Waveform at 3.5 Gb/s with
PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps) PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
Device DDJ =2 ps
Device DDJ = 3 ps
TIME (37 ps/div)
TIME (21 ps/div)
Figure 8. Typical Output Waveform at 5 Gb/s with PRBS
223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
Figure 9. Typical Output Waveform at 10 Gb/s with
PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
0
40
35
30
25
20
15
10
5
−10
S22
−20
S11
−30
−40
−50
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Small Signal Gain – S21 Magnitude*
Figure 11. Input and Output Reflection – S11
and S22 Magnitude*
*T = +25°C, V = 3.3 V, V =0 V, P = −44 dBm,Z = Z = 50 W, input and output matching network is not included.
A
CC
EE
IN
S
L
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6
NB7L216
Table 6. TYPICAL DEVICE S−PARAMETERS
S11
S21
S12
S22
Frequency
(Hz)
dbS11
−45.2
−30.4
−36.2
−27.4
−12.3
−10.6
−19.0
−10.6
−10.7
−9.0
|S11|
0.005
0.030
0.015
0.042
0.244
0.295
0.112
0.294
0.291
0.354
0.294
0.341
0.340
0.133
0.053
0.206
0.462
0.552
0.652
0.326
0.283
0.384
0.506
0.356
0.166
0.175
0.250
0.265
0.140
0.068
íS11
−88.5
−134.7
−146.5
25.7
dbS21
37.2
37.3
37.1
37.4
36.2
36.9
35.4
35.6
36.0
35.1
36.4
35.8
36.2
34.3
33.2
25.2
22.6
19.4
19.0
18.7
14.5
12.9
12.7
12.9
10.5
9.9
|S21|
72.799
73.145
íS21
−33.2
−68.4
dbS12
−72.3
−45.8
−43.3
−37.1
−29.9
−26.1
−28.3
−24.8
−22.5
−25.2
−24.3
−24.5
−21.9
−22.7
−24.4
−21.5
−19.4
−19.0
−19.4
−24.0
−25.9
−29.4
−21.4
−19.4
−21.0
−24.0
−22.0
−18.6
−20.1
−20.2
|S12|
0.001
0.005
0.007
0.014
0.032
0.050
0.038
0.058
0.075
0.055
0.061
0.060
0.080
0.073
0.060
0.084
0.107
0.112
0.107
0.063
0.051
0.034
0.085
0.107
0.089
0.063
0.079
0.118
0.099
0.098
íS12
−139.1
129.8
98.5
dbS22
−2.5
|S22|
0.749
0.714
0.717
0.666
0.599
0.485
0.566
0.417
0.201
0.367
0.398
0.397
0.237
0.428
0.445
0.416
0.249
0.246
0.267
0.301
0.288
0.213
0.085
0.214
0.239
0.272
0.181
0.120
0.163
0.274
íS22
157.4
154.3
132.8
107.1
92.1
4.97E+08
1.02E+09
1.51E+09
2.00E+09
2.52E+09
3.01E+09
3.50E+09
4.02E+09
4.51E+09
4.99E+09
5.48E+09
6.01E+09
6.49E+09
6.98E+09
7.51E+09
7.99E+09
8.52E+09
9.00E+09
9.49E+09
1.00E+10
1.05E+10
1.10E+10
1.15E+10
1.20E+10
1.25E+10
1.30E+10
1.35E+10
1.40E+10
1.45E+10
1.50E+10
−2.9
71.433 −105.4
74.061 −139.0
64.810 −179.5
−2.9
91.8
−3.5
−27.7
−83.8
−22.1
−120.3
167.4
87.1
54.4
−4.4
70.102
58.933
60.437
62.843
56.576
65.812
61.327
144.5
99.9
9.4
−6.3
77.3
25.9
−5.0
67.9
73.8
−32.6
−68.3
−107.2
−121.4
−125.7
−152.4
177.5
165.7
152.8
120.7
109.9
62.0
−7.6
54.2
41.1
−13.9
−8.7
70.2
14.2
81.2
−10.6
−9.3
62.7
−16.1
−72.8
−8.0
50.4
108.2
59.4
−8.0
−0.9
−9.4
64.212 −119.4
52.039 −141.5
−12.5
−7.4
−27.2
−32.2
−37.9
−54.7
−73.7
−62.5
−100.2
−117.0
−172.0
74.0
−17.5
−25.6
−13.7
−6.7
25.5
107.9
146.5
117.9
106.2
71.1
45.861
18.093
13.434
9.336
8.937
8.595
5.298
4.408
4.339
4.395
3.360
3.121
2.728
2.314
1.856
1.695
164.6
133.6
116.2
102.0
61.1
−7.0
−7.6
−12.1
−12.2
−11.5
−10.4
−10.8
−13.4
−21.4
−13.4
−12.4
−11.3
−14.9
−18.4
−15.7
−11.2
−5.2
−3.7
−9.7
46.2
18.6
50.6
−11.0
−8.3
35.8
−13.3
−9.6
12.9
7.2
21.1
−5.9
−0.4
−33.7
−63.4
−97.8
−119.7
−148.9
−167.1
167.6
145.0
36.3
−148.6
159.5
169.2
171.6
177.8
140.3
98.2
−9.0
−23.8
−46.9
−83.0
−96.5
−105.9
−97.8
−108.9
−9.5
−15.6
−15.1
−12.0
−11.5
−17.0
−23.4
−39.0
−39.9
−39.1
−74.2
−107.0
−128.1
8.7
7.3
5.4
4.6
96.1
NOTE: T = +25°C, V =3.3V, V = 0 V, P = −44 dBm, Z = Z = 50 W, input and output matching network is not included.
A
CC
EE
IN
S
L
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7
NB7L216
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 12. AC Reference Measurement
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
D
D
D
D
V
th
V
th
Figure 14. Differential Input Driven
Single−Ended
Figure 15. Differential Inputs Driven
Differentially
V
V
CC
CC
V
IHDmax
V
IHmax
V
V
CMmax
thmax
V
V
ILDmax
ILmax
V
= V
− V
IHD ILD
ID
D
D
V
V
V
V
IH
th
IHDtyp
ILDtyp
IHDmin
V
CMR
V
th
D
V
IL
V
V
V
IHmin
ILmin
V
V
CMmax
thmin
V
ILDmin
GND
GND
NOTE:
V
v V v V ; V > V
EE IN CC IH IL
Figure 16. Vth Diagram
Figure 17. VCMR Diagram
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8
NB7L216
APPLICATION INFORMATION
All NB7L216 inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential
input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within
these conditions, the input voltage can range from V to 1.2 V. Examples interfaces are illustrated below in a 50 W
CC
environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D.
Table 7. INTERFACING OPTIONS
Interfacing Options
CML
Connections
Connect VTD and VTD to V (See Figure 18)
CC
LVDS
Connect VTD and VTD Together (See Figure 20)
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
Bias VTD and VTD Inputs within Common Mode Range (V
Standard ECL Termination Techniques (See Figure 13)
) (See Figure 19)
CMR
An External Voltage (V ) should be Applied to the Unused Complementary Differential Input. Nominal
THR
V
V
is 1.5 V for LVTTL and V / 2 for LVCMOS Inputs. This Voltage must be within the
Specification. (See Figure 21)
THR
THR
CC
V
V
CC
CC
50 W 50 W
Z = 50 W
Z = 50 W
Q
D
50 W
50 W
VTD
NB7L216
CML
Driver
V
V
CC
CC
VTD
D
Q
V
V
EE
EE
CC
Figure 18. CML to NB7L216 Interface
V
V
CC
C
Z = 50 W
Z = 50 W
D
50 W
50 W
VTD
V
*
PECL
Driver
Bias
NB7L216
V
*
Bias
VTD
D
Recommended R Values
C
T
V
R
T
CC
R
T
R
T
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
V
V
V
EE
EE
EE
*V
must be within common mode range limits (V
)
CMR
Bias
Figure 19. PECL to NB7L216 Interface
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9
NB7L216
V
V
CC
CC
Z = 50 W
Z = 50 W
D
50 W
50 W
VTD
LVDS
Driver
NB7L216
VTD
D
V
V
EE
EE
Figure 20. LVDS to NB7L216 Interface
V
V
CC
CC
Z = 50 W
D
50 W
50 W
LVTTL/
LVCMOS
Driver
VTD
No Connect*
NB7L216
No Connect
VTD
Recommended V
Values
REF
V
REF
V
REF
D
LVCMOS
V
− V
CC EE
2
*or 60 pF to GND
V
V
CC
EE
LVTTL 1.5 V
Figure 21. LVCMOS/LVTTL to NB7L216 Interface
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10
NB7L216
ORDERING INFORMATION
Device
†
Package
Shipping
NB7L216MN
QFN−16
123 Units / Rail
123 Units / Rail
NB7L216MNG
QFN−16
(Pb−Free)
NB7L216MNR2
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
NB7L216MNR2G
QFN−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NB7L216
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
A3
b
D
0.20 REF
TOP VIEW
0.18
0.30
0.15
C
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
1.85
0.50 BSC
(A3)
E2 1.65
0.10
0.08
C
C
e
K
L
0.20
0.30
−−−
0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
C
SOLDERING FOOTPRINT*
3.25
0.128
0.30
0.575
0.022
e
L
16X
EXPOSED PAD
EXPOSED PAD
5
8
NOTE 5
0.012
4
9
E2
e
K
16X
12
1.50
0.059
1
3.25
0.128
16
13
16X b
0.10
0.05
C
C
A
B
0.30
0.012
BOTTOM VIEW
NOTE 3
0.50
0.02
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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NB7L216/D
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