NBSG11MN [ONSEMI]
2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs; ？ 2.5V / 3.3V SiGe半导体1 ： 2差分时钟驱动器，带有RSECL *输出
| 型号： | NBSG11MN |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBSG11
2.5V/3.3VꢀSiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
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MARKING
The NBSG11 is a 1-to-2 differential fanout buffer, optimized for
low skew and ultra-low JITTER.
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL),
400 mV.
DIAGRAM*
SG
11
LYW
FCBGA-16
BA SUFFIX
CASE 489
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• 30 ps Typical Rise and Fall Times
• 125 ps Typical Propagation Delay
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V
CC
SG11
ALYW
QFN-16
MN SUFFIX
CASE 485G
with V = 0 V
EE
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V = 0 V with V = -2.375 V to -3.465 V
CC
EE
• RSECL Output Level (400 mV Peak-to-Peak Output), Differential
A = Assembly Location
L = Wafer Lot
Y = Year
Output Only
• 50 W Internal Input Termination Resistors
W = Work Week
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
*For further details, refer to Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
NBSG11BA
4x4 mm
100 Units / Tray
FCBGA-16
NBSG11BAR2
4x4 mm
500 / Tape & Reel
FCBGA-16
NBSG11MN
3x3 mm
QFN-16
123 Units / Rail
NBSG11MNR2
3x3 mm
QFN-16
3000 / Tape & Reel
Board
Description
NBSG11BAEVB
NBSG11BA Evaluation Board
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
April, 2003 - Rev. 6
NBSG11/D
NBSG11
1
2
3
4
V
NC NC
15 14
V
CC
EE
Exposed Pad (EP)
16
13
VTCLK
A
B
NC
NC
Q1
VTCLK
CLK
Q0
11 Q0
1
2
3
4
12
CLK
CLK
V
Q1
Q0
V
CC
CC
EE
NBSG11
Q1
Q1
CLK
10
9
V
V
EE
C
D
VTCLK
VTCLK
NC
NC
Q0
5
6
7
8
V
EE
NC NC
V
CC
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
D1
QFN
Name
VTCLK
CLK
I/O
Description
1
2
-
Internal 50 W Termination Pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V and 36.5 kW to V
C1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
.
CC
EE
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 kW to V
.
EE
A1
4
VTCLK
-
-
-
Internal 50 W Termination Pin. See Table 2.
Negative Supply Voltage
No Connect
B2,C2
5,16
V
EE
A2,A3,D2,
D3
6,7,14,15
NC
B3,C3
A4
8,13
9
V
-
Positive Supply Voltage
CC
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 W to
= V - 2 V
V
TT
CC
B4
C4
10
11
12
-
Q1
Q0
Q0
EP
RSECL Output
RSECL Output
RSECL Output
-
Noninverted Differential Output 1. Typically Terminated with 50 W to
= V - 2 V
V
TT
CC
Inverted Differential output 0. Typically Terminated with 50 W to
= V - 2 V
V
TT
CC
D4
Noninverted Differential Output 0. Typically Terminated with 50 W to
= V - 2 V
V
TT
CC
N/A
Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
CC
EE
bottom (see case drawing) must be attached to a heat-sinking conduit.
3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self-oscillation.
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2
NBSG11
V
CC
VTCLK
Q1
Q1
36.5 KW
50 W
CLK
CLK
Q0
Q0
75 KW
75 KW
50 W
VTCLK
V
EE
Figure 3. Logic Diagram
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
Connect VTCLK and VTCLK to V
CML
LVDS
CC
Connect VTCLK and VTCLK together
AC-COUPLED
Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
RSECL, PECL, NECL
LVTTL, LVCMOS
Standard ECL Termination Techniques
An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V /2
CC
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (CLK, CLK)
Internal Input Pullup Resistor (CLK)
ESD Protection
Value
75 kW
36.5 kW
Human Body Model
> 2 kV
> 100 V
Machine Model
Moisture Sensitivity (Note 4)
FCBGA-16
QFN-16
Level 3
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
125
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional information, see Application Note AND8003/D.
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NBSG11
Table 4. MAXIMUM RATINGS (Note 5)
Symbol Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
3.6
Units
V
CC
V
EE
V
I
V
V
V
V
EE
Negative Power Supply
= 0 V
-3.6
CC
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V ≤ V
3.6
V
V
EE
I
CC
V ≥ V
-3.6
CC
I
EE
V
INPP
Differential Input Voltage
|D - D|
V
CC
V
CC
- V
- V
w
2.8 V
2.8 V
2.8
V
V
EE
EE
<
|V
- V
|
CC
EE
I
Output Current
Continuous
Surge
25
50
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
16 FCBGA
16 QFN
-40 to +70
-40 to +85
°C
A
T
stg
-65 to +150
°C
q
q
Thermal Resistance (Junction-to-Ambient) 0 LFPM
16 FCBGA
16 FCBGA
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JA
(Note 6)
500 LFPM
0 LFPM
500 LFPM
16 QFN
Thermal Resistance (Junction-to-Case)
Wave Solder
1S2P (Note 6)
2S2P (Note 7)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
JC
T
sol
< 15 Seconds
225
°C
5. Maximum Ratings are those values beyond which device damage may occur.
6. JEDEC standard multilayer board - 1S2P (1 signal, 2 power).
7. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 2.5 V; V = 0 V (Note 8)
CC
EE
-40 °C
Typ
25°C
70°C(BGA)/85°C(QFN)**
Min
45
Max
75
Min
45
Typ
Max
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 9)
Output Amplitude Voltage
Unit
mA
mV
mV
V
I
EE
60
60
75
V
V
V
1450
350
1530
410
1575
525
1525 1565 1600
350 410 525
1550
350
1590
410
1625
525
OH
OUTPP
IH
Input HIGH Voltage (Single-Ended)
(Note 11)
V
CC
-
V
CC
-
V
CC
V
CC
-
V
CC
-
V
CC
V
1435
mV
-
V
1000
mV*
-
V
CC
CC
CC
1435
mV
1000
mV*
1435 1000
mV mV*
V
V
Input LOW Voltage (Single-Ended)
(Note 12)
V
2.5 V
-
V
-
V
-
V
-
V
-
V
-
V
2.5 V
-
V
1400
mV*
-
V -
IH
150
mV
V
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
1400 150 mV 2.5 V 1400 150
mV*
mV*
mV
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
1.2
2.5
1.2
45
2.5
1.2
2.5
IHCMR
R
Internal Input Termination Resistor
45
50
80
25
55
50
80
25
55
45
50
80
25
55
W
TIN
I
Input HIGH Current (@ V , V )
IHMAX
150
100
150
100
150
100
mA
mA
IH
IL
IH
I
Input LOW Current (@ V , V
)
IL
ILMIN
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
8. Input and output parameters vary 1:1 with V . V can vary +0.125 V to -0.965 V.
CC
EE
9. All loading with 50 W to V - 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
11. V cannot exceed V
.
CC
IH
12.V always ≥ V
.
IL
EE
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum temperature specification of 70°C and devices packaged in QFN-16 have maximum
temperature specification of 85°C.
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NBSG11
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 3.3 V; V = 0 V (Note 13)
CC
EE
-40 °C
Typ
25°C
70°C(BGA)/85°C(QFN)**
Min
45
Max
75
Min
45
Typ
60
Max
75
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 14)
Output Amplitude Voltage
Unit
mA
mV
mV
V
I
EE
60
V
OH
2250
350
2330
410
2375
525
2325
350
2365
410
2400
525
2350
350
2390
410
2425
525
V
V
OUTPP
IH
Input HIGH Voltage (Single-Ended)
(Note 16)
V
CC
-
V
CC
-
V
CC
V
CC
-
V
CC
-
V
CC
V
1435
mV
-
V
1000
mV*
-
V
CC
CC
CC
1435
mV
1000
mV*
1435
mV
1000
mV*
V
V
Input LOW Voltage (Single-Ended)
(Note 17)
V
2.5 V
-
V
1400
mV*
-
V
150
mV
-
V
2.5 V
-
V
1400
mV*
-
V
150
mV
-
V
2.5 V
-
V
1400
mV*
-
V -
IH
150
mV
V
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
Input HIGH Voltage Common Mode
Range (Note 15)
1.2
3.3
1.2
3.3
1.2
3.3
IHCMR
(Differential Configuration)
R
Internal Input Termination Resistor
45
50
80
25
55
45
50
80
25
55
45
50
80
25
55
W
TIN
I
Input HIGH Current (@ V , V )
IHMAX
150
100
150
100
150
100
mA
mA
IH
IL
IH
I
Input LOW Current (@ V , V
)
IL
ILMIN
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13.Input and output parameters vary 1:1 with V . V can vary +0.925 V to -0.165 V.
CC
EE
14.All loading with 50 W to V - 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
15.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
16.V cannot exceed V
.
CC
IH
17.V always ≥ V
.
IL
EE
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum temperature specification of 70°C and devices packaged in QFN-16 have maximum
temperature specification of 85°C.
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NBSG11
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V = -3.465 V to -2.375 V (Note 18)
EE
-40 °C
Typ
60
25°C
Typ
60
70°C(BGA)/85°C(QFN)**
Min
Max
75
Min
45
Max
75
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 19)
Output Amplitude Voltage
Unit
mA
mV
mV
V
I
EE
45
VOH
-1050 -970
350 410
-925
525
-975
350
-935
410
-900
525
-950
350
-910
410
-875
525
V
V
OUTPP
Input HIGH Voltage (Single-Ended)
(Note 21)
V
CC
-
V
CC
-
V
CC
V
CC
-
V
CC
-
V
CC
V
1435
mV
-
V
1000
mV*
-
V
CC
IH
CC
CC
1435 1000
mV mV*
1435 1000
mV mV*
V
Input LOW Voltage (Single-Ended) (Note 22)
V
-
V
-
V
150
mV
-
V
-
V
-
V
150
mV
-
V
2.5 V
-
V
1400
mV*
-
V -
IH
150
mV
V
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
2.5 V 1400
mV*
2.5 V 1400
mV*
V
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 20)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V +1.2
EE
0.0
IHCMR
R
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
80
25
55
W
TIN
I
IH
I
IL
Input HIGH Current (@ V , V )
IHMAX
80
25
150
100
80
25
150
100
150
100
mA
mA
IH
Input LOW Current (@ V , V
)
IL
ILMIN
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 W to V - 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
21.V cannot exceed V
.
CC
IH
22.V always ≥ V
.
IL
EE
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum temperature specification of 70°C and devices packaged in QFN-16 have maximum
temperature specification of 85°C.
Table 8. AC CHARACTERISTICS for FCBGA-16
V
CC
= 0 V; V = -3.465 V to -2.375 V or V = 2.375 V to 3.465 V; V = 0 V
EE CC EE
-40 °C
Typ
12
25°C
Typ
12
70°C
Typ
12
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.709
10.709
10.709
GHz
max
(See Figure 4. F /JITTER) (Note 23)
max
t
t
,
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 24)
Within-Device Skew (Note 25)
Device-to-Device Skew (Note 26)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
SKEW
t
RMS Random Clock Jitter
ps
JITTER
f
in
< 10 GHz
0.2
1
0.2
1
0.2
1
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75
20
2600
55
75
20
2600
55
75
20
2600
55
mV
ps
INPP
t
r
t
f
Output Rise/Fall Times
(20% - 80%) @ 1 GHz
Q, Q
30
30
30
23.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V -2.0 V. For minimum f
value of 10.709 GHz,
CC
max
output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around
150 mV). Input edge rates 40 ps (20% - 80%).
24.See Figure 5. t
= |t
- t
| for a nominal 50% Differential Clock Input Waveform.
SKEW
PLH
PHL
25.Within-Device skew is defined as identical transitions on similar paths through a device.
26.Device-to-device skew for identical transitions at identical V levels.
CC
27.V
(MAX) cannot exceed V - V
.
INPP
CC
EE
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NBSG11
Table 9. AC CHARACTERISTICS for QFN-16 V = 0 V; V = -3.465 V to -2.375 V or V = 2.375 V to 3.465 V; V = 0 V
CC
EE
CC
EE
-40 °C
25°C
Typ
12
85°C
Typ
12
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.5
12
10.5
10.5
GHz
max
(See Figure 4. F /JITTER) (Note 28)
max
t
t
,
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 29)
Within-Device Skew (Note 30)
Device-to-Device Skew (Note 31)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
SKEW
t
RMS Random Clock Jitter
ps
JITTER
f
in
< 10 GHz
0.2
1
0.2
1
0.2
1
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
75
15
2600
55
75
20
2600
55
75
20
2600
55
mV
ps
INPP
t
r
t
f
Output Rise/Fall Times
(20% - 80%) @ 1 GHz
Q, Q
30
30
30
28.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V -2.0 V. For minimum f
value of 10.5 GHz,
CC
max
output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around
150 mV). Input edge rates 40 ps (20% - 80%).
29.See Figure 5. t
= |t
- t
| for a nominal 50% Differential Clock Input Waveform.
PHL
SKEW
PLH
30.Within-Device skew is defined as identical transitions on similar paths through a device.
31.Device-to-device skew for identical transitions at identical V levels.
CC
32.V
(MAX) cannot exceed V - V
.
INPP
CC
EE
600
500
400
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
-0.5
OUTPUT AMP.
OUTPUT P-P SPEC
300
200
100
0
RMS JITTER
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
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NBSG11
CLK
V
V
= V (CLK) - V (CLK)
IH IL
INPP
CLK
Q
= V (Q) - V (Q)
OUTPP
OH
OL
Q
t
t
PHL
PLH
Figure 5. AC Reference Measurement
Q
Q
D
Receiver
Device
Driver
Device
D
50 W
50 W
V
TT
V
TT
= V
- 2.0 V
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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NBSG11
PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
-X-
D
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
M
-Y-
K
E
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
M
MILLIMETERS
0.20
DIM MIN
MAX
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
A
A1
A2
b
1.40 MAX
0.25
0.35
3 X e
4
3
2
1
1.20 REF
0.30
0.50
A
D
4.00 BSC
3
B
E
4.00 BSC
1.00 BSC
0.50 BSC
e
16 X
b
C
D
S
M
M
0.15
0.08
Z X
Z
Y
S
VIEW M-M
5
0.15
Z
A2
A
-Z-
16 X
A1
0.10
Z
4
DETAIL K
ROTATED 90 CLOCKWISE
_
http://onsemi.com
9
NBSG11
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-X-
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
M
-Y-
MILLIMETERS
DIM MIN MAX
3.00 BSC
3.00 BSC
0.80
INCHES
MIN MAX
A
B
C
D
E
F
0.118 BSC
0.118 BSC
B
1.00 0.031
0.039
0.011
0.073
0.073
0.23
1.75
1.75
0.28 0.009
1.85 0.069
1.85 0.069
N
G
H
J
0.50 BSC
0.875 0.925
0.20 REF
0.020 BSC
0.034
0.036
0.25 (0.010) T
0.25 (0.010) T
0.008 REF
K
L
0.00
0.35
0.05 0.000
0.45 0.014
0.002
0.018
M
N
P
R
1.50 BSC
1.50 BSC
0.875 0.925
0.60 0.80 0.024
0.059 BSC
0.059 BSC
0.034
0.036
0.031
J
R
C
SEATING
PLANE
-T-
0.08 (0.003) T
K
E
H
G
L
5
8
4
9
F
12
1
16
13
P
D NOTE 3
M
0.10 (0.004)
T
X Y
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