NCD57080A [ONSEMI]
Isolated High Current IGBT Gate Driver;型号: | NCD57080A |
厂家: | ONSEMI |
描述: | Isolated High Current IGBT Gate Driver 栅 双极性晶体管 |
文件: | 总24页 (文件大小:646K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Isolated High Current IGBT
Gate Driver
NCD57080A, NCD57080B,
NCD57080C
NCD57080A, NCD57080B and NCD57080C are high−current
single channel IGBT gate drivers with 3.75 kVrms internal galvanic
isolation, designed for high system efficiency and reliability in high
power applications. The devices accept complementary inputs and
depending on the pin configuration, offer options such as Active
Miller Clamp (NCD57080A), negative power supply (NCD57080B)
and separate high and low (OUTH and OUTL) driver outputs
(NCD57080C) for system design convenience. NCD57080 (A/B/C)
accommodate wide range of input bias voltage and signal levels
from 3.3 V to 20 V. NCD57080 (A/B/C) are available in narrow−body
SOIC−8 package.
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8
1
SOIC−8 NB
CASE 751−07
MARKING DIAGRAM
8
Features
• High Peak Output Current (+6.5 A/−6.5 A)
• Low Clamp Voltage Drop Eliminates the Need of Negative Power
Supply to Prevent Spurious Gate Turn−on (NCD57080A)
• Short Propagation Delays with Accurate Matching
• IGBT Gate Clamping during Short Circuit
NCD57080x
ALYW
G
1
NCD57080
x
= Specific Device Code
= A/B/C
= Assembly Location
= Wafer Lot
= Year
• IGBT Gate Active Pull Down
A
L
Y
W
G
• Tight UVLO Thresholds for Bias Flexibility
• Wide Bias Voltage Range including Negative V
• 3.3 V, 5 V, and 15 V Logic Input
• 3.75 kVrms Galvanic Isolation
• High Transient Immunity
(NCD57080B)
EE2
= Work Week
= Pb−Free Package
PIN CONNECTIONS
• High Electromagnetic Immunity
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
V
DD1
GND2
CLAMP
OUT
Compliant
IN+
IN−
Typical Applications
• Motor Control
• Uninterruptible Power Supplies (UPS)
• Industrial Power Supplies
• HVAC
GND1
V
DD2
NCD57080A
NCD57080B
V
DD1
V
EE2
IN+
IN−
GND2
OUT
GND1
V
DD2
V
GND2
OUTL
OUTH
DD1
IN+
IN−
GND1
V
DD2
NCD57080C
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
August, 2020 − Rev. 1
NCD57080A/D
NCD57080A, NCD57080B, NCD57080C
V
DD2
V
DD1
UVLO1
UVLO2
V
DD2
V
DD1
IN−
OUT
IN+
Logic
Logic
2
GND1
VCLAMP−THR
1
+
−
CLAMP
GND2
2
Figure 1. Simplified Block Diagram, NCD57080A
V
DD2
V
DD1
V
DD2
V
DD1
IN+
OUT
CLAMP
GND2
IN−
GND1
Figure 2. Simplified Application Schematic, NCD57080A
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NCD57080A, NCD57080B, NCD57080C
V
DD2
V
DD1
UVLO1
UVLO2
V
DD2
V
DD1
IN−
OUT
IN+
V
EE2
Logic
Logic
GND1
1
GND2
2
Figure 3. Simplified Block Diagram, NCD57080B
V
DD2
V
DD1
V
DD2
V
DD1
IN+
OUT
IN−
GND2
GND1
V
EE2
Figure 4. Simplified Application Schematic, NCD57080B
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NCD57080A, NCD57080B, NCD57080C
V
DD1
V
DD2
UVLO1
UVLO2
V
DD2
V
DD1
IN−
OUTH
OUTL
IN+
Logic
Logic
GND2
GND1
2
1
Figure 5. Simplified Block Diagram, NCD57080C
V
DD1
V
DD2
V
DD2
V
DD1
IN+
OUTH
OUTL
GND2
IN−
GND1
Figure 6. Simplified Application Schematic, NCD57080C
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NCD57080A, NCD57080B, NCD57080C
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
V
DD1
1
Power
Input side power supply. A good quality bypassing capacitor is required from this
pin to GND1 and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than V
Please see Figure 8 for more details.
is present.
UVLO1−OUT−ON
IN+
IN−
2
3
I
I
Non inverted gate driver input. It is internally clamped to V
and has a pull−
DD1
down resistor of 50 kW to ensure that output is low in the absence of an input
signal. A minimum positive or negative going pulse−width is required at IN+ be-
fore OUT or OUTH/OUTL responds.
Inverted gate driver input. It is internally clamped to V
and has a pull−up
DD1
resistor of 50 kW to ensure that output is low in the absence of an input signal. A
minimum negative or positive going pulse−width is required at IN− before OUT
or OUTH/OUTL responds.
GND1
4
5
Power
Power
Input side ground reference.
V
DD2
Output side positive power supply. The operating range for this pin is from
UVLO2 to its maximum allowed value. A good quality bypassing capacitor is
required from this pin to GND2 and should be placed close to the pins for best
results.
GND2
8
Power
Output side gate drive reference connecting to IGBT emitter or FET source.
(NCD57080A,
NCD57080C)
GND2
(NCD57080B)
7
6
OUT
O
Driver output that provides the appropriate drive voltage and source/sink current
to the IGBT/FET gate. OUT is actively pulled low during start−up.
(NCD57080A,
NCD57080B)
OUTH
6
7
7
O
O
O
Driver high output that provides the appropriate drive voltage and source current
to the IGBT/FET gate.
(NCD57080C)
OUTL
(NCD57080C)
Driver low output that provides the appropriate drive voltage and sink current to
the IGBT/FET gate. OUTL is actively pulled low during start−up.
CLAMP
(NCD57080A)
Provides clamping for the IGBT/FET gate during the off period to protect it from
parasitic turn−on. Its internal N FET is turned on when the voltage of this pin falls
below V
. It is to be tied directly to IGBT/FET gate with minimum trace
CLAMP−THR
length for best results.
V
8
Power
Output side negative power supply. A good quality bypassing capacitor is re-
quired from this pin to GND2 and should be placed close to the pins for best
results.
EE2
(NCD57080B)
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NCD57080A, NCD57080B, NCD57080C
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted.
Parameter
Symbol
Minimum
−0.3
−0.3
−18
Maximum
Unit
V
Supply voltage, input side
V
V
GND1
DD1−
22
32
0.3
36
Positive Power Supply, output side
GND2
GND2
V
DD2−
Negative Power Supply, output side
V
V
EE2−
Differential Power Supply, output side (NCD57080B)
V
V
MAX2
0
V
DD2− EE2
(V
)
Gate−driver output high voltage
NCD57080A
V
V
− GND2
− GND2
− GND2
V
DD2
+ 0.3
V
V
OUT
NCD57080B
NCD57080C
OUT
V
OUTH
Gate−driver output low voltage
NCD57080A
V
OUT
− GND2
−0.3
NCD57080B
V − V
OUT EE2
NCD57080C
V
OUTL
− GND2
Gate−driver output sourcing current
I
6.5
A
A
PK−SRC
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
DD2
= 15 V, V
= 0 V)
EE2
Gate−driver output sinking current
I
6.5
2.5
10
PK−SNK
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
DD2
= 15 V, V
= 0 V)
EE2
Clamp sinking current
I
A
PK−CLAMP
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
= 2.5 V)
CLAMP
Maximum Short Circuit Clamping Time
(I = 500 mA)
t
ms
CLP
OUT_CLAMP
Voltage at IN+, IN−
V
GND1
−0.3
−0.3
V
V
+ 0.3
V
V
LIM−
DD1
Clamp Voltage
V
GND2
+ 0.3
CLAMP−
DD2
Power Dissipation (SOIC−8 narrow package) with 4−layer board
Input to Output Isolation Voltage
PD
1315
mW
V
V
ISO
−1200
−40
1200
150
150
2
Maximum Junction Temperature
T (max)
°C
°C
kV
kV
−
J
Storage Temperature Range
T
STG
−65
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Moisture Sensitivity Level
ESDHBM
ESDCDM
MSL
2
1
Lead Temperature Soldering Reflow, Pb−Free (Note 3)
T
SLD
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCD57080A, NCD57080B, NCD57080C
Table 3. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
95 (4−layer board)
175 (1−layer board)
RqJA
°C/W
Thermal Characteristics, SOIC−8 narrow body (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES (Note 6)
Parameter
Symbol
Min
UVLO1
UVLO2
−15
Max
20
30
0
Unit
Supply voltage, input side
V
V
V
V
DD1−GND1
DD2−GND2
Positive Power Supply, output side
Negative Power Supply, output side (NCD57080B)
Differential Power Supply, output side (NCD57080B)
Low level input voltage at IN+, IN− (Note 7)
High level input voltage at IN+, IN− (Note 7)
Common Mode Transient Immunity
V
V
EE2−GND2
V
(V
MAX2
)
0
32
V
DD2−VEE2
V
IL
0
0.3 x V
V
DD1
DD1
V
IH
0.7 x V
V
V
DD1
|dV /dt|
100
kV/ms
°C
ISO
Ambient Temperature
T
A
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
7. Table values are valid for 3.3 V and 5 V V
, for higher V
voltages, the threshold values are maintained at the 5 V V
levels.
DD1
DD1
DD1
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NCD57080A, NCD57080B, NCD57080C
Table 5. ELECTRICAL CHARACTERISTICS V
= 5 V, V
= 15 V, (V
= 0 V for NCD57080B).
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VOLTAGE SUPPLY
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
V
3.1
V
V
UVLO1−OUT−ON
V
2.4
0.1
UVLO1−OUT−OFF
V
V
UVLO1−HYST
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
V
12.4
11.5
12.9
12
1
13.4
12.5
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
V
V
V
UVLO2−HYST
Input Supply Quiescent Current
IN+ = Low, IN− = Low, V
IN+ = Low, IN− = Low
IN+ = Low, IN− = Low, V
IN+ = High, IN− = Low
= 3.3 V
= 15 V
I
2
2
mA
mA
mA
mA
mA
mA
mA
DD1
DD1−0−3.3
I
DD1−0−5
I
2
DD1
DD1−0−15
I
5.5
2
DD1−100−5
Output Positive Supply
Quiescent Current
IN+ = Low, IN− = Low, no load
IN+ = High, IN− = Low, no load
IN+ = Low, IN− = Low, no load,
I
DD2−0
I
2
DD2−100
Output Negative Supply
Quiescent Current
(NCD57080B)
I
2
EE2−0
V
EE2
= −8 V
IN+ = High, IN− = Low, no load,
I
2
mA
EE2−100
V
EE2
= −8 V
LOGIC INPUT AND OUTPUT
IN+, IN−, Low Input Voltage
V
0.3 x
DD1
V
V
V
IL
(Note 7)
V
IN+, IN−, High Input Voltage
(Note 7)
V
IH
0.7 x
DD1
V
Input Hysteresis Voltage
(Note 7)
V
I
0.15 x
DD1
IN−HYST
V
IN− Input Current
V
IN−
V
IN−
V
IN−
V
IN−
V
IN+
V
IN+
V
IN+
V
IN+
= 0 V, V
= 0 V
= 3.3 V
100
100
100
100
100
100
100
100
10
mA
mA
mA
mA
mA
mA
mA
mA
ns
DD1
IN−L−3.3
I
IN−L−5
= 0 V, V
= 0 V, V
= 15 V
= 20 V
I
DD1
DD1
IN−L−15
IN−L−20
I
IN+ Input Current
= V
= 3.3 V
= 5 V
I
IN+H−3.3
DD1
= V
= V
= V
I
IN+H−5
DD1
DD1
DD1
= 15 V
= 20 V
I
IN+H−15
IN+H−20
I
Input Pulse Width of IN+, IN− for
Guaranteed No Response at
Output
t
ON−MIN1
Input Pulse Width of IN+, IN− for
t
40
ns
V
ON−MIN2
Guaranteed Response at Output
DRIVER OUTPUT
Output Low State
I
I
= 200 mA
V
V
0.15
0.3
0.8
SINK
OUTL1
(V
(V
(V
– GND2 for NCD57080A)
OUT
OUT
OUTL
– V
for NCD57080B)
EE2
= 1.0 A, T = 25°C
SINK
A
OUTL2
– GND2 for
NCD57080C)
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NCD57080A, NCD57080B, NCD57080C
Table 5. ELECTRICAL CHARACTERISTICS V
= 5 V, V
= 15 V, (V
= 0 V for NCD57080B).
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
DRIVER OUTPUT
Output High State
I
I
= 200 mA
V
V
0.2
0.35
1.0
V
SRC
OUTH1
(V
DD2
(V
DD2
(V
DD2
– V
– V
– V
for NCD57080A)
for NCD57080B)
for NCD57080C)
OUT
OUT
OUTL
= 1.0 A, T = 25°C
SRC
A
OUTH2
Peak Driver Current, Sink
Peak Driver Current, Source
MILLER CLAMP (NCD57080A)
Clamp Voltage
I
6.5
6.5
A
A
PK−SNK1
I
PK−SRC1
I
I
= 2.5 A, T = 25°C
V
CLAMP
2
V
CLAMP
A
= 2.5 A,
T = −40°C to 125°C
3.5
2.5
CLAMP
A
Clamp Activation Threshold
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage, Sourcing
V
1.5
2
V
V
CLAMP−THR
IN+ = Low, IN− = High,
V
0.7
0.9
1.5
1.7
CLAMP−OUTH
(V
OUT
/ V
OUTH
– V
)
I
= 500 mA,
DD2
CLAMP−OUT/OUTH
(pulse test, t
= 10 ms)
CLPmax
Clamping Voltage, Sinking
(V − V
IN+ = High, IN− = Low,
I = 500 mA,
CLAMP−OUTL
(pulse test, t
V
0.8
1.1
V
V
CLAMP−OUTL
)
OUTL
DD2
= 10 ms)
CLPmax
Clamping Voltage, Clamp
(V − V ) (NCD57080A)
IN+ = High, IN− = Low,
= 500 mA
V
CLAMP−CLAMP
I
CLAMP−CLAMP
CLAMP
DD2
(pulse test, t
= 10 ms)
CLPmax
DYNAMIC CHARACTERISTIC
IN+, IN− to Output High
Propagation Delay
C
IH
= 10 nF
LOAD
V
to 10% of output change
Pulse Width > 150 ns.
V
DD1
V
DD1
V
DD1
V
DD1
= V
= V
= V
= V
= 3.3V, V
= 0 V
t
PD−ON−3.3
40
40
40
40
60
60
60
60
90
90
90
90
ns
ns
ns
ns
IN+
IN+
IN+
IN+
IN−
= 5 V, V
= 0 V
t
PD−ON−5
IN−
= 15 V, V
= 20 V, V
= 0 V
= 0 V
t
IN−
IN−
PD−ON−15
PD−ON−20
t
IN+, IN− to Output Low
Propagation Delay
C
IH
= 10 nF
LOAD
V
to 10% of output change
Pulse Width > 150 ns.
V
V
V
V
= V
= V
= V
= V
= 3.3 V, V
= 0 V
t
PD−OFF−3.3
40
40
40
40
60
60
60
60
−6
90
90
90
90
ns
ns
ns
ns
ns
ns
ns
DD1
DD1
DD1
DD1
IN+
IN+
IN+
IN+
IN−
= 5 V, V
= 0 V
t
PD−OFF−5
IN−
= 15 V, V
= 20 V, V
= 0 V
= 0 V
t
IN−
IN−
PD−OFF−15
PD−OFF−20
t
Propagation Delay Distortion
T = 25°C, PW > 150 ns
A
t
DISTORT
(= t
− t
PD−OFF
)
PD−ON
T = −40°C to 125°C, PW > 150 ns
A
−25
−30
25
30
Prop Delay Distortion between
Parts
PW > 150 ns
t
0
13
DISTORT_TOT
Rise Time (see Fig. 3)
Fall Time (see Fig. 3)
UVLO1 Fall Delay
C
= 1 nF,
ns
ns
ns
LOAD
10% to 90% of Output Change
C
= 1 nF,
13
LOAD
90% to 10% of Output Change
t
1500
UVF1
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NCD57080A, NCD57080B, NCD57080C
Table 5. ELECTRICAL CHARACTERISTICS V
= 5 V, V
= 15 V, (V
= 0 V for NCD57080B).
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTIC
UVLO1 Rise Delay
UVLO2 Fall Delay
UVLO2 Rise Delay
t
770
1000
1000
ns
ns
ns
UVR1
t
UVF2
UVR2
t
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Values based on design and/or characterization.
V
IH
V
IL
IN+
t
t
tOFF-MIN1
FALL
RISE
t
ON−MIN2
90%
t
PD−ON
t
ON−MIN1
t
PD−OFF
OUT/OUTH
10%
Figure 7. Propagation Delay, Rise and Fall time
V
DD2
V
UVLO1 OUT ON
V
UVLO1 OUT OFF
V
DD1
t
t
UVF1
t
UVF1
UVR1
t
t
UVR1
UVR1
t
UVR1−spread
IN+
OUT/OUTH
Figure 8A. UVLO1 and Associated Timing Waveforms
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NCD57080A, NCD57080B, NCD57080C
V
DD2
V
UVLO1 OUT ON
V
UVLO1 OUT OFF
t
V
DD1
UVF1
t
UVR1
t
t
UVR1
UVR1
t
t
UVR1−spread
UVR1
IN+
OUT/OUTH
Figure 8B. UVLO1 Waveforms Depicting VDD1 Glitch Filtering
V
DD1
V
UVLO2 OUT ON
V
UVLO2 OUT OFF
V
DD2
t
t
UVF2
t
UVF2
UVR2
t
t
UVR2
UVR2
t
UVR2−spread
IN+
OUT/OUTH
Figure 8C. UVLO2 and Associated Timing Waveforms
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NCD57080A, NCD57080B, NCD57080C
V
DD1
V
UVLO2 OUT ON
V
UVLO2 OUT OFF
V
DD2
t
UVF2
t
UVR2
t
t
UVR2
UVR2
t
t
UVR2−spread
UVR2
IN+
OUT/OUTH
Figure 8D. UVLO2 Waveforms Depicting VDD2 Glitch Filtering
V
DD1
Clamping
Circuit
IN+
Figure 9. Input Pin Structure
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NCD57080A, NCD57080B, NCD57080C
TYPICAL CHARACTERISTICS
5
4
3
2
1
0
5
4
3
2
1
0
−50
−25
0
25
50
75
100 125
−50
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
V
= 3V3, IN+ = 0%
= 3V3, IN+ = 100%
= 3V3, IN+ = 50%
V
V
V
= 20 V, IN+ = 0%
= 20 V, IN+ = 50%
= 20 V, IN+ = 100%
DD1
DD1
DD1
DD1
V
V
DD1
DD1
Figure 10. IDD1 Supply Current VDD1 = 3.3 V
Figure 11. IDD1 Supply Current VDD1 = 20 V
5
4
3
2
1
0
2.5
2
1.5
1
0.5
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
Temperature [°C]
Temperature [°C]
V
V
V
= 5V, IN+ = 0%
= 5 V, IN+ = 100%
= 5 V, IN+ = 50%
V
V
= 15 V, IN+ = LOW
DD1
DD2
DD2
= 15 V, IN+ = V
DD1
DD1
DD1
Figure 12. IDD1 Supply Current VDD1 = 5 V
Figure 13. IDD2 Supply Current VDD2 = 15 V
2.5
20
15
10
5
2
1.5
1
0.5
0
−50
0
−25
0
25
Temperature [°C]
= 30 V, IN+ = LOW
50
75
100
125
1
10
100
1000
f [kHz]
V
V
DD2
DD2
CG = 100 nF
CG = 10 nF
CG = 1 nF
= 30 V,IN+ = V
DD1
Figure 14. IDD2 Supply Current VDD2 = 30 V
Figure 14a. IDD2 vs. Switching Frequency
www.onsemi.com
13
NCD57080A, NCD57080B, NCD57080C
TYPICAL CHARACTERISTICS (continued)
13.5
2.9
2.8
2.7
2.6
13
12.5
12
11.5
−50
−25
0
25
50
75
100 125
−50
−25
0
25
50
75
100 125
Temperature [°C]
Temperature [°C]
UVLO2 ON Threshold
UVLO2 OFF Threshold
UVLO1 ON Threshold
UVLO1 OFF Threshold
Figure 15. UVLO1 Threshold Voltage
Figure 16. UVLO2 Threshold Voltage
3
2.1
2.5
2
2
1.9
1.8
1.5
1
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 17a. Miller Clamp Voltage (2.5 A)
Figure 17b. Miller Clamp Activation
Voltage Threshold
1.5
1.4
1.3
1.2
1.1
1
72
70
68
66
64
62
0.9
0.8
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
125
125
Temperature [°C]
Temperature [°C]
IN+, V
= 5 V
DD1
VOUT−V
SCKT CLAMPING
DD2
IN−,V
= 5 V
DD1
VCLAMP−V
SCKT CLAMPING
DD2
Figure 19. Propagation Delay Turn−on
Figure 18. IGBT Short Circuit CLAMP
Voltage Drop
www.onsemi.com
14
NCD57080A, NCD57080B, NCD57080C
TYPICAL CHARACTERISTICS (continued)
15
71
69
67
65
14
13
12
−50
−25
0
25
Temperature [°C]
= 5 V
50
75
100
125
−50
−25
0
25
Temperature [°C]
= 5 V
50
75
100
125
IN+, V
DD1
IN+, V
IN−, V
DD1
DD1
IN−, V
= 5 V
DD1
= 5 V
Figure 20. Propagation Delay Turn−off
Figure 21. Rise Time
14
50
40
30
20
13
12
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
IN+, V
= 5 V
= 5 V
DD1
V
DD1
V
DD1
= 3V3
= 5 V
V
V
= 15 V
= 20 V
DD1
IN−, V
DD1
DD1
Figure 22. Fall Time
Figure 23. Input Current – Positive Input
−30
−35
−40
−45
−50
−55
−60
125
−50
−25
0
25
50
75
100
Temperature [°C]
V
DD1
V
DD1
= 3V3
= 5 V
V
V
= 15 V
= 20 V
DD1
DD1
Figure 24. Input Current – Negative Input
www.onsemi.com
15
NCD57080A, NCD57080B, NCD57080C
Under Voltage Lockout (Refer to Figure 8A/8B/8C/8D)
UVLO ensures correct switching of IGBT connected to
the driver output.
value of 2 W has to be used in order to avoid interference of
the high di/dt with internal circuitry (e.g. UVLO2).
After the power−on of the driver there has to be a rising
edge applied to the IN+ or falling edge to the IN− in order
for the output to start following the inputs. This serves as a
protection against producing partial pulses at the output if
• The IGBT is turned−off and the output is disabled, if
the supply V
drops below V
or
DD1
UVLO1−OUT−OFF
V
DD2
drops below V
.
UVLO2−OUT−OFF
• The driver output does not follow the input signal on
the V
or V
is applied in the middle of the input PWM
DD1
DD2
IN+ or IN− until the V rises above the
DDX
pulse.
If the V
V
and the input signal rising edge is
UVLOX−OUT−ON
rises over V
level the PWM
DD2
UVLO−OUT−ON
applied to the IN+ or IN−
will appear on the output after t
+ t
. The
UVR2
UVR2−spread
• V
is not monitored (NCD57080B)
EE2
t
time is variable and is defined as a time from
UVR2−spread
end of t
to first rising edge on IN+ input. If the V
UVR2
DD2
With high loading gate capacitances over 10 nF it is
important to follow the decoupling capacitor routing
guidelines as shown on Figure 32. The decoupling capacitor
value should be at least 10 mF. Also gate resistor of minimal
is starting from 0 V the time until PWM is at the output of
the driver is longer than t + t . This is caused
by start up time of internal circuits of the driver.
UVR2 UVR2−spread
www.onsemi.com
16
NCD57080A, NCD57080B, NCD57080C
ACTIVE MILER CLAMP PROTECTION (CLAMP)
NCD57080B supports bipolar power supply to prevent
unintentional turning on.
For operation with unipolar supply, typically,
V = 15 V with respect to GND2, and V = GND2. In
DD2
EE2
For operation with bipolar supplies, the IGBT is turned off
with a negative voltage through OUT with respect to its
emitter. This prevents the IGBT from unintentionally
turning on because of current induced from its collector to
its gate due to Miller effect. Typical values for bipolar
this case, the IGBT can turn on due to additional charge from
IGBT Miller capacitance caused by a high voltage slew rate
transition on the IGBT collector. To prevent IGBT to turn on,
the CLAMP pin is connected directly to IGBT gate and
Miller current is sinked through a low impedance CLAMP
transistor. When the IGBT is turned−off and the gate voltage
operation are V
GND2.
= 15 V and V
= −5 V with respect to
DD2
EE2
transitions below V , the CLAMP output is activated
CLAMP
NCD57080A supports unipolar power supply with active
Miller clamp.
OUT/OUTH
OUT/OUTH
Figure 25. Current Path with Miler Clamp Protection
Figure 26. Current Path without Miler Clamp Protection
Non−inverting and Inverting Input Pin (IN+, IN−)
NCD57080x has two possible input modes to control
IGBT. Both inputs have defined minimum input pulse width
to filter occasional glitches.
• Non−inverting input IN+ controls the driver output
while inverting input IN− is set to LOW
NCD57080B is designed to support bipolar power supply.
For reliable high output current delivery suitable external
power capacitors are required. Parallel combination of
100 nF + 4.7 mF ceramic capacitors is optimal for a wide
range of applications using IGBT. For reliable driving of
IGBT modules (containing several parallel IGBTs) a higher
capacity is required (typically 100 nF + 10 mF). Capacitors
should be as close as possible to the driver’s power pins.
• In bipolar power supply the driver is typically supplied
• Inverting input IN− controls the driver output while
non−inverting input IN+ is set to HIGH
WARNING: When the application uses an independent
or separate power supply for the control
unit and the input side of the driver, all
inputs should be protected by a serial
with a positive voltage of 15 V at V
and negative
DD2
voltage −5 V at V
(Figure 27). Negative power
EE2
supply prevents a dynamic turn on through the internal
IGBT input capacitance
resistor (In case of a power failure of the
driver, the driver may be damaged due to
overloading of the input protection circuits)
• In Unipolar power supply the driver is typically
supplied with a positive voltage of 15 V at V
.
DD2
Dynamic turn on through the internal IGBT input
capacitance could be prevented by Active Miler Clamp
function (NCD57080A). CLAMP output should be
directly connected to IGBT gate (Figure 25)
Power Supply (VDD1, VDD2, VEE2
NCD57080A and NCD57080C are designed to support
unipolar power supply.
)
www.onsemi.com
17
NCD57080A, NCD57080B, NCD57080C
V
DD1
V
EE2
V
DD1
IN+
IN-
GND2
OUT
10 µF
100 n
V
EE2
-
+
-
+
100 n 10 µF
GND 1
V
DD2
V
DD2
10 µF
100 n
+
-
Figure 27. Bipolar Power Supply NCD57080B
V
GND2
CLAMP
OUT
DD1
V
DD1
IN+
IN-
+
100 n
10 µF
-
GND1
V
DD2
V
DD2
10µF
100 n
+
-
Figure 28. Unipolar Power Supply NCD57080A
V
GND2
OUTL
OUTH
DD1
V
DD1
IN+
IN-
+
-
100 n
10 µF
GND1
V
DD2
V
DD2
10 µF
100 n
+
-
Figure 29. Suggested Bypassing Scheme for NCD57080x
www.onsemi.com
18
NCD57080A, NCD57080B, NCD57080C
Common Mode Transient Immunity (CMTI)
10µF
+
GND2
CLAMP
OUT
V
DD1
+
-
IN+
IN-
S1
5V
OUT must remain stable
-
V
DD2
GND1
15V
+
10µF
-
HV PULSE
10µF
+
GND2
OUTL
OUTH
V
DD1
+
-
IN+
IN-
S1
5V
OUT must remain stable
-
V
DD2
GND1
15V
+
-
10µF
HV PULSE
10µF
+
V
EE2
V
DD1
+
GND2
OUT
IN+
IN-
S1
5V
-
-
OUT must remain stable
V
DD2
GND1
15V
+
-
10µF
HV PULSE
Figure 30. Common−Mode Transient Immunity Test Circuit
High-speed signals
Ground plane
10 mils
0.25 mm
10 mils
0.25 mm
Keep this space free
40 mils
1 mm
40 mils
1 mm
from traces, pads and
vias
Power plane
10 mils
0.25 mm
10 mils
0.25 mm
Low-speed signals
157 mils
(4 mm)
Figure 31. Recommended Layer Stack
www.onsemi.com
19
NCD57080A, NCD57080B, NCD57080C
Figure 32. Recommended Layout
www.onsemi.com
20
NCD57080A, NCD57080B, NCD57080C
ORDERING INFORMATION
Device
†
Package
Shipping
NCD57080ADR2G
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8 Narrow Body, (Pb−Free)
SOIC−8 Narrow Body, (Pb−Free)
NCD57080BDR2G
(In Development)
NCD57080CDR2G
2500 / Tape & Reel
SOIC−8 Narrow Body, (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
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