NCL2801CDBDR2G [ONSEMI]
Power Factor Controller, High-Efficiency, Enhanced for Lighting;
| 型号： | NCL2801CDBDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Power Factor Controller, High-Efficiency, Enhanced for Lighting 光电二极管 |
| 文件： | 总28页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Power Factor Controller,
High-Efficiency,
Enhanced for Lighting
NCL2801
The 8−pin PFC controller NCL2801 is designed to drive PFC boost
stages. It is based on an innovative Valley Count Frequency
Fold−back (VCFF) method. The circuit classically operates in
Critical conduction Mode (CrM) for high load values. When the load
decreases a Discontinuous Conduction Mode DCM is forced by
forcing a dead time which, by construction corresponds to a fixed
number of valleys. The lower the output power, the higher the number
of valleys corresponding to the dead time. After DCM works down to
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8
1
SOIC−8
CASE 751
th
6 valley switching and if the load continues to decrease, a dead time
th
is continuously added to the 6 valley. The end of additional dead time
is synchronized with the drain voltage valley. The maximum
switching period is limited to 36.5 ms. VCFF maximizes the
efficiency during DCM and light load. In particular, the stand−by
losses are reduced to a minimum. Like in FCCrM controllers, internal
circuitry allows near−unity power factor even when the switching
frequency is reduced. Housed in a SO−8 package, the circuit also
incorporates the features necessary for robust and compact PFC
stages, with few external components.
MARKING DIAGRAMS
8
L2801abc
ALYW
G
1
General Features
L2801abc = Specific Device Code
• Near−Unity Power Factor
• Critical Conduction Mode (CrM)
• Valley Count Frequency Fold−Back (VCFF)
• Peak Current Control Mode to Maintain a Proper Current Shaping in
VCFF Mode
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Fast Line / Load Transient Compensation (Dynamic Response
PIN CONNECTIONS
Enhancer) Option
1
FB
VCC
• Brown−out Detection
• Two−level Line Feed−Forward (HL&LL)
VCTRL
DRV
GND
ZCD
MULT
CS
• Valley Turn−on (No Valley Hoping by Construction)
• High Drive Capability: −500 mA / +800 mA
(Top Views)
• V Range: from 10.5 V to 27 V
CC
• Low Start−up Consumption for :
• [*C*]& [*D*] Option: Low V Start−up Level (12.5 V)
CC
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of
this data sheet.
[*A*]& [*B*] Option: High V Start−up Level (17.0 V)
CC
[*E*]& [*F*] Option: High V Start−up Level (10.5 V)
CC
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
September, 2019 − Rev. 3
NCL2801/D
NCL2801
Safety Features
Typical Applications
• Thermal Shutdown
• PC Power Supplies
• Lighting Ballasts (LED, Fluorescent)
• Flat TV
• Non−latching, Over−Voltage Protection (3 Prog Levels)
• Over Current Limitation
• Low Duty−Cycle Operation if the Bypass Diode is
• All Off Line Appliances Requiring Power Factor
Shorted
Correction
Several product configurations coded with three letters
• Open Ground Pin Fault Monitoring
• Pin CS shorted to GND or open Monitoring
(L ,L L ) marked on the package will be available
1
2,
3
• Pin ZCD open tested before controller starts
• Controller not allowed to start if MULT pin is left open
Table 1. NCL2801 1ST LETTER CODING OF PRODUCT VERSIONS
L
1
Soft OVP (% of V
)
Fast OVP (% of V
)
REF
REF
A
Disabled
112.5
B
Disabled
110.0
C (default)
105.0
107.0
1. The NCL2801 SO8 package is marked L L L
2 3
1
Table 2. NCL2801 2ND LETTER CODING OF PRODUCT VERSIONS
L2
VCC Startup Level (V)
DRE (After Startup)
DRE (During Startup)
A
17.0
17.0
12.5
12.5
10.5
10.5
NO
YES
NO
YES
YES
YES
YES
YES
YES
B
C
D (default)
YES
NO
E
F
YES
2. The NCL2801 SO8 package is marked L L L
2 3
1
Table 3. NCL2801 3RD LETTER CODING OF PRODUCT VERSIONS
L
3
Brown−in & Brown−out
Line Range Detection w/ 2−level Line Feed−Forward
A (default)
YES
YES
NO
YES
NO
B
C
D
YES
NO
NO
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2
NCL2801
D2
Vin
Np
D1
V
I
L
bulk
L
Naux
Rfb1
RZCD
VCC
AC line
Rmult1
Cbulk
Cin
LOAD
EMI
Filter
FB
VCC
1
8
7
6
5
DRV
GND
VCTRL
2
MULT
Q1
Rfb2
3
CS
ZCD
Rmult2
4
Rz
Cz
Cp
RCS
Rsense
Figure 1. NCL2801 Application Schematic
Table 4. NCL2801 3RD LETTER CODING OF PRODUCT VERSIONS
Pin
Number
Name
Function
This pin receives a portion of the PFC output voltage for the regulation and the optional Dynamic Response
Enhancer (DRE) that drastically speeds−up the loop response when the output voltage drops below 95.5 % of
the desired output level.
FB pin voltage V is also the input signal for the (non−latching) Over−Voltage (OVP). The UVP comparator
FB
prevents operation as long as FB pin voltage is lower than V
internal voltage reference. A SOFTOVP com-
UVPH
1
FB
parator gradually reduces the duty−ratio when FB pin voltage
exceeds 105% of V (option dependent). If despite of this, the output voltage still increases, the driver is im-
REF
mediately disabled by fast OVP if the output voltage exceeds x% of the desired level (option dependent)..
A 250−nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is
accidently left open.
The error amplifier output is available on this pin. The network connected between this pin and ground adjusts
the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios.
VCTRL pin is internally pulled down when the circuit is off so that when it starts operation, the power increases
slowly to provide a soft−start function.
2
VCTRL
VCTRL pin must not be controlled or pulled down externally.
Pulled to GND if BO and at startup (pseudo−soft start). Just a switch.
Multiplier input pin. This pin receives a scaled down rectified mains voltage by the means of a resistor voltage
divider connected between Vin and GND.
.
3
4
MULT
CS
This pin senses the MOSFET current in order to end the on−time when the current reaches the control value or
the maximum current limit.
Just before startup, the value of the resistance between CS pin and GND pin is sensed for determining the
VCTRL value of the CrM to DCM threshold.
5
6
ZCD
GND
This pin uses the auxiliary winding voltage to determine the inductor current zero crossing.
Connect this pin to the PFC stage ground.
The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to effectively drive high
gate charge power MOSFETs.
7
DRV
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17.0 V ([*A*] & [*B*]
Versions) or 12.5 V ([*C*] & [*D*] Versions) or 10.5 V ([*E*] & [*F*] Options) and turns off when VCC goes below
10.0 V (typ) for [*C*] & [*D*] Options and below 9.0 V (typ) for [*A*] & [*B*] &[*E*] & [*F*] Options. After start−up,
the operating range is 10.0 V (or 9 V depending on option) up to 27 V.
8
VCC
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3
NCL2801
Table 5. MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
Value
Unit
FB
1
Feedback Pin
−0.3, +9
V
−0.3, V
ctrl,max
VCTRL
2
V
pin
V
CONTROL
(Note 3)
MULT
CS
3
4
5
Multiplier Input pin
CS Pin
−0.3, +9
V
V
V
−0.3, +9
ZCD
ZCD Pin
−0.3, VCC+0.3
Driver Voltage
Driver Current
−0.3, V
(Note 3)
V
DRV
DRV
VCC
7
8
−500, +800
mA
Power Supply Input
−0.3, + 27
V
Power Dissipation and Thermal Characteristics
P
q
300
180
mW
D
ja
Maximum Power Dissipation @ T =70°C
A
R
°C/W
Thermal Resistance Junction to Air
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
T
−40 to + 125
150
°C
°C
°C
°C
−
J
T
J,max
S,max
T
−65 to 150
300
T
Lead Temperature (Soldering, 10s)
Moisture Sensitivity Level
L,max
MSL
1
ESD Capability, HBM model (Note 4)
ESD Capability, Machine Model (Note 4)
ESD,CDM
> 2000
> 200
1000
V
V
V
3. “V
” is the VCTRL pin clamp voltage. “V
” is the DRV clamp voltage (V
) if V is higher than (V
). “V
” is V
CC
ctrl,max
DRV
DRVhigh
CC
DRVhigh
DRV
otherwise.
4. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
5. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, T = −40°C to +125°C, unless otherwise specified) (Note 6)
J
Symbol
Rating
Min
Typ
Max
Unit
START−UP AND SUPPLY CIRCUIT
Start−Up Threshold, V increasing:
CC
9.75
11.6
15.6
10.5
12.50
16.7
11.25
13.4
18.00
V
V
V
[*E*] & [*F*] Versions
[*C*] & [*D*] Versions
[*A*] & [*B*] Versions
V
CC,on
V
CC,off
V
CC,rst
Minimum Operating Voltage, V falling
CC
9.3
8.4
10.0
9.0
10.7
9.6
V
V
[*C*] & [*D*] Versions
[*A*] & [*B*] & [*E*] & [*F*]
Voltage at which IC completely restarts
ICC drops to ~ ICC,start
6.50
7.2
7.80
V
(Min and Max values are guaranteed by functional testing)
Hysteresis (V
− V
)
CC,on
CC,off
0.75
1.25
6.00
1.6
2.5
7.7
3.0
3.75
10
V
V
V
[*E*] & [*F*] Versions
[*C*] & [*D*] Versions
[*A*] & [*B*] Versions
V
CC,hyst
I
Start−Up Current, V = 9.4 V, below startup voltage
0
0
10
0.4
60
mA
mA
mA
CC,start
CC
I
Operating Consumption, no switching.
1.00
3.00
CC,op1
I
Operating Consumption, 50−kHz switching, no load on DRV pin
1.0
2.00
CC,op2
GATE DRIVE
t
Output voltage rise−time @ C = 1 nF, 10−90% of output signal
15
10
4
30
20
10
7
90
50
20
15
ns
ns
W
R
L
t
Output voltage fall−time @ C = 1 nF, 10−90% of output signal
F
L
R
Source resistance @ 200 mV under High VCC
Sink resistance @ 200mV above Low VCC
OH
R
2
W
OL
DRV pin level for V = V
+ 200 mV
CC
CC,off
8.6
9.6
9.2
10
10
11
V
V
(10−kW resistor between DRV and GND)
[*A*] & [*B*] & [*E*] & [*F*]
V
DRV,low
[*C*] & [*D*] Versions
V
DRV pin level at V = 27 V (R = 33 kW & C = 1 nF)
10
0
12
14
V
DRV,high
CC
L
L
Maximum DRV voltage while forcing zero at DRV pin and injecting 10 mA
V
100
200
mV
DRV,L
into DRV pin @ V = 12 V
CC
REGULATION BLOCK
V
Feedback Voltage Reference
Error Amplifier Current Capability (source and sink)
Error Amplifier Gain
2.45
15
2.50
20
2.55
25
V
REF
I
mA
mS
EA
G
110
200
290
EA
VCTRL pin Voltage (V ):
FB
ctrl
4.4
0.4
4.5
0.5
4.6
0.6
V
V
− @ V = 2 V (OTA is sourcing 20 mA)
ctrl,max ctrl,min
− @ V = 3 V (OTA is sinking 20 mA)
V
FB
CURRENT SENSE BLOCK
Current Sense Voltage Reference for option w/o line level detection
[**B]&[**D] Options
V
V
0.97
1.45
1.07
1.60
1.19
1.78
V
V
CS_OCP(th)
At t
LEB,OCP
Current Sense Overstress Voltage Reference for option w/o line level
detection
CS_OVS(th)
[**B]&[**D] Options
At t
LEB,OVS
Current Sense Voltage Reference when Low Line is detected
[**A]&[**C] Options
V
V
0.97
1.45
1.07
1.60
1.19
1.78
V
V
CS_OCP_LL(th)
At t
LEB,OCP
Current Sense Overstress Voltage Reference when Low Line is detected
[**A]&[**C] Options
CS_OVS_LL(th)
At t
LEB,OVS
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, T = −40°C to +125°C, unless otherwise specified) (Note 6)
J
Symbol
Rating
Min
Typ
Max
Unit
Current Sense Voltage Reference when High Line is detected
[**A]&[**C] Options
V
V
0.53
0.58
0.66
V
CS_OCP_HL(th)
At t
LEB,OCP**
Current Sense Overstress Voltage Reference when High Line is detected
[**A]&[**C] Options
0.79
0.87
0.97
V
CS_OVS_HL(th)
At t
LEB,OVS
t
Leading edge Blanking Time for current control
Leading edge Blanking Time for Overstress
125
50
200
100
275
150
ns
ns
LEB,OCP
t
LEB,OVS
Over−Current Protection Delay from V >V
to
CS
CS(th)
DRV low
t
10
40
200
ns
OCP
Test: V > V + 100 mV
CS
CS
t
Watch Dog Timer in “OverStress” Situation
ZERO CURRENT DETECTION BLOCK
ZCD positive clamp (V = 12 V, I
400
800
1200
ms
WDG(OS)
V
= 5 mA)
ZCD
12.6
675
200
375
0
12.9
750
250
500
250
80
13.2
825
300
625
500
200
−
V
CL(pos)
CC
V
Zero Current Detection, V
rising
mV
mV
mV
nA
ns
ZCD(th)H
ZCD
V
Zero Current Detection, V
falling
ZCD(th)L
ZCD
V
Hysteresis of the Zero Current Detection Comparator
ZCD pin input leakage current
ZCD(hyst)
ZCD,bias
I
t
(V
ZCD
< V ) to (DRV high)
ZCD(th)L
20
ZCD
t
Minimum ZCD Pulse Width (Guaranteed by Design)
−
60
ns
SYNC
Watch Dog Timer
If no ZCD detected
t
80
200
320
ms
WDG
Pull−up current source to detect ZCD open pin
I
0.85
150
1
1.15
250
mA
ZCD,pu
At startup only
V
Voltage reference to test ZCD pin short during startup
200
mV
REF,ZCD,open
MULTIPLIER
Multiplier Gain (Note 2) for option w/o line level detection
[**B]&[**D] Options
K
0.34
0.22
0.72
2.9
0.38
0.24
0.80
3.3
0.42
0.28
0.88
3.7
1/V
1/V
1/V
mult
Multiplier Gain (Note 2) when High Line is detected
[**A]&[**C] Options
K
mult,HL
Multiplier Gain (Note 2) when Low Line is detected
[**A]&[**C] Options
K
mult,LL
Ration between K
and K
mult,HL
mult,LL
K
mult,Ratio
[**A]&[**C] Options
K
K
.V voltage added at the multiplier output
offset ton
K
0.10
0.140
0.20
offset
[**A]&[**C] Options (w/ Line Detection)
.V voltage added at the multiplier output
offset ton
K
V
0.040
200
0.075
280
0.12
350
offset_nld
[**B]&[**D] Options (w/o Line Detection)
Current pull−down on Mult pin
Maximum MULT pin voltage
I
nA
V
mult_pd
2.88
3.2
3.52
mult_max
Controller disabled if MULT pin voltage goes above this threshold
MAXIMUM ON−TIME
t
t
@ V
@ V
= 4.50 V
= 0.55 V
26
30
5
36
ms
ms
ON,max,A,2
ON,max,A,1
CTRL
3.6
6.9
CTRL
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, T = −40°C to +125°C, unless otherwise specified) (Note 6)
J
Symbol
Rating
Min
Typ
Max
Unit
R
VALUE IDENTIFICATION REFERENCE VOLTAGES
CS
Internal current sourced by CS pin into a 1% R resistor just before the
CS
I
0.96
20
1.0
50
1.04
100
280
530
880
mA
mV
mV
mV
mV
RCS
startup generates a voltage drop V
CS
Internal voltage reference for identifying the R resistor value
CS
RCS,REF,1
V
V
V
V
RCS,REF,1
RCS,REF,2
RCS,REF,3
RCS,REF,4
CS pin is said shorted to GND if V < V
CS
Internal voltage reference for identifying the R resistor value
CS
180
400
720
230
460
790
R
= 150 W if
< V < V
CS
RCS,REF,1 CS RCS,REF,2
Internal voltage reference for identifying the R resistor value
CS
R
= 330 W if V
< V < V
CS
RCS,REF,2 CS RCS,REF,3
Internal voltage reference for identifying the R resistor value
CS
R
= 620 W if V
< V < V
CS
RCS,REF,3 CS RCS,REF,4
Internal voltage reference for identifying the R resistor value
CS
R
= 1000 W if V
< V < V
CS
RCS,REF,4 CS
RCS,REF,5
RCS,REF,5
RCS open do not allow the controller to start
V
1190
1300
1400
mV
RCS,REF,5
CS pin open if V >V
CS
FREQUENCY FOLDBACK THRESHOLDS & HYSTERESIS
V
V
V
V
V
V
V
V
V
V
V
threshold for valley1 to valley2 forcing @R = 1000 W
1.971
1.647
1.332
1.008
0.693
1.008
1.332
1.647
1.971
2.286
300
2.19
1.83
1.48
1.12
0.77
1.12
1.48
1.83
2.19
2.54
356
2.409
2.013
1.628
1.232
0.847
1.232
1.628
2.013
2.409
2.794
420
V
V
CTRL,th,12,1000
CTRL,th,23, 1000
CTRL,th,34, 1000
CTRL,th,45, 1000
CTRL,th,56, 1000
CTRL,th,65, 1000
CTRL,th,54, 1000
CTRL,th,43, 1000
CTRL,th,32, 1000
CTRL,th,21, 1000
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CS
V
V
V
V
V
V
V
V
V
threshold for valley2 to valley3 forcing @R = 1000 W
CS
threshold for valley3 to valley4 forcing @R = 1000 W
V
CS
threshold for valley4 to valley5 forcing @R = 1000 W
V
CS
threshold for valley5 to valley6 forcing @R = 1000 W
V
CS
threshold for valley6 to valley5 forcing @R = 1000 W
V
CS
threshold for valley5 to valley4 forcing @R = 1000 W
V
CS
threshold for valley4 to valley3 forcing @R = 1000 W
V
CS
threshold for valley3 to valley2 forcing @R = 1000 W
V
CS
threshold for valley2 to valley1 forcing @R = 1000 W
V
CS
V
V
CTRL
hysteresis when changing forced valley @R = 1000 W
mV
CTRL,hyst, 1000
CS
V
V
V
V
V
V
V
V
V
V
V
threshold for valley1 to valley2 forcing @R = 620 W
1.647
1.413
1.170
0.927
0.693
0.927
1.170
1.413
1.647
1.890
200
1.830
1.570
1.300
1.030
0.770
1.030
1.300
1.570
1.830
2.100
267
2.013
1.727
1.430
1.133
0.847
1.133
1.430
1.727
2.013
2.310
320
V
V
CTRL,th,12,620
CTRL,th,23, 620
CTRL,th,34, 620
CTRL,th,45, 620
CTRL,th,56, 620
CTRL,th,65, 620
CTRL,th,54, 620
CTRL,th,43, 620
CTRL,th,32, 620
CTRL,th,21, 620
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CS
V
V
V
V
V
V
V
V
V
threshold for valley2 to valley3 forcing @R = 620 W
CS
threshold for valley3 to valley4 forcing @R = 620 W
V
CS
threshold for valley4 to valley5 forcing @R = 620 W
V
CS
threshold for valley5 to valley6 forcing @R = 620 W
V
CS
threshold for valley6 to valley5 forcing @R = 620 W
V
CS
threshold for valley5 to valley4 forcing @R = 620 W
V
CS
threshold for valley4 to valley3 forcing @R = 620 W
V
CS
threshold for valley3 to valley2 forcing @R = 620 W
V
CS
threshold for valley2 to valley1 forcing @R = 620 W
V
CS
V
V
CTRL
hysteresis when changing forced valley @R = 620 W
mV
CTRL,hyst, 620
CS
V
V
V
V
V
threshold for valley1 to valley2 forcing @R = 330 W
1.332
1.170
1.008
0.846
1.480
1.300
1.120
0.940
1.628
1.430
1.232
1.034
V
V
V
V
CTRL,th,12, 330
CTRL,th,23, 330
CTRL,th,34, 330
CTRL,th,45, 330
CTRL
CTRL
CTRL
CTRL
CS
V
threshold for valley2 to valley3 forcing @R = 330 W
CS
V
V
threshold for valley3 to valley4 forcing @R = 330 W
CS
threshold for valley4 to valley5 forcing @R = 330 W
CS
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, T = −40°C to +125°C, unless otherwise specified) (Note 6)
J
Symbol
Rating
threshold for valley5 to valley6 forcing @R = 330 W
Min
Typ
Max
0.847
1.034
1.232
1.430
1.628
1.826
230
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
0.693
0.846
1.008
1.170
1.332
1.494
120
0.770
0.940
1.120
1.300
1.480
1.660
178
CTRL,th,56, 330
CTRL,th,65, 330
CTRL,th,54, 330
CTRL,th,43, 330
CTRL,th,32, 330
CTRL,th,21, 330
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CS
threshold for valley6 to valley5 forcing @R = 330 W
V
CS
threshold for valley5 to valley4 forcing @R = 330 W
V
CS
threshold for valley4 to valley3 forcing @R = 330 W
V
CS
threshold for valley3 to valley2 forcing @R = 330 W
V
CS
threshold for valley2 to valley1 forcing @R = 330 W
V
CS
V
V
CTRL
hysteresis when changing forced valley @R = 330 W
mV
CTRL,hyst, 330
CS
V
V
threshold for valley1 to valley2 forcing @R = 150 W
1.008
0.927
0.846
0.774
0.693
0.774
0.846
0.927
1.008
1.089
35
1.120
1.030
0.940
0.860
0.770
0.860
0.940
1.030
1.120
1.210
89
1.232
1.133
1.034
0.946
0.847
0.946
1.034
1.133
1.232
1.331
135
V
V
CTRL,th,12,150
CTRL,th,23, 150
CTRL,th,34, 150
CTRL,th,45, 150
CTRL,th,56, 150
CTRL,th,65, 150
CTRL,th,54, 150
CTRL,th,43, 150
CTRL,th,32, 150
CTRL,th,21, 150
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CTRL
CS
V
V
V
V
V
V
V
V
V
V
threshold for valley2 to valley3 forcing @R = 150 W
CS
V
V
V
V
V
V
V
V
threshold for valley3 to valley4 forcing @R = 150 W
V
CS
threshold for valley4 to valley5 forcing @R = 150 W
V
CS
threshold for valley5 to valley6 forcing @R = 150 W
V
CS
threshold for valley6 to valley5 forcing @R = 150 W
V
CS
threshold for valley5 to valley4 forcing @R = 150 W
V
CS
threshold for valley4 to valley3 forcing @R = 150 W
V
CS
threshold for valley3 to valley2 forcing @R = 150 W
V
CS
threshold for valley2 to valley1 forcing @R = 150 W
V
CS
V
V
CTRL
hysteresis when changing forced valley @R = 150 W
mV
CTRL,hyst, 150
CS
SWITCHING CYCLE DEAD TIME
th
Dead time added after 6 valley
14
0
20
0.1
−
0.4
ms
ms
Vctrl = 0.50 V
Vctrl = 0.77 V
t
ADT
FEED−BACK OVER AND UNDER−VOLTAGE PROTECTIONS (OVP)
R
Ratio (Soft OVP Threshold, V rising) over V (Options [C**])
REF
103.5
0.8
105
1.3
106.5
3.2
%
%
%
%
%
%
softOVP,C
softOVP(HYST)
FB
R
Ratio (Soft OVP Hysteresis) over V
REF .
R
R
R
Ratio (Fast OVP Threshold, V rising) over V
(Options [A**])
(Option [B**])
(Option [C**])
REF
108.5
106.1
103.2
3.0
112.5
110
107
4.0
116.5
113.9
110.8
5.7
fastOVP,A
fastOVP,B
fastOVP,C
FB
REF
Ratio (Fast OVP Threshold, V rising) over V
FB
REF
Ratio (Fast OVP Threshold, V rising) over V
FB
R
Ratio (Fast OVP Hysteresis) over V
fastOVP(HYST)
REF
FB pin pull−down Current @ V = V
and V = V
FB UVP
FB
OVP
I
50
200
450
nA
B,FB
Pulls down the FB pin in case the pin is open (solder failure)
DYNAMIC RESPONSE ENHANCER (DRE)
Ratio (DRE Threshold, V falling) over V
R
94.0
0.8
95.7
2.0
97.5
3.0
%
%
DRE
DRE(HYST)
FB
REF
R
Ratio (DRE Hysteresis) over V
REF
Current measured out of VCTRL pin (DRE current source
minus max OTA current)
I
80
100
200
120
240
mA
mA
VCTRL,Startup
@ VFB=1V (PFCOK=0 ⇔ Startup)
Current measured out of VCTRL pin (DRE current source
minus max OTA current )
I
160
VCTRL,1,Steady
@ VFB=1V (PFCOK=1 ⇔ Steady State)
[*B*], [*D*], [*F*] Product Options
UNDER VOLTAGE PROTECTION / DISABLE
UVP Threshold, V increasing
V
UVPH
380
150
450
200
520
250
mV
mV
FB
V
UVPL
UVP Threshold, V decreasing
FB
www.onsemi.com
8
NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, T = −40°C to +125°C, unless otherwise specified) (Note 6)
J
Symbol
Rating
Min
Typ
Max
Unit
V
UVP Hysteresis
200
250
300
mV
UVP(HYST)
BROWN−OUT PROTECTION AND LINE FEED FORWARD
Brown−In Threshold, V
increasing
mains
V
BOH
725
634
787
709
860
770
mV
mV
Note: V
= 74, 80, 87 V assuming 1/K = 144
line,BOH,rms
m
Brown−Out Threshold, V
line,BOL,rms
decreasing
mains
V
BOL
Note: V
= 64, 72, 78 V assuming 1/K = 144
m
V
Brown−Out Comparator Hysteresis
Brown−Out Blanking Time
50
36
20
75
50
30
130
67
mV
ms
mA
BO(HYST)
t
BO(blank)
I
VCTRL pin sink current during BO condition
42
VCTRL(BO)
Comparator Threshold for Line Range Detection V
rising
falling
MULT
m
V
1.543
1.625
1.706
V
HL
Note: V
= 157,165,174 V assuming 1/K = 144
line,HL,rms
Comparator Threshold for Line Range Detection V
MULT
V
1.350
37
1.422
218
25
1.493
300
43
V
LL
Note: V
= 137,145,152 V assuming 1/K = 144
line,HL,rms
m
V
Comparator Hysteresis for Line Range Detection
Blanking Time for Line Range Detection
mV
ms
HL(hyst)
t
13
HL(blank)
(must stay below V for 25 ms before changing to LL)
LL
THERMAL SHUTDOWN
T
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
−
−
−
°C
°C
LIMIT
TEMP
H
−
50
6. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
7. In CrM mode, G
= V
/[(V
−0.5)*(1.5/4.0)*V
], V
is the CS pin voltage threshold at which DRV pin goes low (end of
mult
CS(th)
CTRL
MULT
CS(th)
on−time). K
is set to zero in test mode, otherwise the formula is more complex.
offset
www.onsemi.com
9
NCL2801
MULT
VREF,LLINE
OTA
SOURCING
VREF
FB
LINE& BO
MANAGMENT
VREF,BONOK
PFCOK
FFTH
FFTH
SENSE
FB
OFF
VREF,DRE
VREF,UVP
VREF,SOFT_OVP
VREF,FAST_OVP
VREGUL
DRE
UVP
MANAGMENT
VCTRL
MANAGMENT
STATICOVP
BONOK
SOFTOVP
VREF,OVS
FASTOVP
OVERSTRESS
OCP
VREF
VREF,XXXX
DRV
CURRENT
SENSE
ISENSE
THERMAL
SHUTDOWN
VDD
VREF,OCP
VCC
TSD
BONOK
UVP
OFF
FAULT
MANAGMENT
STATICOVP
ZERO
CROSSING
DETECTION
ZCD
DRV
VREF,VCC
UVLO
OFF
STATICOVP
STOP
FASTOVP
OCP
SOURCING
PFCOK
Q
S
R
OVERSTRESS
OFF
LLINE
MULT
BONOK
TONMX
RST
ON TIME
MANAGMENT
ISENSE
DRV
VCC
CLK
FFTH
VREGUL
DRV
ZCD
OVERSTRESS
PFCOK
VTON
Q
S
R
CLK
DT
VREGUL
DT
SOFTOVP
Output
Buffer
UVLO
Vton
Processing
Circuitry
VTON
CLK & DT
MANAGMENT
All RS latches are
reset dominat
Figure 2. NCL2801 Block Diagram (SOURCING Flag is High When OTA Sources
Current, if Sourcing Less Than 1nA SOURCING Flag Goes Low)
www.onsemi.com
10
NCL2801
DETAILED OPERATING DESCRIPTION
Introduction
under−shoot. This circuit limits possible deviations
from the regulation level as follows:
− NCL2801 linearly decays the power delivery to zero
when the output voltage exceeds the soft OVP limit
NCL2801 is designed for working with LED Lighting
applications coping with high ripple voltage on bulk
capacitor and providing optimized line current THD and
good efficiency. In addition, it incorporates protection
features for robust operation. More generally, NCL2801 is
ideal in systems where cost−effectiveness, reliability, low
line current THD, low stand−by power and high efficiency
are key requirements:
• Valley Count Frequency Fold−back: NCL2801 is
designed to drive PFC boost stages in so−called Valley
Count Frequency Fold−back (VCFF). In high load
current condition, the circuit classically operates in
(105% of V ) for option [C**]). Soft OVP feature
REF
is disabled on options [A**] &[B**]. If this soft
OVP is too smooth and the output continues to rise,
the circuit immediately (priority to Fast OVP)
interrupts the power delivery when the output
voltage is 112.5 % above its desired level (Fast
OVP) for options [A**]. Options [B**] & [C**] are
providing lower Fast OVP thresholds. Fast OVP
threshold is higher than Soft OVP threshold for
option [C**].
st
Critical conduction Mode (CrM) also called 1 valley
− While disabled on options [*A*], [*C*] and [*E*]
after startup time, NCL2801 has a DRE (Dynamic
Response Enhancer) circuitry on options [*B*],
[*D*]&[*F*] which dramatically speeds−up the
regulation loop when the output voltage goes below
95.5 % of its regulation level. The DRE function is
enabled only after the PFC stage has started−up to
allow normal soft−start operation to occur. For all
the product options, the DRE is active during the
start−up phase to accelerate the start−up (VCTRL
pin voltage is brought at its higher value by the by
half of the 200−mA DRE current source which
charges the capacitors of the compensation network)
switching. When output power is decreasing, if a
threshold is reached (determined by sensing the CS pin
impedance during initial power up), a dead time based
on a number of valleys is added. The number of valleys
will increase, each time a dead time window (based on
V
CTRL
value) is entered. By construction, this counting
process will avoid valley hoping during the mains
voltage period. If the output power continues
th
decreasing and the 6 valley is reached, extra “analog”
dead time will be added based on a voltage ramp (see
Figure 4). On−time will be synchronized with a valley.
A timer will clamp the total switching period to not
exceed 36.5 ms (the switching frequency will never go
under about 27.4 kHz). The switching frequency
depends on output voltage, input voltage, and boost
inductor value, and increases as the load power
increases. Hysteresis and added to the VCTRL control
windows to avoid valley hopping during steady state
conditions. VCFF maximizes the efficiency at both
nominal and light load. Similarly to FCCrM
• Soft−OVP / Fast−OVP ( Over Voltage Protection)
There are cases (for example during an high−load to
low−load rapid transition) were the bulk capacitor
voltage goes up very rapidly above the voltage
regulation level triggering Over−Voltage protection.
When the bulk capacitor voltage V
reaches typically
bulk
105% of its nominal value, the Soft−OVP protection is
triggered, causing the duty−ratio to decrease gradually
down to zero. As a consequence, Vbulk decreases and
when Vbulk reaches the low level of Soft−OVP
threshold (typically 103% of nominal Vbulk) the
protection is released and the voltage regulation loop
takes−over .If Vbulk rises faster and reaches the
Fast−OVP threshold (typically 107% of nominal
Vbulk), the switching is instantaneously stop (DRV
signal is disabled). As a consequence, Vbulk decreases
and when the low level of Fast−OVP threshold is
reached (typically 103% of nominal Vbulk) the
protection is released and the voltage regulation loop
takes−over. Soft−OVP has only one level and can be
disabled dependent on product option. Three Fast_OVP
levels are available by product options : typically 107,
110 and 112% of nominal Vbulk. The 112% option is
well suited for applications using a low value bulk
capacitor were the two−times mains frequency Vbulk
controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is
reduced.
• Low Start−up Current: The start−up consumption of the
circuit is minimized to allow the use of high impedance
start−up resistors to precharge the V capacitor. Also,
CC
the minimum value of the UVLO hysteresis is 6 V to
avoid the need for large V capacitors and help
CC
shorten the start−up time without the need for excessive
dissipation in the start−up circuit. The [*C*] & [*D*]
version is preferred in applications where the circuit is
fed by an external power source (from an auxiliary
power supply or from a downstream converter). After
start−up, the high V maximum rating allows a large
CC
operating range from 10.5 V up to 27 V.
• Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): Since PFC stages exhibit low loop
bandwidth, abrupt changes in the load or input voltage
(e.g. at start−up) may cause excessive over or
www.onsemi.com
11
NCL2801
ripple voltage is high (in this case Soft−OVP is
valley number count up to 6 valleys (the number of
disabled)
valleys between end of inductor demagnetization and
power MOSFET turn−on determines the dead time
value). After counting is done, the power MOSFET
• Safety Protections: Permanently monitoring the input
and output voltages, the MOSFET current and the die
temperature to protect the system from possible
over−stress makes the PFC stage extremely robust and
reliable. In addition to the OVP protection, the
following methods of protection are provided :
− Maximum Current Limit: The circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low duty−cycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
th
turns on at drain voltage valley. When 6 valley is
reached and V
voltage stays under 0.77 V, an extra
CTRL
“analog” dead time is added based on a voltage ramp
(see Figure 4). The added analog dead time t is
ADT
based on 0.77 V minus V
value. t
will be equal
CTRL
ADT
to zero when (0.5 V−V ) = 0 V and will increase
CTRL
monotonically versus V
decreases while V
is
CTRL
CTRL
under the 0.77 V threshold corresponding to
. The analog dead time added tADT will
V
CTRL,th,56
equal typically 20 ms when VCTRL=0.5 V.
− When additional “analog” dead time is added, the
power MOSFET turn−on will, by default, be
synchronized with the falling edge of ZCD signal
(valley turn−on) and there will be possible, upon
request, of no valley synchronization for the on−time
− Thermal Shutdown: An internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150°C (typically). The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
start. The total dead−time (number of valleys and extra
dead−time) will not exceed 36.5 ms (A timer will be
clamping the dead time).
• Output Stage Totem Pole: NCL2801 incorporates a −0.5
A / +0.8 A gate driver to efficiently drive most TO220
or TO247 power MOSFETs.
− When the output power increases, the extra ”analog”
dead−time plus number of valleys dead time will
decrease ,according in which VCTRL pin voltage
NCL2801 Operation Modes
st
window VCTRL pin voltage is, down to 1 valley
As mentioned, NCL2801 PFC controller implements a
Valley Count Frequency Fold−back (VCFF) where:
− The circuit operates in classical Critical conduction
Mode (CrM) when output power is high and VCTRL
switching which is the CrM mode. The VCTRL pin
voltage window in which VCTRL pin voltage is will be
detected with comparators having an hysteresis to avoid
valley hopping due to VCTRL pin voltage ripple.
− It will be the responsibility of the application designer
not to allow a VCTRL pin voltage ripple (at 2 times the
mains frequency) greater than the hysteresis of VCTRL
windows.
pin voltage greater than a threshold (V
for
CTRL,th,12
for V
CTRL,th,21 CTRL
V
CTRL
decreasing and V
increasing) which value is determined by the value the
resistance R placed between CS pin and top of
Rsense which bottom is connected to GND (R
CS
sense
− Valley hopping can lead to audible noise. The
NCL2801 avoids this activity by locking the operating
valley before turning on the MOSFET during steady
state operation.
being negligible versus R , it is the R value which
CS
CS
is sensed). R value is sensed just before the startup
CS
phase (see Table 6).
− When the output power decreases the NCL2801
reduces the operating frequency by means of increasing
www.onsemi.com
12
NCL2801
Counting 1 valley
Counting 3 valleys
High Load Current
One valley (CrM)
Low Load Current
More valleys (DCM)
Lower Load Current
More valleys (DCM)
Counting 6 valleys
tADT
Extremely Low Load Current
More valleys (DCM)
Plus analog dead time
Counting 6 valleys + tADT
Figure 3. Valley Switching Operation in CrM and DCM Modes Seen Through Power MOSFET
Drain Voltage
As illustrated in Figure 3, under high load conditions, the
boost stage is operating in CrM (only one valley is counted
before turning on the power MOSFET). The second
example shows a DCM state of operation where 3 valleys
have been counted before turning on the power MOSFET.
The third example shows a DCM state with lower output
power than the previous one where 5 valleys have been
counted before turning on the power MOSFET.The fourth
means of counting the falling edges of the ZCD signal until
the counter reaches the number of valleys set by the window
in which the VCTRL pin voltage is (see Figure 4). The 3−bit
counter allows to work “Valley synchronized” up to 6
th
valleys. When the 6 valley is reached, and V
is lower
CTRL
than 0.770 V (V
= 0.770 V whatever frequency
CTRL,th,56
foldback threshold setting), an additional analog dead time
will be added to the 6 valleys dead time and there will be
valley synchronization turn−on of the power MOSFET
(ADT_nosync = 0 by default) based on falling edge of ZCD
signal. The total dead−time (number of valleys and extra
analog dead−time) will not exceed 36.5 ms. As a result of this
timer the minimum switching frequency will not go under
27.4 kHz.
th
example shows how additional dead time is added after 6
valley.
Valley Count Frequency Foldback (VCFF)
The turn−on of the power MOSFET is synchronized with
the valley of the power MOSFET drain voltage signal by the
www.onsemi.com
13
NCL2801
DIGITAL
COMPARATOR
CMPOUT
VCTRL
ZCD
UP
COUNTER
RST
CLK
DRV
Rz
Cz
Cp
VCTRL
CS
RCS
RCS
stored
RCS – VCTRL,th,ij
Lookup−Table
−us TIMER
36.5
RST
Rsense
DRV
VCTRL,max
VCTRL,th,12
VCTRL,th,21
VCTRL,th,23
VCTRL,th,32
VCTRL,th,34
VCTRL,th,43
VCTRL,th,45
VCTRL,th,54
VCTRL,th,56
VCTRL,th,65
0
ADT
ADT_nosync
IADT
V2I
1/RADT
CMPOUT
D
Q
R
VADT
CADT
DRV
ZCDbar
ADT
Figure 4. Valley Count Turn−on Block Diagram
This Valley Counting (VC) method avoids “valley
hoping” during the half period of mains voltage which is on
other designs, the cause of undesired mains current ringing
glitches due to the excitation of the input EMI filter by a dead
time discontinuity. The NCL2801 circuitry acts so that the
PFC controller transitions from the n valley to (n+1) valley
or from the n valley to (n−1) and stays on this valley number
is long as the VCTRL pin voltage stays in a the voltage
window corresponding to this valley number. If no
demagnetization is sensed the power MOSFET will be
turned−on after a watchdog timing of 200−ms.
The system relies on the counting of ZCD pulses to
determine dead−time periods. Should the ZCD pulses
diminish in voltage so that the event timing can’t be used, an
internal copy of the last reliable first−to−second falling edge
timing is substituted for the natural ZCD ring. The substitute
timing for a second falling edge is allowed 1us beyond the
recorded value before being asserted. The substitute timing
for the third falling edge and afterward is allowed 250 ns
beyond the recorded value before a ZCD pulse is asserted.
The NCL2801 PFC controller, depending on the
application power output which is correlated with the
www.onsemi.com
14
NCL2801
VCTRL pin voltage level, starts adding a dead−time t . The
output power in order to ensure that the instantaneous mains
current remains in phase with the mains instantaneous
voltage (creating a unity PF).
DT
system adjusts the on−time t (by means of peak current
ON
control) versus t (see Figure 5) and consequently the
DT
tON
tDEMAG
Ipeak,max
Iind
0
Tsw
CLK
tDT
DT
DRV
time
Figure 5. NCL2801 Clock, Dead Time and tON waveforms
When the output power is at the maximum available for
a given application and the inductor peak current limitation
the maximum power is given just under to the maximum
VCTRL pin voltage V
which is 4.5 V. Zero ouput
CTRL
is not triggering, VCTRL pin voltage (V
), is above the
CTRL
power will be supplied for V =0.5 V
CTRL
frequency foldback threshold (V ) making the
CTRL,th,21
For adjusting at which V
value the transition from
CTRL
controller to work in CrM mode. When output power
decreases V will go under the frequency foldback
CrM to DCM mode will happen, the resistance value
between CS pin and GND will be sensed before start−up and
its value stored digitally (see Figure 6). The sensed
CTRL
threshold (V ) and DCM mode will be forced by
CTRL,th,12
adding dead time as explained before.
resistance is equal to R plus R
value is much lower than RCS, it is the RCS value which will
be sensed.
This resistor sense will be done after VCC,on level is
reached and just before the controller starts switching in
order to avoid any noise perturbation the sensing (see Figure
, but because Rsense
CS
sense
Adding dead−time will naturally decrease the switching
frequency, hence the FF (standing for Frequency Foldback)
which is part of the name VCFF.
The switching frequency in DCM mode is given by the
following equation..
1
6). The I
1−mA (+/− 4%) current source, active when
FSW,DCM
+
RCS
(eq. 1)
t
DT ) tON ) tDEMAG
RCS flag is high will generate a voltage drop through R
CS
The value of the external resistor placed between CS pin
(+/−1%) resistor and this voltage drop will be compared to
internal voltage references to identify which is the R
resistor value and set the internal frequency foldback
CS
and Rsense will determine the value of the VCTRL pin
voltage frequency foldback threshold.
settings.
CrM−DCM Threshold
For a given application, R
and R
divider ratio of
sense
mult
the resistors bridge connected to MULT pin are set such as
www.onsemi.com
15
NCL2801
Controller starts
switching
VCC_CMP_new
RCS
IRCS
RCS
(+/−1%)
VCC_CMP
Open_RCS
CS
RCS
VRCS,REF,5
VRCS,REF,4
VRCS,REF,3
VRCS,REF,2
VRCS,REF,1
Q
D
ó
RCS
Lookup−Table
VCTRL ,th,12
CLK
Qb
RCS value
is stored
here
RCS
Figure 6. RCS Sensing Method And Schematic
Table 7.
R
(W)
V
(V)
CS
CTRL,th,12
1000
620
330
150
2.19
1.83
1.48
1.12
gives the digital code used in Figure 6 corresponding to
triggered and latched disabling the startup of the controller,
the fault will be released if VCC pin voltage falls unders
the R resistor value which in turn will be used to set the
CS
CrM to DCM threshold (when output power is decreasing).
There will be a different DCM to CrM threshold than CrM
to DCM making an hysteresis to avoid valley hopping (see
Table 7 and Figure 4).
V
.
CC,rst
DCMn−DCMn+1 and DCMn+1−DCMn Transition
Hysteresis
As explained before, DCM mode is driven by the number
of valleys counted before the power MOSFET turns on.
As shown in Figure 7, the forced number of valleys,
shown in the Y−axis, depends on 5 VCTRL pin voltage
windows,
the X−Axis representing the VCTRL pin voltage. In order
to avoid valley hopping due to VCTRL pin voltage ripple,
we have included an hysteresis. We can clearly see in Figure
During this R identification phase which main purpose
CS
is to setting the the frequency foldback thresholds and
number of valley for dead time, if it happen that V voltage
CS
is greater than V
an OPEN CS pin fault will be
RCS,REF,5
triggered and latched disabling the startup of the controller,
the fault will be released if VCC pin voltage falls unders
V
CC,rst
. On the other hand if it happen that V voltage is
CS
lower than V
a SHORT CS pin fault will be
RCS,REF,1
www.onsemi.com
16
NCL2801
7 that the V
hysteresis voltage is defined by: V
results from output power decrease. We can also mention
looking at Figure 7 and the specified frequency foldback
thresholds of Table 7 that V which is the V
CTRL
−V
CTRL,hyst
and more generally by V
CTRL,th,34 CTRL,hyst
= V
CTRL,th43
= V
− V
. If VCTRL pin peak−to−peak
CTRL,th,ji
CTRL,th,ij
CTRL,th,56
CTRL
ripple voltage stays under V
hopping.
there will be no valley
threshold at which we force counting 6 valleys, has always
the same value. This threshold is also called V
CTRL,hyst
CTRL,ADT
V
can be calculated for each frequency foldback
because when VCTRL pin voltage falls under this threshold,
an analog dead−time starts to be added to the dead−time
determined by counting 6 valleys. The lower VCTRL pin
CTRL,hyst
option determined by R
value from the thresholds
CS
specified in Table 7. While the hysteresis between two
adjacent valley numbers is constant for one frequency
foldback option, it decreases for options having a lower
CrM to DCM V
problem as the two times mains frequency ripple also
decreases when VCTRL pin voltage decreases which
voltage goes under V
threshold, the more analog
CTRL,ADT
dead time is added. An example on how the analog dead time
can be added is shown in the circuit of Figure 4 and the
correspond power MOSFET drain voltage is shown in
Figure 3.
threshold. This should not be a
CTRL
www.onsemi.com
17
NCL2801
Forced Valley #
VCTRL,th,65
6
@RCS = 1000 W
VCTRL,th,54
5
4
VCTRL,th,56
VCTRL,th,43
VCTRL,hyst
VCTRL,th,45
VCTRL,th,32
3
2
1
VCTRL,th,34
VCTRL,th,21
VCTRL,th,23
VCTRL,th,12
VCTRL (V)
2.5
3.5
4.0
2.0
3.0
4.5
0.5
1.0
1.5
VCTRL ,ADT
Forced Valley #
Entering Forced Valley #
Exiting Forced Valley #
VCTRL,th,65
6
VCTRL ,th,54
5
4
@RCS = 330 W
VCTRL,th,56
VCTRL,th,45
VCTRL ,th,43
VCTRL,hyst
VCTRL,th,32
3
2
1
VCTRL,th,34
VCTRL,th,23
VCTRL,th,12
VCTRL ,th,21
VCTRL (V)
2.5
3.5
4.0
2.0
3.0
4.5
0.5
1.0
1.5
Figure 7. Forced Valley Number versus VCTRL Pin Voltage For a Two Different RCS
Values of the Mandatory List {150 W, 330 W, 620 W, 1000 W}
www.onsemi.com
18
NCL2801
NCL2801 On−time Modulation and VTON Processing
Circuit
Let’s analyze the ac line current absorbed by the PFC
boost stage. The initial inductor current at the beginning of
each switching cycle is always zero. The coil current ramps
One can show that the ac line current is given by:
t1(t1 ) t2)
(eq. 2)
(eq. 3)
Iin + Vin
2TL
Where
T + t1 ) t2 ) t3
up when the MOSFET is on. The slope is (V /L) where L is
in
the coil inductance. At the end of the on−time (t ), the
inductor starts to demagnetize. The inductor current ramps
1
is the switching period and V is the ac line rectified
in
voltage.
In light of this equation, we immediately note that I is
down until it reaches zero. The duration of this phase is (t ).
2
in
In some cases, the system enters then the dead−time (t ) that
3
proportional to V if [t (t +t )/T] is a constant.
in
1.
1
2
lasts until the next clock is generated.
L1
D1
Vin
Iind
Vout
Vin
Cin
Cbulk
Q1
DRV
Rsense
time
Iind
t1
t2
t3
Ipeak,max
time
0
T
Figure 8. PFC boost converter and Inductor Current in DCM
NCL2801 operates in current control mode. As portrayed
of the NCL2801 because at steady state, what results from
by Figure 8 & Figure 10, the MOSFET on−time t results
a current control is a constant on−time.
1
from a current control mode circuitry which is using a
Current Control Mode & THD Enhancer
In order for the mains current to have very good THD, the
Current Control Mode depicted in Figure 10 mode is
preferred.
To improve the mains current THD, an offset voltage is
added to the multiplier output (see Figure 9).
dedicated circuitry monitoring V
and dead−time t
ctrl
3
ensuring [t (t +t )/T] is constant and as a result making I
1.
1
2
in
proportional to V (PF=1)
in
On−time t , also called t , has a high value clamp called
1
ON
t
, generated by an internal circuitry. This 30−ms
ON,max
clamp value is given for maximum VCTRL pin voltage
(V =4.5 V) but reduces down to 5 ms when VCTRL pin
The added offset is equal to Koffset.Vton
CTRL
The role of this offset is to add on−time and this added
on−time will be very beneficial close to line zero crossing
where, without this offset, the inductor peak current is low
and comparable to the inductor negative peak current
resulting to zero line current. Adding this offset greatly
reduces the time width during which the line current is equal
to zero (line voltage cross−over distortion) and by doing
improve the line current THD.
A traditional scheme, where the inductor current during
on−time multiplied by Rsense is compared to a scaled down
rectified mains voltage Vin multiplied by Vton is used. What
voltage reaches 0.5 V which is its minimum value.
The input current is then proportional to the input voltage.
Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CrM
case. This condition is just a particular case of this
functioning where (t3=0), which leads to (t1+t2=T) and
(Vton=Vregul). That is why the NCL2801 automatically
adapts to the conditions and transitions from DCM to
n
DCM
and DCM
to DCM without power factor
n+1 n
n+1
degradation and without discontinuity in the power delivery.
This analysis while carried−out for constant on−time
architecture is also valid for the current control architecture
may sound strange is the Vton, but Vton is equal to Vregul
when in CrM.
www.onsemi.com
19
NCL2801
Iind
Rsense
RCS
PWM
Vin
Vipeak
End of on−time
when high
Vm
Rmult1
Rmult2
Vton
Vton
Figure 9. Simplified Current Control Circuit (Max On−Time and Blanking Not Shown)
1.5V
4.0V
In DCM mode, the Vton input of the multiplier is modified
thanks to the Vton processing block in order to maintain the
mains current proportional to the mains voltage.
It can be demonstrated that the maximum peak inductor
current is given by the following equation
Vregul + (VVCTRL * 0.5V)
(eq. 4)
The range of Vregul is equal to 1.5 V and Vregul operates
between 0 V and 1.5 V.
The range of V
is equal to 4.0 V and V
operates
CTRL
CTRL
between 0.5 V and 4.5 V.
Ǹ
ǒ
Ǔ
KmKmult 2 Vmains,rms ) Koffset @ VTON
Vipeak,max
(eq. 5)
Iind,peak,max
+
+
+
Rsense
Rsense
From I
assuming we are in CrM we can get the
ind,peak,max,
rms line current by :
Ǹ
ǒ
Ǔ
KmKmult 2 Vmains,rms ) Koffset @ VTON
Vind,peak,max
(eq. 6)
(eq. 7)
Imains,rms
+
Ǹ
Ǹ
2 2
2 2 Rsense
Then,
(KmKmult 2 V2
) KoffsetVmains,rms) @ VTON
Ǹ
mains,rms
Pmains,rms
+
Ǹ
2 2 Rsense
To better see the effect of K
on P
the previous
offset
mains,rms
equation can be re−written as follows
KmKmultV2
VTON
KoffsetVmains,rmsVTON
mains,rms
(eq. 8)
Pmains,rms
+
)
Ǹ
2Rsense
2 2 Rsense
The multiplier gain, for product options having no line
level detection ([**B]&[**D] has a value which does not
In both previous equations Kmult is the multiplier gain
and Km is given by the following:
vary versus V
value.
mains
Rmult2
For product options having line level detection
([**A]&[**C], the multiplier gain has an High Line value
Km
+
(eq. 9)
R
mult1 ) Rmult2
It is important to mention that in CrM mode so particularly
at max output power, V =V
(K ) and a Low Line value (K ). These two line
mult,HL mult,LL
.
regul
TON
www.onsemi.com
20
NCL2801
level dependent multiplier gain values act as a two−level line
feed forward.
options. For the product options where the DRE is enabled,
an internal comparator monitors the FB pin voltage (V
)
FB
and when V is lower than 95.5% of its nominal value, it
FB
NCL2801 Maximum on−time
In order to avoid the on−time to go too high close to line
connects the 220−mA current source to VCTRL pin in order
to speed−up the charge of the compensation network.
Effectively this appears as a 10x increase in the loop gain.
The circuit also detects overshoot using the Soft OVP
circuitry and immediately reduces the power delivery when
the output voltage exceeds a value which is product option
dependent.
The error Operational Transconductance Amplifier OTA
and the OVP and DRE comparators share the same input
information. Based on the typical value of their parameters
and if Vbulk,nom is the bulk nominal voltage value (e.g., 400
V), we can deduce:
voltage zero crossing, a V
dependent maximum on
CTRL
time circuitry has been added. The on−time limiting values
are linearly depending on VCTRL pin voltage as follows:
30−ms @V
= 4.5 V and 5−ms @V
= 0.55 V
CTRL
CTRL
NCL2801 Regulation Block and Output Voltage Control
A trans−conductance error amplifier (OTA) with access to
its inverting input (FB pin) and to its output pin (VCTRL
pin) is provided. It features a typical trans−conductance gain
of 200 mS and a maximum current capability of +/−20 mA.
The output voltage of the PFC stage is typically scaled down
by a resistors divider and monitored by the OTA inverting
input (pin FB). Bias current is minimized (less than 500 nA)
to allow the use of a high impedance feed−back network.
However, it is high enough so that the pin remains in low
state if the pin is not connected.
The output of the error amplifier is brought to pin VCTRL
for external loop compensation. Typically a type−2 network
is applied between pin VCTRL and ground, to set the
regulation bandwidth below about 20 Hz and to provide a
decent phase boost.
• Output Regulation Level:
• Output DRE Level:
95.5%.Vbulk,nom
Vbulk,nom
Vbulk,dre
Vbulk,sovp
Vbulk,fovp
=
• Output Soft OVP Level:
=
=
X%.Vbulk,nom
• Output Fast OVP level:
Y%.Vbulk,nom
NOTE: Note: X% and Y% are product option dependent
Current Sense and Current Control
The swing of the error amplifier output is limited within
an operating range:
− It is forced above a voltage drop (V ) by a dedicated
The power MOSFET current I
is sensed during the
ind
on−time phase by the resistor Rsense inserted between the
MOSFET source and ground (see Figure 10). The voltage
Rsense.Iind after a proper leading edge blanking (tLEB,OCP
F
circuitry.
− It is clamped not to exceed 4.0 V + the same V voltage
F
drop.
and tLEB,OVS) starting from the power MOSFET rising
edge drive signal (DRV) is compared to internal
over−current protection (OCP) and overstress protection
(OVS) internal references (namely VCS(th) and
VCS,OVS(th)) which when triggered ends the on−time for
OCP or stops the switching during 800 us for OVS. The
voltage Rsense.Iind is also low−pass filtered (R=20 kW,
C=20 pF see Figure 10), leading edge blanked and
compared to the multiplier output voltage to generate the
end of the on−time which is typical of a current mode control
(see Figure 10).
In order to improve the THD of the mains current, a Vton
dependent offset at the output of the multiplier and a
TONMAX processing block have been added (see Figure
10).
Vton is one of the inputs of the multiplier for helping
improve THD in DCM mode (Frequency Foldback).
Vton is equal to Vregul which is proportional to the
VCTRL pin voltage when in CrM mode.
The V value is 0.5 V typically.
The regulated output voltage Vbulk uses an internal
reference voltage V
The regulated Vbulk voltage (its average value in case of
important ripple) will be equal to V multiplied by the
F
= 2.5 V.
REF
REF
dividing factor given by the resistor bridge placed between
and FB pin, resulting for example in V = 395 V.
V
bulk
bulk
Given the low bandwidth of the regulation loop, abrupt
variations of the load, may result in excessive over or
under−shoot. Over−shoot is limited by the Over−Voltage
Protection (OVP) connected to FB pin (Feedback).
Optionally, NCL2801 embeds a “Dynamic Response
Enhancer” circuitry (DRE) that limits under−shoots. The
DRE works during startup phase by injecting current into the
VCTRL pin which rises VCTRL pin voltage and allows
more current to charge the bulk capacitor. After the startup
phase, when internal PFCOK flag goes high, the DRE is
disabled on some options, but is enabled in other product
www.onsemi.com
21
NCL2801
OCP
OVS
RCS – VCRTL,th,ij,Rcs
Lookup−Table
Iind
20kOhms
VCTRL,th,12,Rcs controls
the Frequency Foldback
threshold
BLK
Rsense
RCS
10pF
PWM
Vin
Vm
End of on−time
when high
Rmult1
Rmult2
Vton
Vton
Koffset.Vton
Vregul
Figure 10. PWM Circuit Showing Current Control Mode With a New MULT Pin
Zero Current Detection (ZCD)
The ZCD pin features a classical and robust ZCD
detection based on sensing the auxiliary winding voltage as
shown in Figure 11. The ZCD pin voltage is clamped high
When no signal is received that triggers the ZCD
comparator to indicate the end of inductor demagnetization,
an internal 200−ms watchdog timer initiates the next drive
pulse.
at VCC plus a diode V (0.7 V) and clamped low at minus
f
a diode Vf (−0.7 V) and then compared to ZCD thresholds
voltages VZCD,th,H and VZCD,th,L (see Table 6).
www.onsemi.com
22
NCL2801
VCC
Vaux
RZCD
ZCD
ZCD
VZCD,th,H
VZCD,th,L
Figure 11. Zero Current Detection (ZCD) Circuitry
Brown−Out Detection) – (Options [**A], [**B])
Thanks to the line voltage scaled−down by K and
The line voltage (V
reducing on−time until it stops switching which can be
called brown−out and is given by:
) at which the controller starts
line,BO,L
m
rectified available on MULT−pin (V ) a Brown−Out feature
m
is available on options [**A], [**B].
VBOL
(eq. 13)
Vline,BO,L + Vline,Brown*in
+
Vm(t) + Km @ Vin(t)
(eq. 10)
(eq. 11)
Ǹ
Km
2
With
It has to be reminded that while changing Km by changing
the Rmult resistors dividing ratio can help to shift up or
down the line brown−in and brown−out levels, Km
determines also the internal gain of the controller, together
with Rsense and Kmult (multiplier gain), so care must be
Rmult2
Km
+
R
mult1 ) Rmult2
The V
voltage is sensed and when eventually V
MULT
MULT
falls under Brown−out internal reference voltage V
50 ms, BONOK flag will be set to 1. After BONOK flag is
set to 1, drive is not disabled, instead, a 30−mA current
for
BOL
taken at adjusting R
accordingly to the K adjustment.
sense
m
source (I
reduce V
) is applied to VCTRL pin to gradually
. As a result, the circuit only stops pulsing
VCTRL(BO)
Line Level Detection and 2−Level Line Feed−Forward–
(Options [**A], [**C])
CTRL
when the STATICOVP function is activated. At that
moment, the circuit stops switching. This method limits any
risk of false triggering.
The input of the PFC stage has some impedance that leads
to some sag of the input voltage when the input current is
large. If the PFC stage suddenly stops while a high current
is drawn from the mains, the abrupt decay of the current may
make the input voltage rise and the circuit detect a correct
For product options [**A], [**C], the line level detection
(High Line or Low Line) feature together with a two−level
line feed forward is activated and operates as described here
after.
MULT pin voltage V
is used to sense the line voltage
MULT
and apply a two−level line feed−forward.
The V voltage is compared to a V internal voltage
MULT
HL
reference. If V
exceeds V
,
the circuit detects
MULT
HL
line level. Instead, the gradual decrease of V
avoids a
a High−Line state (LLINE flag is set to 0) and the multiplier
CTRL
line current discontinuity and limits the risk of false
triggering.
gain is set to value corresponding to High Line which is
Kmult,HL. Once this occurs, if V
remains below V
LL
MULT
The line voltage (V
) at which the controller starts
line,BO,H
for 25 ms, the circuit detects a Low−Line state (VHL(hyst)
hysteresis) and the multiplier gain is set to Kmult,LL
At startup, the circuit is in High−Line state (LLINE flag
is set to 0) and then V will be used to determine the
switching which can be called brown−in and is given by the
following equation:
.
VBOH
MULT
Vline,BO,H + Vline,Brown*in
+
(eq. 12)
High−Line or Low−Line state.
Ǹ
Km
2
www.onsemi.com
23
NCL2801
The line range detection circuit allows more optimal loop
The High Line and Low Line thresholds, respectively
Vline,HL and Vline,LL are given by the following equations:
gain control for universal (wide input mains) applications by
adjusting the multiplier gain value versus line voltage status
(High Line or Low Line).
For the options [**B], [**D], no line feedforward action
is taken based on the line level and the multiplier gain
remains set at Kmult whatevever line level.
VHL
Vline,HL,rms
+
(eq. 14)
Ǹ
Km
2
VLL
Vline,LL,rms
+
(eq. 15)
Ǹ
Km
2
Vin
VREF,LLINE
VHL if LLINE=1
VLL otherwise
VREF,BONOK
VBOH if BONOK=1
VBOL otherwise
Figure 12. Input Line Sense and Brown−out Monitoring
Thermal Shut−Down (TSD)
More specifically, when the circuit is in OFF state:
An internal circuitry sensing the silicon temperature
disables the circuit gate drive and keeps the power switch off
when the junction temperature exceeds 150_C. The output
stage is then enabled once the temperature drops below
about 100_C (50_C hysteresis).
− The drive output is kept low
− All the blocks are off except:
♦ The UVLO circuitry that keeps monitoring the
V
CC
voltage and controlling the start−up current
source accordingly.
The temperature shutdown remains active as long as the
♦ The TSD (thermal shutdown)
circuit is not reset, that is, as long as V is higher than a reset
− V is grounded so that when the fault is removed, the
CC
ctrl
threshold.
device starts−up under the soft start mode.
− The internal “PFCOK” signal is grounded.
Output Drive Section
− The output of the “V processing block” is grounded
ton
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. Its high current capability
(−500 mA/+800 mA) allows it to effectively drive high gate
charge power MOSFET.
Failure detection
When manufacturing a power supply, elements can be
accidently shorted or improperly soldered. Such failures can
also happen to occur later on because of the components
fatigue or excessive stress, soldering defaults or external
interactions. In particular, adjacent pins of controllers can be
shorted; a pin can be grounded or badly connected. Such
open/short situations are generally required not to cause fire,
smoke or hazardous conditions. NCL2801 integrate
functions that ease meeting this requirement. Among them,
we can list:
OFF Mode
As previously mentioned, the circuit turns off when one
of the following faults is detected:
• Incorrect feeding of the circuit (“UVLO” high when
V
<V
, V
).
CC CC(off) CC(off)
• Excessive die temperature detected by the thermal
shutdown
♦ Fault of the GND connection
If the GND pin is not connected, internal circuitry
detects it and if such a fault is detected for 200 ms,
the circuit stops operating.
• STATICOVP (see Figure 2)
Generally speaking, the circuit turns off when the
conditions are not proper for desired operation. In this mode,
the controller stops operating. The major part of the circuit
sleeps and its consumption is minimized.
♦ Fault of the FB connection
If the FB pin is left open because for example of bad
www.onsemi.com
24
NCL2801
soldering, an internal pull down current source pulls
♦ Boost or bypass diode short
down the FB voltage under the UVP threshold and
the controller is turned off.
♦ Detection the ZCD pin improper connection
If the ZCD pin is floating or shorted to GND it is
detected by internal circuitry and the circuit stops
operating.
The controller addresses the short situations of the boost
and bypass diodes (a bypass diode is generally placed
between the input and output high−voltage rails to divert this
inrush current). Practically, the overstress protection is
implemented to detect such conditions and forces a low
duty−cycle operation until the fault is gone.
Table 8. NCL2801 ORDERING TABLE
DRE
(after
start)
DRE
(during
start)
Line
Range
Detect
Soft
OVP
Fast
OVP (%)
V
Start
(V)
Brown
Out
CC
Ordering Part No.
NCL2801CDADR2G
NCL2801CDBDR2G
NCL2801CFADR2G
Package Shipping
X
X
X
107
107
107
12.5
12.5
10.5
X
X
X
X
X
X
X
X
X
X
SOIC−8
2500/Tape
& Reel
(Pb−Free)
X
www.onsemi.com
25
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
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DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
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