NCN5192 [ONSEMI]
HART Modem; HART调制解调器
| 型号： | NCN5192 |
| 厂家： | 
ONSEMI |
| 描述： | HART Modem |
| 文件： | 总13页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCN5192
HART Modem
Description
The NCN5192 is a single−chip, CMOS modem for use in highway
addressable remote transducer (HART) field instruments and masters.
The modem and a few external passive components provide all of the
functions needed to satisfy HART physical layer requirements
including modulation, demodulation, receive filtering, carrier detect,
and transmit−signal shaping. In addition, the NCN5192 also has an
integrated DAC for low-BOM current loop slave transmitter
implementation.
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MARKING
DIAGRAM
The NCN5192 uses phase continuous frequency shift keying (FSK)
at 1200 bits per second. To conserve power the receive circuits are
disabled during transmit operations and vice versa. This provides the
half−duplex operation used in HART communications.
1
NCN
5192
AWLYYWW
G
32
1
QFN32
CASE 488AM
Features
• Single−chip, Half−duplex 1200 Bits per Second FSK Modem
• Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz
• 3.0 V − 5.5 V Power Supply
NCN5192 = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• Transmit−signal Wave Shaping
• Receive Band−pass Filter
• Low Power: Optimal for Intrinsically Safe Applications
• Compatible with 3.3 V or 5 V Microcontroller
• Internal Oscillator Requires 460.8 kHz, 920 kHz or 1.8 MHz Crystal
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
or Ceramic Resonator
• SPI Communication
• Integrated 16 bit Sigma-Delta DAC
• Meets HART Physical Layer Requirements
• Industrial Temperature Range of −40°C to +85°C
• Available in 32−pin NQFP Package
• These are Pb−Free Devices
Applications
• HART Multiplexers
• HART Modem Interfaces
• 4 − 20 mA Loop Powered Transmitters
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011 − Rev. 2
NCN5192/D
NCN5192
BLOCK DIAGRAM
VDD
VDDA
RxAFI
RxAF
RxA
Demodulator
Logic
RxD
FSK_IN
RxD_ENH
Rx Comp
Rx HP Filter
AREF
Carrier Detect
Counter
CD
CDREF
Carrier Comp
DEMODULATOR
Numeric
Controlled
Oscillator
TxA
Sine
Shaper
TxD
RTS
FSK_OUT
MODULATOR
DAC
NCN5192
JUMP
DAC
CS
DCLK
DATA
SPI
DACREF
VPOR
KICK
RESET
CLK1
CLK2
Crystal
Oscillator
POR
BIAS
KVDE 201104 07.1
CBIAS VSS VSSA
XOUT XIN
Figure 1. Block Diagram NCN5192
ELECTRICAL SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)
Symbol Parameter
Min
−40
−55
−0.3
−0.3
Max
+85
+150
6.0
Units
°C
°C
V
T
Ambient Temperature
Storage Temperature
Supply Voltage
A
T
S
V
DD
V
IN
, V
OUT
DC Input, Output
V + 0.3
DD
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. CMOS devices are damaged by high−energy electrostatic discharge. Devices must be stored in conductive foam or with all pins shunted.
Precautions should be taken to avoid application of voltages higher than the maximum rating. Stresses above absolute maximum ratings
may result in damage to the device.
2. Remove power before insertion or removal of this device.
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NCN5192
Table 2. DC CHARACTERISTICS (V = 3.0 V to 5.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Symbol
Parameter
V
DD
Min
Typ
Max
Units
V
DC Supply Voltage
Input Voltage, Low
Input Voltage, High
3.0
5.5
V
V
V
V
V
DD
V
3.0 – 5.5 V
3.0 – 5.5 V
3.0 – 5.5 V
3.0 – 5.5 V
0.3 * V
IL
IH
DD
V
0.7 * V
DD
V
Output Voltage, Low (I = 0.67 mA)
OL
0.4
OL
OH
V
Output Voltage, High (I = −0.67 mA)
2.4
OH
C
Input Capacitance of:
Analog Inputs
RxA
IN
2.9
25
3.5
pF
pF
pF
Digital Inputs
I /I
Input Leakage Current
500
10
nA
mA
mA
IL IH
I
Output Leakage Current
Total Power Supply Current
Static Analog Supply Current
OLL
I
175
350
600
DD
I
3.3 V
5.0 V
150
150
330
370
mA
mA
DDA
I
Static Digital Current
Dynamic Digital Current
Analog Reference
0
30
200
2.6
mA
mA
DDQ
I
5.0 V
25
1.2
DDD
A
3.3 V
5.0 V
1.235
2.5
V
V
REF
CD
Carrier Detect Reference (IAREF – 0.08 V)
3.3 V
5.0 V
1.15
2.42
V
REF
(Note 3)
C
Comparator Bias Current
(RBIAS = 500 kW, IAREF = 1.235 V)
2.5
mA
BIAS
3. The HART specification requires carrier detect (CD) to be active between 80 and 120 mVp−p. Setting CDREF at AREF − 0.08 VDC will set
the carrier detect to a nominal 100 mVp−p.
Table 3. AC CHARACTERISTICS (V = 3.0 V to 5.5 V, V = 0 V, T = −40°C to +85°C) (Note 4)
DD
SS
A
Pin Name
Description
Min
Typ
Max
Units
RxA
Receive analog input
Leakage current
Frequency – mark (logic 1)
Frequency – space (logic 0)
150
1210
2220
nA
Hz
Hz
1190
2180
1200
2200
RxAF
Output of the high−pass filter
Slew rate
Gain bandwidth (GBW)
Voltage range
0.025
V/ms
kHz
V/ms
150
0.15
V
DD
– 0.15
RxAFI
TxA
Carrier detect and receive filter input
Leakage current
500
nA
Modulator output
Frequency – mark (logic 1)
Frequency – space (logic 0)
Amplitude (IAREF 1.235 V)
Slew Rate − mark (logic 1)
Slew Rate − space (logic 0)
Loading (IAREF = 1.235 V)
1196.9
2194.3
500
1860
3300
Hz
Hz
mV
V/s
V/s
kW
30
20
20
RxD
CD
Receive digital output
Rise/fall time
ns
Carrier detect output
Rise/fall time
ns
4. The modulator output frequencies are proportional to the input clock frequency (460.8 kHz/920 kHz/1.8 MHz).
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NCN5192
Table 4. MODEM CHARACTERISTICS (V = 3.0 V to 5.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Parameter
Min
Typ
Max
Units
Demodulator jitter
Conditions
12
% of 1 bit
1. Input frequencies at 1200 Hz 10 Hz, 2200 Hz 20 Hz
2. Clock frequency of 460.8 kHz 0.1%
3. Input (RxA) asymmetry, 0
Table 5. CERAMIC RESONATOR AND CRYSTAL − External Clock Specifications
(V = 3.0 V to 5.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Parameter
Min
Typ
Max
Units
Resonator
Tolerance
Frequency
1.0
%
460.8
921.6
kHz
Crystal or Resonator, 920 kHz
Tolerance
Frequency
1.0
1.0
60
%
kHz
Crystal, 1.8 MHz
Tolerance
Frequency
%
MHz
1.843
50
External
Duty cycle
Amplitude
40
%
V
V
− V
OH
OL
Table 6. DAC CHARACTERISTICS (V = 3.0 V to 5.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Parameter
Min
Typ
Max
Units
Bandwidth
10
Hz
Accuracy
Return−to−Zero
Non Return−to−Zero
16
14
Bit
Bit
Maximum Output
Return−to−Zero
Non Return−to−Zero
AVDD/2
AVDD
V
V
Differential Non−linearity
Return−to−Zero
Non Return−to−Zero
0.5
0.25
0.75
0.75
LSB
LSB
Integral Non−linearity
Return−to−Zero
Non Return−to−Zero
2.0
1.0
4.0
2.0
LSB
LSB
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NCN5192
TYPICAL APPLICATION
POWER
3.0 to 5.5 V
VDD
RxAFI
RxAF
VDDA
RESET
RxA
HART IN
VPOR
KICK
RxD_ENH
VDDA
RxD
CD
AREF
NCN5192
TxD
LM285
RTS
CS
mC
CDREF
DATA
CLK
TxA
HART &
4 – 20 mA OUT
S
VDDA
DAC
CLK1
KVDE20110407.2
JUMP
DACREF
CLK2
XOUT
1. 8 MHz
XIN
CBIAS
VSS
VSSA
Figure 2. Application Diagram NCN5192
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NCN5192
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SCLK
DATA
JUMP
RESET
TxD
RTS
VDD
VSS
KICK
CS
NCN5192
VSSA
XIN
VSS
TxA
XOUT
AREF
Figure 3. Pin Out NCN5192 in 32-pin NQFP (top view)
Table 7. PIN OUT SUMMARY 32−PIN NQFP
Pin No.
1
Signal Name
SCLK
DATA
JUMP
KICK
Type
Input
Pin Description
SPI Serial Clock
SPI Serial Data
2
Input
3
Input
Sigma−Delta Modulator Alarm condition value
Watchdog kick
4
Input
5
CS
Input
SPI Serial Chip Select
6
VSS
Ground
Output
Input
Ground
7
TxA
Transmit Data Modulator output
Analog reference voltage
Carrier detect reference voltage
Comparator bias current
POR measurement point
Analog ground
8
AREF
CDREF
CBIAS
VPOR
VSSA
VDDA
RxA
9
Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Output
Input
Ground
Power
Input
Analog supply voltage
Receive Data Modulator input
Analog receive filter input
Analog receive comparator input
Crystal oscillator output
RxAF
RxAFI
XOUT
XIN
Output
Input
Output
Input
Crystal oscillator input
VSSA
VSS
Ground
Ground
Power
Input
Analog ground
Ground
VDD
Digital supply voltage
RTSB
TxD
Request to send
Input
Input transmit data, transmit HART data stream from microcontroller
Reset all digital logic when low
Received demodulated HART data to microcontroller
Carrier detect output
RESETB
RxD
Open Drain
Output
Output
Output
Input
CD
RxD_ENH
DACREF
DAC
not[CD] or RxD
Sigma−Delta Modulator Reference Voltage
Sigma−Delta Modulator Output
Digital supply voltage
Output
Power
Output
Output
VDD
CLK1
CLK2
Programmable Clock Output 1
Programmable Clock Output 2
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NCN5192
Pin Descriptions
Table 8. PIN DESCRIPTIONS
Symbol
Pin Name
Description
AREF
Analog reference voltage
Receiver Reference Voltage. Normally 1.23 V is selected (in combination with VDDA
= 3.3 V). See Table 2.
CDREF
Carrier detect reference voltage
Reset digital logic
Carrier Detect Reference voltage. The value should be 85 mV below AREF to set
the carrier detection to a nominal of 100 mV
.
p−p
RESETB
When at logic low (V ) this input holds all the digital logic in reset. During normal
SS
operation RESETB should be at V . RESETB should be held low for a minimum of
DD
10 nS after V = 2.5 V as shown in Figure NO TAG.
DD
RTSB
RxA
Request to send
Active−low input selects the operation of the modulator. TxA is enabled when this
signal is low. This signal must be held high during power−up.
Analog receive input
Receive Data Demodulator Input. Accepts a HART 1200 / 2200 Hz FSK modulated
square wave serial data stream as input.
RxAFI
TxD
Analog receive comparator input
Digital transmit input
Positive input of the carrier detect comparator and the receiver filter comparator.
Input to the modulator accepts digital data in NRZ form. When TxD is low, the modu-
lator output frequency is 2200 Hz. When TxD is high, the modulator output frequency
is 1200 Hz.
XIN
Oscillator input
Oscillator output
Input to the internal oscillator must be connected to a parallel mode ceramic resonator
when using the internal oscillator or grounded when using an external clock signal.
XOUT
Output from the internal oscillator must be connected to an external clock signal or to
a parallel mode ceramic resonator when using the internal oscillator.
CLK1
CLK2
Programmable Clock Output
Programmable Clock Output
Output signal derived from oscillator output, frequency division set by internal register.
Output signal derived from oscillator output, frequency division set by internal register.
As this signal is also used internally, the division should be set so that the output fre-
quency is 460.8 kHz
CBIAS
CD
Comparator bias current
Carrier detect output
Connection to the external bias resistor. R
BIAS
should be selected such that AREF /
BIAS
R
= 2.5 mA 5 %
Output goes high when a valid input is recognized on RxA. If the received signal is
greater than the threshold specified on CDREF for four cycles of the RxA signal, the
valid input is recognized.
RxAF
RxD
Analog receive filter output
Digital receive output
The output of the three pole high pass receive data filter
Signal outputs the digital receive data. When the received signal (RxA) is 1200 Hz,
RxD outputs logic high. When the received signal (RxA) is 2200 Hz, RxD outputs
logic low. The HART receive data stream is only active if Carrier Detect (CD) is high.
RxD_ENH Digital receive output, alternative
Not(OCD) or RXD
TxA
Analog transmit output
Transmit Data Modulator Output. A trapezoidal shaped waveform with a frequency of
1200 Hz or 2200 Hz corresponding to a data value of 1 or 0 respectively applied to
TxD. TxA is active when RTSB is low. TxA equals 0.5 V when RTSB is high.
SCLK
DATA
CS
SPI bus clock line
SPI bus data line
SPI bus chip select
Serial communication clock line
Serial communication data line. Frames transmitted can either be 8 bit or 16 bit long.
Serial communication chip select line. Pulled high by microcontroller while a frame is
transmitted.
JUMP
DAC Alarm value
DAC Reference
When a problem is detected, such as a clock failure or the watchdog going off, the
DAC will jump to the value set on this pin.
DACREF
This is the high value of the output and can be connected to any voltage between
AREF and VDD.
DAC
DAC Output
Output of a 16 bit Sigma−Delta Modulator
KICK
Watchdog Kick
Periodically a pulse should be provided to reset the watchdog. This can be configured
in internal registers for an internal 1.8kHz signal, or to an external signal provided to
this pin.
VPOR
POR Input
Input to the POR comparator. The voltage on this pin is compared with AREF. An
external resistor divider should divide the supply voltage to this pin.
VDD
Digital power
Analog supply voltage
Ground
Power for the digital modem circuitry
Power for the analog modem circuitry
Digital ground (and Analog ground in the case of PLCC package)
Analog ground
VDDA
VSS
VSSA
Analog ground
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NCN5192
Functional Description
The Numeric Controlled Oscillator (NCO) works in a
phase continuous mode preventing abrupt phase shifts when
switching between mark and space frequency. The control
signal “Request To Send” (RTSB) enables the NCO. When
RTSB is logic low the modulator is active and NCN5192 is
in transmit mode. When RTSB is logic high the modulator
is disabled and NCN5192 is in receive mode.
The NCN5192 is a single-chip modem for use in Highway
Addressable Remote Transducer (HART) field instruments
and masters. The modem IC contains a transmit data
modulator with signal shaper, carrier detect circuitry, an
analog receiver, demodulator circuitry and an oscillator, as
shown in the block diagram in Figure 1.
The modulator accepts digital data at its digital input TxD
and generates a trapezoidal shaped FSK modulated signal at
the analog output TxA. A digital “1” or mark is represented
with a frequency of 1200 Hz. A digital “0” or space is
represented with a frequency of 2200 Hz. The used bit rate
is 1200 baud.
The digital outputs of the NCO are shaped in the Wave
Shaper block to a trapezoidal signal. This circuit controls the
rising and falling edge to be inside the standard HART
waveshape limits. Figure 6 shows the transmit-signal forms
captured at TxA for mark and space frequency. The slew
rates are SR = 1860 V/s at the mark frequency and SR =
m
s
The demodulator receives the FSK signal at its analog
input, filters it with a band-pass filter and generates 2 digital
signals: RxD: Received Data and CD: Carrier Detect. At the
digital output RxD the original modulated signal is received.
CD outputs the Carrier Detect signal. It goes logic high if the
received signal is above 100 mVpp during 4 consecutive
carrier periods.
The oscillator provides the modem with a stable time base
using either a simple external resonator or an external clock
source.
3300 V/s at the space frequency. For AREF = 1.235 V, TxA
will have a voltage swing from approximately 0.25 to
0.75 V
.
DC
VTxA
“1” = Mark; fm =1.2 kHz
0.5 V
0.5 V
SRm = 1860 V/s
t (ms)
0
1
Detailed Description
2
VTxA
“0” = Space; fs =2.2 kHz
Modulator
The modulator accepts digital data in NRZ form at the
TxD input and generates the FSK modulated signal at the
TxA output.
0.5 V
0.5 V
t (ms)
SRs = 3300 V/s
1
0
2
Numeric
Controlled
Oscillator
TxA
KVDE20110408
Sine
Shaper
TxD
RTS
FSK_OUT
Figure 6. Modulator shaped output signal for Mark
and Space frequency at TxA pin.
MODULATOR
PC20101117.1
Demodulator
Figure 4. Modulator Block Diagram
A logic “1” or mark is represented by a frequency f
1200 Hz. A logic “0”or space is represented by a frequency
f = 2200 Hz.
The demodulator accepts a FSK signal at the RxA input
and reconstructs the original modulated signal at the RxD
output. Figure 7 illustrates the demodulation process.
=
m
s
FSK_IN
“1” = Mark
1.2 kHz
“0” = Space
2.2 kHz
RxD
LSB
MSB
D7
IDLE (mark)
IDLE (mark)
Stop
tBIT
Start
D0
“1”
D1
“0”
D2
“1”
D3
D4
“0”
D5
“1”
D6
“0”
Par
“0”
“0”
“0”
“1”
t
tBIT
8
data bits
PC20101013.4
Figure 7. Modulation Timing
This HART bit stream follows a standard 11-bit UART
frame with Start, Stop, 8 Data – and 1 Parity bit. The
communication speed is 1200 baud.
tBIT
=
ms
tBIT = 454 ms
833
KVDE20110407.5
Figure 5. Modulation Timing
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NCN5192
Receive Filter and Comparator
high and the next comparator pulse is received in less than
2.5 ms. Once CD goes inactive, it takes four consecutive
pulses out of the comparator to assert CD again. Four
consecutive pulses amount to 3.33 ms when the received
signal is 1200 Hz and to 1.82 ms when the received signal
is 2200 HZ. The difference between RxD and RxD_ENH is
evident when CD is low: RxD is then also low, while
RxD_ENH is then high. When CD is high, RxD and
RxD_ENH have the same output.
The received FSK signal first is filtered using a band-pass
filter build around the low noise receiver operational
amplifier “Rx HP filter”. This filter blocks interferences
outside the HART signal band.
R6
R5
C4
RxAF
RxAFI
PC20101118.2
HART IN
C1
Miscellaneous Analog Circuitry
R3
C3
C2
RxA
Voltage References
R4
R1
R2
Rx Comp
The NCN5192 requires two voltage references, AREF
and CDREF. AREF sets the DC operating point of the
internal operational amplifiers and is the reference for the
Rx HP Filter
1.235 VDC
DEMODULATOR
AREF
Rx comparator. If NCN5192 operates at V = 3.3 V the ON
DD
Figure 8. Demodulator Receive Filter and Signal
Comparator
Semiconductor LM285D 1.235
recommended.
V
reference is
The filter output is fed into the Rx comparator. The
threshold value equals the analog ground making the
comparator to toggle on every zero crossing of the filtered
FSK signal. The maximum demodulator jitter is 12 % of one
bit given the input frequencies are within the HART
specifications, a clock frequency of 460.8 kHz ( 1.0 %) and
zero input (RxA) asymmetry.
The level at which CD (Carrier Detect) becomes active is
determined by the DC voltage difference (CDREF - AREF).
Selecting a voltage difference of 80 mV will set the carrier
detect to a nominal 100 mV
.
p-p
Bias Current Resistor
The NCN5192 requires a bias current resistor R
to be
BIAS
connected between CBIAS and V . The bias current
controls the operating parameters of the internal operational
amplifiers and comparators and should be set to 2.5 mA.
SS
Carrier Detect Circuitry
Low HART input signal levels increases the risk for the
generation of bit errors. Therefore the minimum signal
amplitude is set to 80−120 mVpp. If the received signal is
below this level the demodulator is disabled.
This level detection is done in the Carrier Detector. The
output of the demodulator is qualified with the carrier detect
signal (CD), therefore, only RxA signals large enough to be
BIAS
AREF
OPA
detected (100 mV typically) by the carrier detect circuit
p-p
produce received serial data at RxD.
FILTERED
HART IN
KVDE20110407.6
RxAFI
CBIAS
PC20101118 .4
Demodulator
Logic
RBIAS
RxD
Rx Comp
RxD_ENH
AREF
1.235 VDC
Figure 10. Bias Circuit
The value of the bias current resistor is determined by the
reference voltage AREF and the following formula:
Carrier Detect
Counter
CD
CDREF
VAREF – 80 mV
Carrier Comp
DEMODULATOR
AREF
2.5 mA
RBIAS
+
Figure 9. Demodulator Carrier and Signal
Comparator
The recommended bias current resistor is 500 KW when
AREF is equal to 1.235 V.
The carrier detect comparator shown in Figure 9 generates
logic low output if the RxAFI voltage is below CDREF. The
comparator output is fed into a carrier detect block. The
carrier detect block drives the carrier detect output pin CD
high if RTSB is high and four consecutive pulses out of the
comparator have arrived. CD stays high as long as RTSB is
Oscillator
The clock signal used by NCN5192 can either be
460.8 kHz, 921.6 kHz or 1.8432 MHz. This can be provided
by an external clock or a resonator or crystal connected to the
internal oscillator.
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NCN5192
Internal Oscillator Option
Reset
The oscillator cell will function with a 460.8 kHz,
921.6 kHz or 1.8432 MHz crystal or ceramic resonator. A
parallel resonant ceramic resonator can be connected
between XIN and XOUT. Figure 11 illustrates the crystal
option for clock generation using a 460.8 kHz ( 1%
tolerance) parallel resonant crystal and two tuning
The NCN5192 modem includes a Power on Reset block.
An external resistor division of the supply voltage is
required, and should be tied to pin VPOR. This pin is
attached to an internal comparator, and is compared to the
AREF voltage. When this comparator trips, the RESETB
pin will be pulled low and the IC will reset. After VPOR
returns to a valid level, the RESETB pin will be held low for
at least an additional 35 ms (may be longer depending on
clock frequency). The RESETB pin will also be pulled low
when a microcontroller failure is detected. A watchdog will
guard microcontroller communication by looking at the
KICK pin. When the microcontroller fails to provide a
periodical pulse on this pin, the watchdog will pull down the
RESETB pin for 140 ms. A rising edge should be provided
to the IC at least every 53 ms. A 1.8 kHz kick can also be
provided internally if bit 5 of the internal register is set. If the
watchdog kick is provided internally, the KICK pin should
be tied to Vss.
capacitors C . The actual values of the capacitors may
x
depend on the recommendations of the manufacturer of the
resonator. Typically, capacitors in the range of 100 pF to
470 pF are used. Additionally, a resistor may be required
between XOUT and the crystal terminal, depending on
manufacturer recommendation.
The NCN5192 IC uses CLK2 as clock signal for the wave
shaping and digital logic. This signal must be set 460.8 kHz
by activating the proper frequency division in the internal
register (bit 1 and 2). The CLK1 frequency division (bit 3
and 4) can be freely chosen. This programmable clock signal
can be used to drive other ICs such as a microcontroller and
is not used internally in the NCN5192.
POR
AREF
OPA
VDD
Crystal
Oscillator
VPOR
PC20101118.5
XIN
CX
XOUT
CX
460.8 kHz
KVDE20110408 .1
Figure 13. Power on Reset Block
Figure 11. Crystal Oscillator
External Clock Option
It may be desirable to use an external clock as shown in
Figure 12 rather than the internal oscillator. In addition, the
NCN5192 consumes less current when an external clock is
used. Minimum current consumption occurs with the clock
connected to XOUT and XIN connected to V
.
SS
Figure 14. 8 Bit SPI Frame
Crystal
Oscillator
Figure 15. 16 Bit SPI Frame
PC20101118 .6
XIN
XOUT
SPI Communication
460.8 kHz
The SPI bus on the NCN5192 is made up of three signals;
DATA, SCLK, and CS. The data is either 8 bits or 16 bits. In
the case of 8 bits CS will go high for eight clock cycles of
SCLK and in the case of 16 bits CS will be high for 16 clock
cycles of SCLK, as can be seen on Figures 14 and 15.
CS should first go high at least one clock cycle before the
other signals change. One clock cycle is 2.17 ms at a master
Figure 12. Oscillator with External Clock
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10
NCN5192
Internal Register
clock frequency of 460.8 kHz. CS is clocked in at the falling
edge of the CLK1 clock to detect if the data is for the mode
register or the DAC.
The NCN5192 has an 8 bit register to setup its internal
operation. An 8 bit SPI communication method is used to
write to the mode register. If CS goes low after only 8 clock
cycles of SCLK the Mode register will latch in the 8 bits
which are shifted into the SPI shift register. In table x an
explanation of the usage of each bit is given. All bits are set
to ‘0’ at reset.
SCLK can begin to clock in DATA serially to the chip on
the falling edge of SCLK. SCLK should have a maximum
frequency of 460.8 kHz. The format of the data should be
either 8 or 16 bits with the most significant bit first.
DATA is shifted into the chip on the falling edge of SCLK,
and thus for correct operation DATA should change only on
the rising edge of SCLK. The first bit shifted in is the MSB.
If 14 bit DAC communication is utilized, then two 0’s should
precede the 14 bits, and 16 clock cycles on SCLK should
occur. Once the data is shifted in, CS should go low no
sooner than one clock cycle after the last rising edge of
SCLK.
Sigma Delta DAC
The NCN5192 Modem has an integrated Sigma−Delta
Modulator for use in a current loop slave transmitter.
Through this DAC, an analog value can be set and
transmitted across the current loop. For more information on
how to create a current loop slave transmitter, see
application notes on the ON Semi website. The DAC output
will switch between 0 V and the voltage provided to
DACREF. To achieve maximum accuracy, the DACREF
voltage should be kept stable, so that power supply
variations are not visible in the DAC output. The
Sigma−Delta modulator output can be set through SPI
frames containing 14 or 16 significant bits. The length of the
data frames can be set through bit 0 is the status register. The
output of the DAC can be set return to zero (RTZ) or
non−RTZ. This is important when the rise and fall time of the
signal are not identical. This will cause a DC offset
depending on the number of rising and falling edges. As the
output bits of a sigma−delta modulator are randomly
arranged (ie. for the same setting we could get 01110000 or
01010100), the number of edges might vary over time for a
non return to zero signal. Setting the DAC to “return to zero”
forces the output to have a rising and falling edge for each
logic “1” bit, so that no offset from pulse asymmetry can
occur. However, this will decrease the range of the
modulator to 50% of DACREF, as the maximum duty cycle
is 50% instead of 100% for NRZ. When a clock failure is
detected, using an internal oscillator, the DAC output will
jump to the level set by the JUMP pin, until the IC is reset
or a rising flank is detected on KICK.
Table 9. INTERNAL REGISTER DESCRIPTION
Bit
Description
0 (LSB)
0 = DAC in 14−bit mode
1 = DAC in 16−bit mode
1
2
3
4
Set the crystal divide so that CLK2 is 460.8 kHz
Bit 2
Bit 1
0
0
1
1
0
1
0
1
Crystal/2
Crystal/4
Crystal/1
Crystal/4
Set the crystal divide for CLK1
Bit 4
Bit 3
0
0
1
1
0
1
0
1
Crystal/2
Crystal/4
Crystal/1
Crystal/4
5
0 = Watchdog kick external (pin)
1 = Watchdog kick internal (1.8 kHz)
6
0 = RTZ output format on DAC
1 = Non RTZ output format on DAC
7 (MSB)
0 = RxD is low when carrier is off
1 = RxD is high when carrier is off
Setting this bit, changes the function of RxD to
the function of RxD_ENH
Table 10. SPI FRAME FORMAT
Description
Bits
8
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register
Mode Register Data
DAC – 14 bits mode
DAC – 16 bits mode
16
16
DAC Output Word
DAC Output Word
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11
NCN5192
Ordering Information
The NCN5192 is available in a 32−pin no lead quad flat pack (NQFP). Use the following part numbers when ordering.
Contact your local sales representative for more information: www.onsemi.com.
Table 11. ORDERING INFORMATION
Part Number
NCN5192MNG
Package
Shipping Configuration
Temperature Range
32−pin NQFP
Green/RoHS compliant
____ Tube/Tray
−40°C to +85°C (Industrial)
NCN5192MNRG
32−pin NQFP
Green/RoHS compliant
____ Tape & Reel
−40°C to +85°C (Industrial)
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12
NCN5192
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
SOLDERING FOOTPRINT*
L
EXPOSED PAD
5.30
32 X
K
9
16
32 X
17
3.20
8
32 X
0.63
E2
1
24
3.20 5.30
25
32
32 X
b
e
0.10
0.05
C
A
B
C
32 X
0.28
28 X
0.50 PITCH
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCN5192/D
相关型号：
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