NCP12600ACBSN100T1G [ONSEMI]
Multi-Mode Controller for Offline Power Supplies;
| 型号： | NCP12600ACBSN100T1G |
| 厂家： | 
ONSEMI |
| 描述： | Multi-Mode Controller for Offline Power Supplies |
| 文件： | 总24页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP12600
Multi-Mode Controller for
Offline Power Supplies
The NCP12600 is a peak−current controller operating at a 65−kHz
or 100−kHz fixed frequency. In high power conditions, the part
operates in continuous conduction mode (CCM). As the load current
reduces, the converter enters the discontinuous conduction mode
(DCM) of operation and synchronizes the turn−on event with the
minimum of the drain voltage. The NCP12600 implements valley
switching mode with a proprietary lockout scheme ensuring
noise−free operations. As output power further reduces, the controller
folds the switching frequency back and ensures stable valley switching
www.onsemi.com
MARKING
DIAGRAM
TSOP−6
(SOT23−6)
SN SUFFIX
CASE 318G
STYLE 13
nd
operations down to the 32 valley provided the ringing is of sufficient
6zvAYWG
G
1
amplitude. The controller then enters a proprietary Quiet−Skip
skip−mode at small peak currents which reduces acoustic noise and
optimizes no−load standby power.
1
6zvAYW = Specific Device Code
Adjustable over power protection ensures a flat output power level
regardless of the operating input voltage. Slope compensation is
ensured via the insertion of a resistor in series with the current sense
pin and is thus user−adjustable. The device packs several useful
features such as an extremely fast short circuit protection, a soft start in
current and frequency plus a dedicated circuitry to avoid latch off in
case of a line cycle dropout.
z
v
A
Y
W
G
= A or 2 (frequency)
= E, F, G or H
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Over temperature protection (OTP) is implemented at the current
sense pin and requires the connection of a simple NTC resistance to
the auxiliary winding. Over voltage protection (OVP) is done by
PIN CONNECTIONS
sampling the auxiliary plateau and exists at the V pin level.
cc
GND
FB
1
2
6
5
4
DRV
Features
V
CC
• 65−kHz or 100−kHz Fixed−frequency Operation
• Valley Switching in Discontinuous Conduction Mode for Improved
Efficiency
ZCD/Fault
3
CS
(Top View)
• Proprietary Valley Lockout for Controlled Operation in
Quasi−resonant Operation and Foldback Modes
• Proprietary Quiet Skip Mode for Noiseless Operation in Light Load
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 3 of this data sheet.
• Adjustable Over Power Protection
• Single 64−ms Protection Timer or Dual OCP Protection in Option
• Frequency Foldback down to 25 kHz
• Auto−recovery or Latched Overload Protection
• Over Temperature Protection Combined on CS Pin
• Ultra−low Start−up Current Below 10 mA up to 125°C T
• Proprietary Quick Latched−state Reset Scheme
• These are Pb−Free and RoHS−compliant Devices
• True Output Short Circuit Protection with Pre−short
j
Compatibility
• Line Cycle Dropout Recovery in Latched OCP Mode
• 5−ms Soft Start on Both Peak Current and Frequency
for Lower Start−up Stress
Typical Applications
• Ac−dc Notebook Adapters, USB Adapters, Wall−mount
Power Supplies, Set Top Boxes, etc.
• Frequency Jitter in All Operating Modes
• Over Voltage Protection with Precise Auxiliary Voltage
Sampling Event
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2018 − Rev. 0
NCP12600/D
NCP12600
Vbulk
Vout
.
.
.
OTP
opt.
NCP12600
1
2
3
6
5
4
slope
compensation
Figure 1. Typical Application Schematic
Table 1. PIN DESCRIPTION
Pin No Pin Name
Function
−
Pin Description
1
2
3
GND
FB
The controller ground.
Feedback pin
Feedback input for the controller. Allows direct connection to an optocoupler.
ZCD/
OPP/
fault
Detects core reset in QR operation.
Latches off the part in OVP. Adjusts
OPP level.
A resistive bridge from this pin to the auxiliary winding adjusts the OPP
level and lets the controller observe the core magnetic state. A precise
OVP level can also be set via this pin.
4
CS
Current sense
This pin monitors the primary peak current but also offers a means to ad-
just the compensation ramp level. A NTC connected to the pin offers a
simple over temperature protection.
5
6
V
Supplies the controller
Driver output
This pin is connected to an external auxiliary voltage and features an over
voltage protection circuitry.
cc
DRV
The driver’s output to an external MOSFET gate. It is clamped to a safe
12−V gate−source level.
Options
Forming the part−number:
Y is the protection scheme:
NCP12600xyzSN65T1G – 65−kHz version with xyz picked
up in the below list
A = all protections are latched: OVP on demag, V OVP,
OTP on CS, overload (OCP) and short circuit (SCP)
cc
NCP12600xyzSN100T1G – 100−kHz version with xyz
picked up in the below list
B = overload (OCP) and short circuit (SCP) are in
auto−recovery mode, all other protections (OVP on demag,
V
cc
OVP, OTP on CS) are latched
The following code is adopted for the three letters x, y and z:
C = all protections are in auto−recovery: OVP on demag, V
OVP, OTP on CS, overload (OCP) and short circuit (SCP)
cc
X implies the following choice:
A = single OCP
Z implies the following options:
A = quiet skip
B = dual−level OCP level
B = normal skip mode
600
X
Y
Y
OCP trip point
OCP Fault
A – All latched
Quiet Skip
A – Yes
A – single, V = 0.7 V (max I )
CS
p
Part
B − dual, V = 0.5 V (overload), V = 0.7 V (max I )
B – SC/OCP autorecovery, rest is latched
C – All autorecovery
B – No
CS
CS
p
C to Z − reserved
www.onsemi.com
2
NCP12600
ORDERING INFORMATION
Freq.
(kHz)
OCP
SCP
OVP
aux
OTP
CS
OVP
V
cc
Controller
Marking
Mode
Skip Package
Shipping
NCP12600AAASN65T1G
NCP12600ABASN65T1G
NCP12600ABBSN65T1G
NCP12600ACBSN65T1G
NCP12600AAASN100T1G
NCP12600ABASN100T1G
NCP12600ACBSN100T1G
6AE
6AF
6AG
6AH
62E
62F
62G
65
65
L
L
L
L
L
L
S
S
S
S
S
S
S
Q
Q
N
AR
AR
AR
L
L
65
L
L
L
3000 /
Tape &
Reel
TSOP6
N
65
AR
L
AR
L
AR
L
(Pb−free)
100
100
100
Q
Q
N
AR
AR
L
L
L
AR
AR
AR
AR
L
OCP
SCP
Mode
Skip
auto−recovery: the controller enters hiccup mode and tries to resume operations
latched: the controller is latched and the user needs to cycle the input voltage to restart
over current protection: the power supply is overloaded
short circuit protection: the power supply output is short circuited
single (S) or dual (D) trip point in overload
normal (N) or Quiet Skip (Q)
Jitter in
CCM
BO?
1.5 us
blanking
OVP1
OTP
UVLO
OVP2
Vcc
Fault Management
Timers, UVLOs
+
−
ZCD
+
−
VZCD
+
−
DCM? DMG
Fixed Fsw
or VCO
Vcc discharge
Multi−Mode Management
Fixed Frequency or
Valley Lockout Operation
OVP1
400 mV
VOVP1
Clamp
clock
FB
−
Vdd
slow
clock
+
reset
S
R
Vcc
60mV
in
out
Drv
Q
Q
RFB
Gnd
FB
Qb
−
FB
always
neg. or
0
+
1.5 us
blanking
Max
Ip
−
+
+
OTP
Qb
−
Skip
+
VOTP
Vilim
skip
LEB
CS
+
Rramp
slope comp.
Jitter in
DCM
Figure 2. Internal Block Diagram
www.onsemi.com
3
NCP12600
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
V
Power Supply voltage, VCC pin, continuous voltage
DRV pin voltage, transigent voltage (Note 1)
Maximum voltage on low power pins CS and FB
Maximum negative transient voltage on ZCD pin (Note 2)
Maximum positive transient voltage on ZCD pin ( 2)
Maximum sourced current, pulse width < 800 ns
Maximum sinked current, pulse width < 800 ns
Maximum injected negative current into the ZCD pin (pin 1)
Thermal Resistance Junction−to−Air
−0.3 to 28
CC
DRV(tran)
V
−0.3 to V + 0.3
V
CC
V
, V , V
FB ZCD
−0.3 to 5.5
V
CS
V
−1
V
ZCD(trann)
ZCD(tranp)
source,max
V
7
V
I
0.6
A
I
1.0
A
sink,max
I
−2
mA
°C/W
°C
°C
kV
ZCD
R
T
360
q
J−A
Maximum Junction Temperature
150
−60 to +150
7
J,max
Storage Temperature Range
HBM
Human Body Model ESD Capability per JEDEC JESD22−A114F (All pins)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. See below figure for detailed specification of transient voltage
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
www.onsemi.com
4
NCP12600
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V unless otherwise noted)
J
J
J
cc
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION AND V MANAGEMENT
CC
V
V
level at which driving pulses are authorized
level at which driving pulses are stopped
V
increasing
decreasing
V
CC(on)
16
8.3
7.7
18
20
V
V
CC
CC
CC
V
CC
V
8.9
9.5
CC(min)
CC(hyst)
CC(reset)
Start−up hysteresis
Hysteresis V
– V
V
V
CC(on)
CC(min)
Latched−state reset voltage
–
V
8.65
150
V
Hysteresis above V
Hysteresis below V
for fast hiccup
before reset
V
mV
V
cc(min)
CC(hiccup)
Hysteresis V
–
V
0.18
–
0.33
0.42
10
CC(min)
CC(min)
CC(reset)
CC(reset,
hyst)
V
Start−up supply current, controller disabled or
latched
V
CC
= V
– 100 mV
I
5
mA
CC(on)
CC1
Internal IC consumption, steady state
F
= 65 kHz, C
= 0 nF,
= 0 nF,
I
–
1
mA
sw
DRV
CC2
V
FB
= 3.2 V
F
sw
= 100 kHz, C
1.1
DRV
V
FB
= 3.2 V
Internal IC consumption, steady state
F
= 65 kHz, C
= 1 nF,
= 1 nF,
I
–
1.7
2.3
mA
sw
DRV
CC3
V
FB
= 3.2 V
F
sw
= 100 kHz, C
DRV
V
FB
= 3.2 V
Internal IC consumption, skip mode – non switching
Feedback voltage is below
skip level
I
300
420
mA
mA
CC(no−load)
Internal IC consumption in skip mode – switching in
application, for information only
(V = 12 V, driving a typical
I
CC(standby)
cc
7−A/650−V MOSFET, includes
optocoupler current)
Internal IC consumption from OVP acknowledgment
IC detects an OVP and quickly
I
1
mA
CC(OVP)
to V
– Single−shot event
brings V to V
for hiccup
CC(off)
CC
CC(off)
CURRENT SENSE COMPARATOR
Maximum Current Sense Voltage Limit – no OPP
V
V
= V
, V increasing
V
V
0.65
0.46
0.7
0.5
0.75
0.53
V
V
FB
FB(max)
CS
ILIM1
V
< –60 mV (Notes 4, 5)
ZCD
Overload Current Sense Voltage Threshold – dual
OCP option
= V
, V increasing
CS
FB
FB(max)
ILIM2
Cycle by Cycle Leading Edge Blanking Duration
Cycle by Cycle Current Sense Propagation Delay
t
230
–
280
50
340
100
ns
ns
LEB1
V
CS
> (V
+ 100 mV) to DRV
turn−off
t
ILIM
ILIM
Maximum Setpoint decrease for pin 3 biased to
–290 mV (Note 6)
V
ZCD
= –290 mV
IOPP
32.8
%
M
Voltage setpoint for pin 3 biased to −250 mV (Note 6)
IOPPv
0.46
0.51
600
−60
200
5
0.56
V
ET
Blanking delay before considering V
Pin 4 voltage bias for 0% OPP
Frozen CS voltage in skip mode
for OPP
IOPP
ns
ZCD
del
V
= −60 mV
IOPP
mV
mV
ms
ZCD
0
V
= 1 V
V
freeze
FB
Soft start, time to meet I
at start up
Open feedback pin
t
SS
p,max
OSCILLATOR
Oscillator frequency – nominal (65 kHz version)
Oscillator frequency – nominal (100 kHz version)
Oscillator frequency – minimum
2.4 V < V < 3.8 V
f
61
90
23
76
65
100
26
71
110
31
kHz
kHz
kHz
%
FB
osc,nom
f
osc,nom
2.4 V < V < 3.8 V
FB
V
FB
< 1.3 V
f
osc,min
Maximum duty ratio
D
max
4. OPP is not active as long as the negative voltage on the ZCD pin during t is less than –60 mV.
on
5. beyond 3.8 V, the peak current is clamped to V
.
ILIM
6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV.
www.onsemi.com
5
NCP12600
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V unless otherwise noted)
J
J
J
cc
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency jittering in percentage of f
CCM−only operation
Internal offset to CS control
–
f
6
10
1
%
osc
jitter
Frequency jitter in valley−switching mode
Jitter modulation frequency in all modes
f
mV
kHz
ms
swingDCM
f
swing
Soft−start, time to meet nominal F at start up
Open feedback pin
t
5
sw
SS
INTERNAL SLOPE COMPENSATION
Artificial ramp level for slope compensation
Internal ramp resistance to CS pin
FEEDBACK SECTION
Internal level at T = 25°C
V
−
−
4.2
−
−
V
j
ramp
R
20.4
kW
ramp
Feedback Input Open Voltage
FB pin is unloaded
V
4
V
–
FB(open)
Internal Current Setpoint Division Ratio
Pull−up resistance
−
−
−
−
−
K
ratio
−
−
5.4
40
29
2.4
1.9
1.0
26
60
−
−
R
kW
kW
V
FB
Equivalent resistance for the optocoupler
R
eq
Frequency foldback threshold, F < 65 kHz
V
fold
2.3
1.8
0.9
2.5
2
sw
End of frequency foldback threshold
V
V
fold,end
Feedback voltage thresholds for skip mode
V
FB
going down, T = 25°C
V
skip(in)
1.1
V
J
Skip−cycle current in percentage of I
Hysteresis on skip comparator
QUIET SKIP ONLY
−
I
%
mV
LIM
skip
V
FB
is going up
I
skip,hys
Minimum number of pulses in burst
Skip out delay
n
t
3
−
−
−
−
ms
ms
V
P,skip
t
−
38
1.5
2.2
skip
Quiet−Skip timer
1.0
1.8
1.25
2
quiet
Quiet−Skip escape level (transient enhancer)
V
FB
going up, T = 25°C
V
skip(tran)
J
DEMAGNETIZATION SENSE
V
threshold voltage
hysteresis
V
decreasing
increasing
V
ZCD(TH)
25
−
45
30
70
−
mV
mV
V
ZCD
ZCD
ZCD
V
V
V
ZCD(HYS)
ZCD
Threshold voltage for output short circuit or aux.
winding short circuit detection (enter)
After t
if V
<
>
V
0.4
delay_ZCD
ZCD
ZCD(short1)
V
ZCD(short1)
Threshold voltage for output short circuit or aux.
winding short circuit detection (exit)
After t
if V
V
0.5
V
delay_ZCD
ZCD
ZCD(short2)
V
ZCD(short2)
Propagation Delay from valley detection to DRV high
Internal delay after demagnetization detection
V
decreasing from 3 V to 0 V
−
T
−
−
150
ns
ns
ms
ZCD
DEM
t
100
5.5
delay
Timeout after last demagnetization transition
(leakage ringing blanking)
T
timout
4.5
−
6.5
0.1
Input leakage current
V
> V
V
= 3 V,
I
ZCD
−
mA
CC
CC(on) ZCD
DRV is low
Low−V flag activation – latched OCP version only
Neg. bias present during the
on−time
V
BOin
−22
−30
−38
mV
in
DRIVE OUTPUT
Drive resistance
DRV Sink
W
R
R
−
−
16
22
−
−
SNK
SRC
DRV Source
4. OPP is not active as long as the negative voltage on the ZCD pin during t is less than –60 mV.
on
5. beyond 3.8 V, the peak current is clamped to V
.
ILIM
6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV.
www.onsemi.com
6
NCP12600
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V unless otherwise noted)
J
J
J
cc
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
DRIVE OUTPUT
Rise time
C
C
= 1 nF, from 10% to 90%
= 1 nF, from 90% to 10%
t
−
−
8
40
30
−
ns
ns
V
DRV
r
Fall time
t
f
DRV
DRV Low voltage
V
= V
+ 0.2 V,
V
−
CC
CC(off)
DRV(low)
C
= 220 pF, R
= 33 kW
DRV
DRV
DRV High voltage
V
CC
= V
−0.2 V C =
DRV
V
10
12
14
V
CC(OVP)
,
DRV(high)
220 pF, R
= 33 kW
DRV
Source current
Sink current
Peak source current V = 0 V
I
300
500
mA
mA
GS
source
Peak sink current V = 12 V
I
sink
GS
PROTECTIONS
Auto−recovery thermal shutdown
Thermal Shutdown Hysteresis
Device switching
Device switching
T
−
−
150
40
−
−
°C
°C
V
SHTDN
T
SHTDN(HYS)
Fault level detection for OVP, demagnetization pin,
sensing
Internal sample V increasing
V
2.85
3.15
3.35
out
OVP1
t
off
Fault level detection on CS pin for OTP implemen-
tation – confirmation delay is T
Internal sample V increasing
V
OTP
0.97
1
1.03
V
CS
PP
Over Voltage Protection on the V pin
–
V
24
25.5
1.5
27
V
cc
OVP2
Sampling delay for OTP and OVP detection
(F = 65 kHz)
sw
Sampling event on ZCD and
CS pins
T
1.2
1.8
ms
delay_ZCD1
Sampling delay for OTP and OVP detection
(F = 100 kHz)
sw
Sampling event on ZCD and
CS pins
T
0.8
−
1.1
8
1.3
−
ms
−
delay_ZCD2
Number of drive cycles before latch confirmation on
OVP1 and 2
V
ZCD
> V
T
latch_count
OVP1
Timer Delay Before Fault Acknowledgment −
Condition 1 – single OCP only
CS pin is w 0.7 V
CS pin w 0.5 V
T
55
200
55
64
256
64
8
75
300
75
ms
ms
ms
PP1
Timer Delay Before Fault Acknowledgment in
Overload Condition – dual OCP only
T
OCP
Timer Delay Before Fault Acknowledgment with
dual OCP – dual OCP only
CS pin is w 0.7 V
T
PP2
Timer Delay in Clock Cycles Before Fault
Acknowledgment when in Output Short Circuit –
Condition 2
V
ZCD
< 0.4 V
T
SCP
Unit is clock cycles
4. OPP is not active as long as the negative voltage on the ZCD pin during t is less than –60 mV.
on
5. beyond 3.8 V, the peak current is clamped to V
.
ILIM
6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Condition 1: V is pushed to its maximum open−loop value. The demagnetization pin during the off−time is above 0.4 V.
FB
Condition 2: V is pushed to its maximum open−loop value. The demagnetization pin during the off−time is less than 0.4 V.
FB
8 clock cycles are counted and the part latches off or goes into auto−recovery. This mechanism only activates once the 5−ms
soft−start sequence is completed.
www.onsemi.com
7
NCP12600
TYPICAL CHARACTERISTICS
19.0
18.8
18.6
18.4
18.2
18.0
17.8
17.6
17.4
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
17.2
17.0
8.2
8.0
−50
−50
−25
0
25
50
75
75
75
100
100
100
125
125
125
−25
0
25
50
75
75
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3.
Figure 4.
10.0
9.8
9.0
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.1
8.0
−50
8.2
8.0
−50
−25
0
25
50
−25
0
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5.
Figure 6.
7.0
6.5
6.0
5.5
5.0
0.320
0.315
0.310
0.305
0.300
F
SW
= 65 kHz
F
SW
= 65 kHz
0.295
0.290
4.5
4.0
−50
−25
0
25
50
−50
−25
0
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7.
Figure 8.
www.onsemi.com
8
NCP12600
TYPICAL CHARACTERISTICS
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.20
2.15
2.10
2.05
2.00
0.9
0.8
−50
−25
0
25
50
75
100
100
100
125
125
125
−50
−25
0
25
50
75
75
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9.
Figure 10.
1.20
1.15
1.10
1.05
1.00
2.00
F
SW
= 65 kHz
F
SW
= 65 kHz
1.98
1.96
1.94
1.92
1.90
1.88
1.86
1.84
0.95
0.90
1.82
1.80
−50
−25
0
25
50
75
−50
−25
0
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11.
Figure 12.
1.14
1.13
1.12
1.11
0.320
F
SW
= 100 kHz
0.315
0.310
0.305
0.300
1.10
1.09
0.295
0.290
−50
−25
0
25
50
75
−50
−25
0
25
50
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13.
Figure 14.
www.onsemi.com
9
NCP12600
TYPICAL CHARACTERISTICS
2.40
2.38
2.36
2.34
0.705
0.704
0.703
0.702
0.701
0.700
0.699
0.698
2.32
2.30
F
= 100 kHz
100
SW
0.697
−50
−50
−25
0
25
50
75
125
125
125
−25
−25
−25
0
0
0
25
50
75
75
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15.
Figure 16.
0.60
0.55
0.50
281
280
279
278
277
0.45
0.40
276
275
−50
−25
0
25
50
75
100
−50
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17.
Figure 18.
1.006
1.004
1.002
1.000
0.998
3.163
3.158
3.153
3.148
3.143
3.138
0.996
0.994
3.133
3.128
−50
−25
0
25
50
75
100
−50
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19.
Figure 20.
www.onsemi.com
10
NCP12600
TYPICAL CHARACTERISTICS
4.00
25.56
25.51
25.46
3.95
3.90
3.85
3.80
125.41
25.36
−50
−25
0
25
50
75
100
125
125
125
−50
−25
0
25
50
75
75
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21.
Figure 22.
3.50
18.7
18.2
17.7
17.2
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
16.7
16.2
3.05
3.00
−50
−25
0
25
50
75
100
−50
−25
0
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23.
Figure 24.
30.0
29.9
29.8
29.7
29.6
29.5
29.4
29.3
29.2
67.0
66.5
66.0
65.5
65.0
F
SW
= 65 kHz
64.5
64.0
29.1
29.0
−50
−25
0
25
50
75
100
−50
−25
0
25
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25.
Figure 26.
www.onsemi.com
11
NCP12600
TYPICAL CHARACTERISTICS
102.0
26.4
26.2
26.0
25.8
25.6
25.4
101.5
101.0
100.5
100.0
99.5
F
= 65 kHz
0
25.2
25.0
SW
F
= 100 kHz
0
SW
99.0
−50
−50
−25
25
50
75
100
100
0
125
125
25
−25
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27.
Figure 28.
27.0
26.9
80.0
79.8
79.6
79.4
26.8
26.7
26.6
26.5
26.4
26.3
26.2
79.2
79.0
78.8
78.6
78.4
78.2
78.0
26.1
26.0
F
= 100 kHz
SW
−50
−25
0
25
50
75
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29.
Figure 30.
80.0
79.8
79.6
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
−50
−25
50
75
100
125
TEMPERATURE (°C)
Figure 31.
www.onsemi.com
12
NCP12600
Application Information
The NCP12600 includes a state−of−the−art multi−mode
controller packed in tiny 6−pin package for
fixed−frequency current mode control flyback converters
applications. Despite its limited amount of pins, the
controller includes numerous proprietary functions which
make it an ideal candidate for cost−sensitive applications.
• Low start−up current: A low start−up current is key to
a
reducing the standby power in no− or light− load
situations. With a 10−mA max guaranteed up to 125°C,
the NCP12600 lets you enjoy high−valued start−up
resistors for the best standby power performance.
• Over voltage protection: By precisely sampling the
auxiliary winding plateau voltage after the leakage
inductance is damped, the circuit monitors the reflected
output voltage with excellent precision. When the
monitored voltage exceeds the internal threshold more
than 8 successive clock cycles, the part definitively
latches off.
• Fixed−Frequency Operation: Implementing peak
current mode control, the NCP12600 drives a flyback
converter at a 65−kHz or 100−kHz fixed switching
frequency and can operate in discontinuous conduction
mode (DCM) or continuous conduction mode (CCM).
• When DCM operation occurs in fixed−frequency
operation, the converter locks in a valley and a specific
mechanism paces valley jumps. When the output power
reduces, the part enters frequency foldback and jumps
into the valleys as the load further reduces. Going down
to 32 valleys (if available), the part ensures the lowest
turn−on losses and enables excellent overall efficiency.
As output power further goes down, the Voltage−
Controlled Oscillator (VCO) takes over and reduces
frequency down to 25 kHz where the current freezes to
26% of the maximum peak value. Then the part enters
normal skip cycle at lower power levels or in a no−load
situation.
• Over current protection: When the circuit senses that
the feedback loop is lost, V > 3.8 V, an internal
FB
64−ms timer counts. If the fault disappears while
countdown has started, the timer resets and the power
converter keeps operating. If the timer elapses, all
pulses are immediately stopped and the part enters an
auto−recovery hiccup mode.
• True short−circuit protection: By observing the peak
current setpoint and the off−time voltage on the
demagnetization pin, the circuit can detect an output
short circuit situation. When this conjunction of events
is confirmed, the SCP timer keeps counting. If this
situation is observed for more than 8 clock cycles, the
circuit immediately stops pulses and enters
• Quiet−Skip operation: classical skip cycle occurring in
light load is a known mechanism to improve the
converter’s efficiency when the load current becomes
lighter. Quiet−Skip also reduces acoustic noise by
preventing the skip mode burst period from entering the
audible range. The part is also available with a normal
skip option.
auto−recovery or latched state. This circuit is active
during a start−up sequence (after SS has completed)
and in auto−recovery hiccup: if the demagnetization pin
is less than 0.4 V after the soft−start period (peak
current is maximum), then 8 cycles are counted and the
part stops operations. This is extremely efficient to
protect against board−level short circuits occurring at
• Temporary and peak power capability: the part includes
a 2−level OCP allowing the converter to permanently
deliver a certain amount of power as long as V is less
high line as the RCD circuit can fail to keep the V
CS
DS
than 0.5 V. When VCS exceeds 0.5 V, a 256−ms timer
withing safe limits.
is activated. If V further increases, the switching
frequency remains constant and the controller pushes
FB
• A general reset is implemented at too low an input
voltage and avoids latch off in line dropout tests with
V
CS
to its maximum value, the 256−ms OCP timer is
OCP−latched versions of the NCP12600. When V
out
instantaneously divided by 4 and becomes a 64−ms
timer. When it elapses, the part enters an auto−recovery
or latched mode depending on the selected option. As
such, the converter can be thermally designed for a
collapses within a line cycle dropout test, the part does
not latch (in case the latched option has been selected)
but nicely recovers when the mains is back to its
normal level.
0.5−V V and authorizes temporary excursions to a
CS
• Quick reset scheme: When latched on an OVP or an
OCP situation, the part will enter a fast low−voltage
hiccup mode slightly above the reset voltage. The reset
time by input power cycling will be greatly reduced
compared to existing solutions.
higher power level. Please note that the controller also
exists in a single OCP level (0.7 V, 64 ms duration)..
• Adjustable over power protection (OPP): Switching
power supplies are prone to output power runaway in
high−line conditions. To keep the delivered power
within control along the input voltage range, a circuit
observes the negative voltage present on the
• Frequency jitter: An internal clock modulates the
switching frequency and provides an efficient energy
spread to ease the converter’s EMI signature. Jitter
demagnetization pin during the on−time and subtracts it
from the maximum peak current limit.
www.onsemi.com
13
NCP12600
operates in fixed−frequency mode but also in QR and
foldback modes when the VCO is active.
clock (LFC) initiates a valley acquisition and increases or
decreases valley count during operations. When the next
low−frequency clock occurs, a new valley acquisition is run
to determine what valley number matches the upcoming
65−kHz (or 100 kHz) or VCO pulse. It is like a snapshot
where you freeze the converter operating point for the
• Over temperature protection is implemented by forming
a resistive divider on the CS pin. The auxiliary voltage
appears during the off time and the CS level is only
considered after the 1.5−ms blanking time (1.1 ms for
the 100−kHz version). For a well−regulated output
voltage, the precision favorably compares with a
classical pull−down NTC on a dedicated pin.
• Temperature shutdown: the controller includes an
internal thermal sensor which protects the circuit in
case of thermal runaway.
st
upcoming period of time. For example, assume the 1 valley
rd
was selected, then the new acquisition may confirm the 3
valley is the correct one and the part locks in valley 3. It
remains there until the next acquisition occurs or a transient
unlocks the control. That way, jumping between valleys
occurs at a controlled recurrence and not in a completely
random way, reducing the possibility to excite a mechanical
resonance on the transformer.
Overall Description
The NCP12600 builds upon previous generations of
fixed−switching frequency power suppy controllers. The
frequency is fixed in nominal power conditions but reduces
as the load is getting lighter. The major improvement lies in
the valley−switching operation: when DCM is entered
whether it is in high−power mode or in foldback, the
controller locks in the valley to ensure the best efficiency.
When variable frequency mode is activated, the part locks
in valleys and remains in this state. The peak current is free
to move at all times.
Variable Frequency Mode
When the load gets lighter, the feedback voltage starts
decreasing. When it reaches 2.4 V, the VCO takes over and
frequency reduces. When VFB reaches 1.9 V, the frequency
is clamped down to 25 kHz. Below this value, F is fixed
and down to the skip cycle point, the part operates in peak
current mode control.
When the frequency reduces, the controller selects the
valley next to the VCO clock and locks in until the next
refresh signal comes from the LFC. By using a 5−bit counter,
sw
nd
the controller goes down to the 32 valley if necessary.
CCM Operation
When a transient is detected on the feedback voltage (load
re− or disconnection), the LFC disappears and the part
returns to a classical fixed−frequency operation for the best
transient response.
In fixed−frequency operation, the part switches at 65 kHz
or 100 kHz in current−mode control and the feedback
permanently adjusts the current setpoint. For a feedback
voltage beyond 3.8 V, the peak current voltage setpoint is
clamped to 0.7 V. The situation with this maximum current
Protections
cannot last more than 64 ms (T ). However, if a true short
PP
There are several types of protection depending on
loading conditions:
circuit is detected in the output, the controller could
potentially place the converter in a dangerous situation if it
1. When the load imposes a peak current setpoint
greater than 0.7 V, the 64−ms timer starts counting.
When it elapses, the converter latches off or enters
auto−recovery depending on the selected option.
2. A dual OCP version exists also for peak power
capability: when the peak current setpoint reaches
0.5 V, the 256−ms timer starts counting. If the
were pulsing while V is almost 0 V (heavy CCM can occur
out
in the primary side with a RCD clamp voltage runaway). To
avoid this stressful situation, the circuit senses the voltage on
the demagnetization pin during t . If during t the
off
off
demagnetization pin voltage is less than 0.4 V for more than
8 consecutive clock cycles, the controller stops all pulses
and goes into latch or auto−recovery mode depending on the
selected option. If during this mode and before the 8−cycle
timer ends, the short circuit disappears and the
demagnetization voltage goes above 0.5 V, the protection
scheme is reset.
power further increases, V also does and
CS
touches the 0.7−V limit. At this moment, the timer
is divided by 4, authorizing a 64−ms duration in
this mode. Afterwards, the controller latches off or
enters an auto−recovery cycle.
3. In this maximum power mode, the converter
DCM Operation
observes the demagnetization voltage during t
If this voltage is lower than 0.4 V and if this
.
off
In fixed−frequency operation, it is very likely that low−
and high−line conditions lead to a different operating point
situation lasts for more than 8 consecutive clock
cycles, the controller immediately stops pulsing
and enters auto−recovery or latches off depending
on the selected options.
for a given P : CCM in low line and DCM in high line.
out
When the controller operates in CCM, the MOSFET is
turned on at a pace imposed by the regular clock. When
DCM is entered, the controller senses this mode and extends
the off−time to exactly match the next available valley. The
peak current is free to move while locked in the valley
whether the part operates in fixed frequency mode or in
foldback. Inside the controller, a low−frequency refresh
4. During start−up, the controller also observes the
demagnetization pin during the off−time. If this
voltage is less than 0.4 V once the soft−start
sequence is over (peak current is max) while F is
sw
www.onsemi.com
14
NCP12600
65 kHz (or 100 kHz), then the controller counts 8
7. A similar sampling occurs on the CS pin to check
if an OTP event is detected. When the pin exceeds
1 V during the off time for more than 64 ms, the
part latches off (or hiccups depending on the
selected option).
clock cycles and terminates operation. V goes
cc
down to UVLO and the IC restarts (hiccup mode)
or remains latched (latched version).
5. At any moment when the 64−ms timer circuit is
counting, the controller observes a brown−out
Start−up Sequence
(BO) flag raised if V
is less than V
. If a
ZCD
BOin
As illustrated in Figure 32, peak current and the switching
frequency are gradually increased at start−up in a 5−ms
soft−start (SS) sequence. Frequency starts from 25 kHz and
hits 65 kHz (or 100 kHz) after 5 ms as feedback voltage is
pushed to its maximum value. The 64−ms timer counts as
condition arises during which the BO flag is raised
AND any of the timer is counting, all pulses stop
but the resulting counter effect (latch for instance)
is ignored and V is let go down to UVLO for a
cc
quick recovery. With this technique, when adapters
featuring a latched OCP option are tested in line
cycle dropouts, even if the converter would like to
latch off because the mains has disappeared while
it was heavily loaded, the circuit prevents this and
forces the converter to auto recover when the
mains is restored..
V
CS
is above 0.7 V. When the 5−ms SS sequence is over, the
peak current is maximum. During this sequence (V is still
FB
pushed to the max, V is not on target), if V accidentally
out
cc
touches UVLO, the part featuring the pre−short option
immediately latches off. On the contrary, if everything goes
well – the loop closes (V is on target) before V touches
out
cc
UVLO and the 64−ms timer is reset. If an UVLO event
occurs after a normal start−up sequence, it auto−recovers as
it should. This smooth start−up mode helps reduce the stress
on the output diode or in the synchronous MOSFET when
power up occurs on heavy load. As this mode is also
activated in auto−recovery protection (for the selected
option), it significantly reduces the stress on the various
power components when the converter tries resuming
operations. Figure 32 offers a typical drive waveform
captured during the power−on sequence.
6. The part senses the plateau voltage on the
demagnetization pin 1.5 ms after the power switch
has been turned off (1.1 ms for the 100−kHz
version). This helps ignore the leakage ringing and
offers a clean plateau voltage to sense. When the
voltage on the demagnetization pin exceeds 3.15 V
for 8 consecutive clock cycles, the part latches off
(or hiccups depending on the selected option).
This is an easy and efficient way to protect the
converter in an OVP situation.
Power on
vDRV
t
( )
25 kHz
65 kHz
5−ms SS
= 1.4 ms
ton
40 ms
25 kHz
Figure 32. During the start−up sequence, both frequency and current setpoint are slowly raised for 5 ms
The NCP12600 start−up voltage is purposely made high
controller start−up current is purposely kept low, below
10 mA and it is guaranteed up to a 125°C junction
temperature. Start−up resistors can therefore be connected
to the bulk capacitor or directly to the mains input voltage if
desired to save a few more mW.
to permit large energy storage in a small V capacitor value.
cc
This helps operation with a small start−up current which,
together with a small V capacitor, will not hamper the
cc
start−up time. To further reduce the standby power, the
www.onsemi.com
15
NCP12600
R3
R1
R4
R2
D1
D3
D2
D4
D5
1N4148
D6
BAV21
I2
I1
Vcc
Cbulk
Input
mains
C1
X2
I3
.
aux
ICC1
C4
CVcc
Figure 33. The startup resistor can be connected to the input mains for further power dissipation reduction
Figure 33 shows a typical recommended configuration
where start−up resistors connect together to the mains input.
This technique offers the benefit of freely discharging the
X2 capacitor usually part of the EMI filter. The calculation
of these resistors depends on several parameters. Assuming
a 0.47−mF X2 capacitor, the safety standard recommends a
time constant t less than 1 s maximum when a resistor is
connected in parallel to provide a discharge path. This sets
the upper limit for the sum of discharge resistors connected
inputs (two half−wave connections then), half of the average
current I is defined by:
1
Ǹ
Vac,rms
2
* VCCon
Rstartup
I1
2
p
+
(eq. 4)
To make sure this current is always greater than 15 mA
(half of the necessary 30−mA current), the minimum value
for R
can be extracted:
start−up
Ǹ
(eq. 5)
Vac,rms
p
2
to the controller V :
cc
85 1.414
−V
−18
CCon v
v 1.3 MW
p
Rstart−up
v
1
(eq. 1)
Rstartup
t
t 2.1 MW
ICV
15 m
,min
0.47 m
CC
We could thus connect two resistors of 1.3 MW (total
2.6 MW) across the line to a) power the IC at start up b)
ensure X2 discharge when the user unplugs the adapter.
However, 2.6 MW conflicts with (1) and we will reduce the
1.3−MW resistor to a 1−MW value, totaling 2 MW, in
agreement with (1).
The first step starts with the calculation of the needed V
capacitor which will supply the controller until the auxiliary
cc
winding takes over. Experience shows that this time t can
1
be between 5 and 20 ms depending on the loading conditions
and the output capacitance. Considering that we need at least
an energy reservoir for a t time of 10 ms, the V capacitor
1
cc
must be larger than:
Multi−mode Operation
(eq. 2)
The NCP12600 works as a classical fixed−switching
frequency controller and can operate in CCM and DCM.
When the load current is reducing, the converter eventually
enters DCM. At this moment, NCP12600 implements a
proprietary multimode engine which locks in the
drain−source valley to improve efficiency. The frequency is
now fixed but the peak current is free to move to maintain
ICCt1
VCCon * VCCmin
1.5 m 10 m
CVCC
w
w
w 1.6 mF
9
Let us first select a 2.2−mF capacitor at first and
experiments in the laboratory will let us know if we were too
optimistic for t . Testing across temperature range is
1
important as capacitance and ESR of this V capacitor can
cc
be affected. The V capacitor being known, we can now
cc
V
out
in regulation. An internal refresh clock will start a new
evaluate the charging current we need to bring the V
cc
acquisition and valley jump occurs but at a controlled pace.
This operation differs from other controllers in which the
selected valley changes on the fly, resulting in a
spectrally−distributed perturbation. This uncontrolled
perturbation can possibly mechanically excite the
transformer and generate acoustic noise. Here, because the
refresh frequency is constant, it is less likely to excite the
transformer across a variety of frequencies and acoustic
noise is eliminated in this mode. In case a transient load
occurs, the controller naturally returns to its normal
operating mode until the feedback stabilizes again.
voltage from 0 to the IC VCC voltage, 18 V typical. This
on
current has to be selected to ensure start−up at the lowest
mains (85 V rms) to be less than 3 s (2.5 s for design margin)
typically for an adapter:
V
CConCV
2.5
18 2.2 m
Icharge
w
CC w
w 16 mA
(eq. 3)
2.5
If we account for the 10−mA current that flows inside the
controller (I in Figure 33), then the total charging current
1
delivered by the start−up resistor must be 26 mA, rounded to
30 mA. If we connect the start−up network to both mains
www.onsemi.com
16
NCP12600
v t
DS ( )
v t
DS ( )
Jump from 3−2−3 valleys
Vin = 142 V, Iout = 0.9 A
v t
DS ( )
3rd to 2nd
Figure 34. The multimode engine paces the valley jump event at a controlled rate
Over Power and Over Voltage Protection
During t , the auxiliary winding jumps to the reflected
off
Over Power Protection (OPP) is a known means to limit
the output power excursion at high mains. Several elements
such as propagation delays and operating mode explain why
a converter operated at high line delivers more power than
at low line. NCP12600 implements a proprietary technique
that senses the bulk input voltage via a resistive network
connected to the auxiliary winding. However, as the pin used
for OPP (pin 3) also combines other functions such as
demagnetization detection and OVP, a specific network has
to be designed as shown in Figure 35.
output voltage scaled by the secondary−to−auxiliary
transformer turns ratio. Diode D is conducting and the
1
network R /R sets the OVP voltage. When the power
upp zcd
MOSFET turns on, the auxiliary voltage jumps to a negative
voltage representative of the input voltage. That negative
voltage will be internally subtracted from the peak current
setpoint. An internal 60−mV offset prevents compensation
from taking place at low line.
The positive and negative auxiliary voltages depend on
the transformer turns ratios. We can define them as follows:
N :N = N , the primary to power winding turns ratio
p
s
pow
Rupp
N :N = N , the primary to auxiliary winding turns ratio
p
a
aux
During the off−time, the auxiliary winding jumps to the
following plateau voltage:
.
Aux
winding
D1
BAV21
f1Ǔ Naux
Ropp
+ ǒV
Vaux
out ) V
(eq. 6)
Npow
in which V is the power diode drop at nominal power. That
voltage appears on pin 3 affected by the resistive divider
f1
3
R
/R and D ’s forward drop V :
upp zcd
1 f2
Rzcd
Rzcd
f2Ǔ
Rzcd ) Rupp
ǒ
Vplat + Vaux ) V
(eq. 7)
During the on−time, D is blocked and R now appears
1
opp
Figure 35. Over Power Protection is provided via
the bulk voltage image present on Brown−Out pin
in series with R . The voltage on pin 3 is defined as
upp
www.onsemi.com
17
NCP12600
Slope Compensation
Rzcd
Vpin3
+
NauxVin
(eq. 8)
The NCP12600 includes an internal slope compensation
signal. This is the buffered oscillator clock delivered during
the on−time only. Its amplitude is around 4.2 V at the
maximum duty ratio. Slope compensation is a known means
used to eliminate sub−harmonic oscillations in CCM−
operated current−mode converters. These oscillations take
place at half the switching frequency and occur only during
CCM with a duty ratio greater than 50%. To lower the
current loop gain, one usually injects between 50 and 100%
of the inductor downslope. Figure 36 depicts how internally
the ramp is generated. Please note that the ramp signal will
be disconnected from the CS pin, during the off time.
Rzcd ) Rupp ) Ropp
in which V is the bulk dc voltage. That voltage is the
in
negative OPP voltage we need for our compensation. As
pin3 internally includes a 60−mV offset, the negative
voltage present on pin3 brings a final sense voltage
reduction of
Vsense + 700 mV ) Vpin3 ) 60 m
(eq. 9)
Assume V
= –150 mV during t , thus the effective
on
pin3
sense reduction is
Vsense + 700 mV * 150 m ) 60 m + 610 mV (eq. 10)
The peak current reduction is thus 12.8%. Combining the
4.2 V
above equations lets us calculate the values for R
and
upp
R
opp
based on design requirements:
0V
ǒV
OVPǓ
Naux 1)V
f
(eq. 11)
Rzcd
V
*
f
2
ǒ
Ǔ
Ǔ
Npow
ON
N
auxRzcdVinHL
Ropp
+
+
*
VOVP1
Vopp
latch
reset
20.4 kW
Rcomp
ǒV
OVPǓ
Naux 1)V
+
f
L.E.B
(eq. 12)
Rzcd
* V
f
2
ǒ
CS
Npow
−
Rsense
Rupp
* Rzcd
VOVP1
from FB
setpoint
In these expressions, we have:
R
is the pull−down resistor arbitrarily selected. 1.8 kW
zcd
Figure 36. inserting a resistor in series with the
current sense information brings ramp
compensation and stabilizes the converter in CCM
operation
could be a value to start with (we recommend to select a
resistance below 2 kW for the best linearity in the OPP
compensation)
V
OVP
is the output voltage at which you want the plateau to
reach the threshold voltage V
(3.15 V typical)
NCP12600 oscillator ramp features a 4.2 V swing. If the
clock operates at a 65−kHz frequency, then the available
oscillator slope corresponds to:
OVP1
V
inHL
is the high−line dc voltage measured across the input
bulk capacitor
Assume the following data:
= 19 V, N = 0.250, N = 0.184, V = 0.8 V, V
(eq. 13)
V
D
max
ramp,peak
4.2 @ 0.8
15.4m
S +
ramp
+
+ 341kVńs or 341mVńms
V
out
=
pow
aux
f1
f2
T
sw
0.65 V, V
= 375 V, R = 1.8 kW
inHL
zcd
In our flyback design, assume a primary inductance L of
p
We want an OPP reduction of 12% and an output OVP set
to 25 V. This leads to the following resistor values: R
550 mH. The converter delivers 19 V with a N :N ratio of
p
s
=
upp
1:0.25. The off−time primary current slope S is thus given
p
9.2 kW and R = 851 kW.
opp
by:
Pin3 is also used for demagnetization detection. A small
1ǓN
capacitance can be added in parallel with R to introduce
zcd
S
NP
(eq. 14)
ǒV
) V
out
f
a delay and to exactly turn−on in the drain−source valley.
Experiments show that capacitances up to 150 pF provide
adequate results. Please make sure the negative value during
the on−time is not affected by too large a capacitance.
Pin3 protects the converter against short circuit to ground.
Should you do this during safety tests, the part simply
interprets the shortening to ground as an output short circuit
(
)
19 ) 0.8 4
S
+
+
+ 144 kAńs
P
L
P
550 u
Considering a sense resistor of 330 mW, the above current
ramp turns into a voltage ramp of the following amplitude:
(eq. 15)
S
+ S R
+ 144 k 0.33 [ 47 kVńs or 47 mVńms
sense
sense
P
®
and stops pulsing quickly. Please note that an Excel
If we select 50% of the downslope as the required amount of
compensation, then we shall inject a ramp whose slope is
spreadsheet is available from our product website and
automates the calculation of the above resistances.
www.onsemi.com
18
NCP12600
Feedback
23 mV/ms. Our internal compensation being of 341 mV/ms,
The feedback is done by bringing the FB pin down with
an optocoupler as shown in Figure 37. To maintain a low
consumption current, the resistive network on the FB pin is
higher than in other controllers. As a result, the optocoupler
pole may be located at a lower position. Popular
optocouplers like PC817 or SFH615 exhibit poles in the
3−4 kHz region. For that reason, a simple 100−pF capacitor
connected between the circuit FB and GND pins (located
close to the IC) will ensure local decoupling without
interfering with crossover selection. In the secondary side,
the figure shows a typical application for a 19.5−V output.
This is a type 2 configuration and a single 0.1−mF capacitor
will do the job typically for a fast and non−ringing transient
response.
the divider ratio (divratio) between R
20.4−kW resistor is:
and the internal
comp
23 m
341 m
divratio +
[ 0.067
(eq. 16)
The series compensation resistor value is thus:
(eq. 17)
Rcomp + Rrampdivratio + 20.4 k 0.067 [ 1.4 kW
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small capacitor of 100 pF, from the current sense
pin to the controller ground for an improved immunity to the
noise. Please make sure both components are located very
close to the controller.
Vout
Vdd
19.5 V
R1
40k
R4
1k
R6
56k
buffer
8
14
FB
R8
12k
GAIN
VCO
VCOoutput
1
2
7
9
R5
10k
C1
R2
100pF
135k
C2
0.1uF
10
3
−
PWMrst
6
0.7 V
+
11
R3
R7
5
31k
10k
NCP431
CS
Figure 37. The optocoupler brings the FB pin
down as the NCP431 injects more current into the
LED
The NCP12600 is a multi−mode controller meaning that
several operating modes are possible:
25 kHz. This low−frequency value is reached
when V reaches 1.9 V. When the
FB
1. Continuous conduction mode (CCM) is available
as with any PWM controller. Usually, CCM is
entered at heavy load and low line.
voltage−controlled oscillator (VCO) operates, the
controller also locks in the valley to ensure the
best efficiency. Valley jumping is also likely to
occur here but the controller sets the pace at which
they occur. Of course, nothing prevents from
finding a stable operating point between two
hesitations, this is normal.
2. As output power reduces, the converter leaves
CCM and enters discontinuous conduction mode
(DCM). The controller detects this mode and locks
in the next available valley. The switching
frequency is no longer fixed and is dictated by the
valley jumps. The feedback voltage can be
between its maximum value and 2.4 V in this
quasi−resonant mode. Discrete frequency jumps
occur but are controlled by NCP12600 internal
logic.
4. The load current is very small and the feedback
voltage is below 1.9 V. Frequency is fixed to
25 kHz and classical peak current mode control
operates. When the feedback voltage touches 1 V,
classical or Quiet skip cycle takes place for the
best standby power performance. See below for
detailed operations.
3. If the load current continues to decrease, the
feedback passes below the 2.4−V threshold and
frequency foldback begins. The frequency is
gradually reduced from 65 kHz (or 100 kHz) to
The curve in Figure 38 describes the various operating
stages as feedback varies.
www.onsemi.com
19
NCP12600
F
sw
PWM operation
with fixedFsw
Foldback zone
with jitter
Open-loop
PWM operation
65 kHz
with fixedFsw
25 kHz
P
out
VFB = 3.8 V VFB = 4 V
Vsense
0.7 V
timer starts
VFB = 1.9 V VFB = 2.4 V
VFB <1V
P
out
Full load
Figure 38. The frequency is folded back as output power demands reduces
Dual OCP – Option
the CS pin crosses this first 0.5−V threshold, a timer of
Some applications require the possibility to deliver a peak
power during a certain duration while the rest of the time, the
average power is low. The converter is thus thermally sized
duration t starts. If the power keeps increasing and pushes
1
the peak current to the next 0.7−V sense voltage limit, the
charging current of the timer is multiplied by 4 making the
new timer t equal to t /4. For instance, a typical timer
to cope with a moderate average power (V < 0.5 V) while
CS
2
1
allowing short−duration output power peaks when V
configuration of 256 ms/64 ms lets the converter delivers
CS
touches the 0.7−V limit. The NCP12600 can be configured
in a so−called dual−OCP mode where a second level is
inserted in the current sense circuitry. When the voltage on
power for 256 ms when V hits 0.5 V and this time is
reduced to 64 ms if it directly jumps to 0.7 V during an
overload condition.
CS
F
sw
PWM operation
with fixedFsw
Foldback zone
with jitter
Open-loop
PWM operation
with fixedFsw
65 kHz
25 kHz
P
out
VFB = 3.8 V VFB = 4 V
VFB = 2.7 V
Vsense
0.7 V
0.5 V
64 ms timer starts
256 ms timer starts
VFB = 1.9 V VFB = 2.4 V
VFB <1V
P
out
Intermediate load
Full load
Figure 39. The dual−OCP option sets two timers depending on the amount of delivered current
Quiet−Skip − Option
until this timer has expired. As the output power decreases,
the switching frequency decreases. Once it hits minimum
To further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audible
range by limiting it to a maximum of 800 Hz. This is
achieved via a timer t
Quiet−Skip. The start of the next burst cycle is prevented
switching frequency f , the skip−in threshold is
OSC(min)
reached and burst mode is entered − switching stops as soon
as the current drive pulses ends – it does not stop
immediately.
that is activated during
quiet
www.onsemi.com
20
NCP12600
Once switching stops, FB will rise. As soon as FB crosses
the skip−exit threshold, drive pulses will resume but the
expires, the drive pulses will wait for the skip−exit
threshold.
controller remains in burst mode. At this point, a 1250 ms
This means that during no−load, there will be a minimum
(typ) timer t
is started together with a count to n
of n
drive pulses, and the burst−cycle period will likely
quiet
P,skip
P,skip
pulses counter. This n
minimum number of DRV signal pulses in burst. The next
time the FB voltage drops below the skip−in threshold, DRV
pulses counter ensures the
be much longer than 1250 ms. This operation helps to
improve efficiency at no−load conditions.
In order to exit burst mode, the FB voltage must rise higher
P,skip
pulses stop at the end of the current pulse as long as n
than V
level. If this occurs before t
expires, the
P,skip
skip(tran)
quiet
drive pulses have been counted (if not, they do not stop until
the end of the n −th pulse). They are not allowed to start
again until the timer expires, even if the skip−exit threshold
is reached first. It is important to note that the timer will not
force the next cycle to begin – i.e. if the natural skip
frequency is such that skip−exit is reached after the timer
drive pulses will resume immediately – i.e. the controller
won’t wait for the timer to expire. Figure 40 provides an
example of how Quiet−Skip works, while Figure 41 shows
P,skip
the immediate escape from Quiet−Skip if V crosses the
FB
transient level V
.
skip(tran)
V FB
Vskip(out)
Vskip(in)
time
Running just above skip
mode with fsw = fosc(min)
DRV
Sequence of events
1; 2; 3 starts the quiet
skip mode
The DRV pulses does not
start even when VFB > V skip(out)
in the quiet skip mode
V FB
2
V skip(out)
Vskip(in)
1
3
time
DRV
t quiet
t quiet
nP ,skip
nP ,skip
When VFB > Vskip(tran) the quiet skip
mode immediately finishes
V FB
Vskip(tran)
V skip(out)
Vskip(in)
time
DRV
tquiet
tquiet
nP ,skip
nP ,skip
nP ,skip
Quiet skip mode
forces at least np,skip
pulses in skip mode
burst
DRV pulses does
not start because
VFB < V skip(in)
Figure 40. Leaving the Quiet−Skip Mode during Load Transient
VFB
Vskip(tran)
Crossing the transient
enhancement level
stops the quiet skip
immediatelly
Vskip(out)
Vskip(in)
Exits skip
after quiet
timer
expires
DRV
tquiet
tquiet
Enters
skip
Enters
skip
Time
Figure 41. Quiet−skip Timing Diagram
www.onsemi.com
21
NCP12600
Over Temperature Protection
ǒ
2Ǔ
Rramp Vaux * Vf
It is possible to trip a second protection via the CS pin. If
you connect a NTC resistor from the auxiliary winding
through a fast diode and a series resistance, it is possible to
latch off the part (or make it auto−recover depending on the
selected option) at the desired temperature. Figure 42 shows
the adopted principle. The auxiliary winding jumps to the
ROTP
+
* Rramp * RNTC (eq. 19)
VOTP
A very popular NTC model is the TT3 series. Assume we
have selected a device exhibiting a 470−kW resistance at
25°C. When the temperature reaches 110°C, this resistance
drops to 8.8 kW typically. Statistical analysis show that a
good precision can be obtained as long as the ramp
resistance is of moderate value. Here, experiments show that
a 1−kW resistance is a good fit to the application and leads
output voltage reflected to the primary side during t and
off
described by (6) If the loop is well designed, i.e. with
sufficient loop gain in dc, the precision of this available
voltage can be very good. As this voltage is available during
the off−time, we can use it to build a temperature−dependent
voltage on the CS pin and compare the value to an internal
precise 1−V reference. According to Figure 42 labels, the
to the following R
calculation:
OTP
(
)
1 k 14 * 0.35
ROTP
+
* 1 k * 8.8 k + 4.1 kW (eq. 20)
1
The NCP12600 reference voltage V
3% across the entire temperature range while all resistors
are 1%. The auxiliary plateau is estimated to a 5%
is guaranteed at
OTP
voltage at the CS pin during t equals
off
Rramp
ǒ
2Ǔ
Rramp ) RNTC ) ROTP
VCS + Vaux * Vf
(eq. 18)
precision. The V of the series diode can be calibrated at the
f
trip point to refine calculations but if the auxiliary winding
is of large amplitude, its contribution to the final error
remains small.
The ramp resistor R
operating mode at low line while R
is selected depending on the
ramp
must be calculated
OTP
as
BAV21
.
ROTP
RNTC
Rramp
OTP
CS
+
−
Rsense
VOTP
DRV
Figure 42. The NTC lifts the CS pin voltage during the off−time. If the voltage exceeds 1 V, all pulses stop
200
We can estimate what the final spread will be in the
temperature trip point by assigning uniform distributions to
each of the parameters. The resulting curve shown in
Figure 43 indicates that an NTC resistance varying between
150
7.6 kW and 10 kW will trip the controller in OTP.
ƴ Ƶ
1
R
100
50
NTCdisti
3
3
3
4
4
7⋅ 10
8 ⋅ 10
9 ⋅10
1⋅ 10
1.1⋅ 10
ƴ Ƶ
0
R
NTCdisti
RNTC = 7.6kW
RNTC =10kW
Figure 43. By assigning precision to the various
components, it is possible to calculate the OTP trip
point dispersion
www.onsemi.com
22
NCP12600
If we now look at the corresponding temperatures the
converter requires less slope compensation (light CCM
operation) or works exclusively in DCM.
NTC resistance varying between these two limits
correspond to, we obtain a range between 116 and 104°C.
Centered at 110°C, it gives a theoretical precision of 5.4°C.
It is possible to improve the precision by removing the
Latched Mode
When the part latches off in OVP or OTP (or even in an
OCP condition if the option is selected), the part
immediately stops pulsing and activates an internal 1−mA
R
resistor. That element is inserted because the ramp
OTP
resistance is imposed before the OTP calculation. Now
assume that you remove R and calculate R to match
current source. This source brings V quickly to the UVLO
cc
OTP
ramp
level +100 mV and a fast hiccup around UVLO starts. That
way, if the user cycles the input source, reset occurs at a
quicker pace. Figure 44 shows a typical waveform inherent
to this proprietary techniques.
the 1−V trip point when R
= 8.8 kW. In our example,
NTC
R
would be 680 W. Considering a 2−element divider
ramp
versus 3 as originally selected, then the dispersion would
narrow down to 8 kW − 9.6 kW, leading to a temperature trip
point of 110°C 4.5°C. Something worth considering if the
vCC
t
( )
1−mA source
is on
1−mA source
is off
vDS
t
Fast hiccup
( )
Figure 44. when the controller latches off, the Vcc is quickly discharged
to the fast hiccup level, authorizing a fast reset
Please note that another OVP is installed on the V pin
and monitors the dc value permanently biasing the pin. If
latches off or auto−recovers depending on the selected
option.
cc
that voltage exceeds V
typically set at 25 V the part
OVP2
www.onsemi.com
23
NCP12600
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
PLANE
M
C
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
L
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0°
10°
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
0.95
3.20
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
◊
NCP12600/D
相关型号：
NCP1271D100R2G
Soft−Skip Mode Standby PWM Controller with Adjustable Skip Level and External Latch
ONSEMI
NCP1271D65R2G
Soft−Skip Mode Standby PWM Controller with Adjustable Skip Level and External Latch
ONSEMI
NCP1271P100G
Soft-Skip Mode Standby PWM Controller with Adjustable Skip Level and External Latch
ONSEMI
©2020 ICPDF网 联系我们和版权申明