NCP12700 [ONSEMI]
Startup Regulator Circuit with 15 mA Capability;
| 型号： | NCP12700 |
| 厂家： | 
ONSEMI |
| 描述： | Startup Regulator Circuit with 15 mA Capability |
| 文件： | 总20页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP12700
Ultra Wide Input Current
Mode PWM Controller
The NCP12700 is a fixed frequency, peak current mode, PWM
controller containing all of the features necessary for implementing
single−ended power converter topologies. The device features a high
voltage startup capable of operating over a wide input range and
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supplying at least 15 mA to provide temporary bias to V during
CC
system startup. The device contains a programmable oscillator
capable of operating from 100 kHz to 1 MHz and integrates slope
compensation to prevent subharmonic oscillations. The controller
offers an adjustable soft−start, input voltage UVLO protection, and an
adjustable Over−Power Protection circuit which limits the total power
capability of the circuit as the input voltage increases, easing the
system thermal design. The UVLO pin also features a shutdown
comparator which allows for an external signal to disable switching
and bring the controller into a low quiescent state.
1
WQFN10
MT SUFFIX
CASE 511DV
MSOP
DN SUFFIX
CASE 846AE
MARKING DIAGRAMS
The NCP12700 contains a suite of protection features including
cycle−by−cycle peak current limiting, timer−based overload
protection, and a FLT pin which can be interfaced with an NTC and an
auxiliary winding to provide system thermal protection and output
over−voltage protection. All protection features place the device into a
low quiescent fault mode and recovery from fault mode is dependent
on the device option.
12700x
ALLYWG
G
10
1
700x
AYW
Common General Features
• Wide Input Range (9 – 120/200 V; MSOP10/WQFN10)
• Startup Regulator Circuit with 15 mA Capability
• Current Mode Control with Integrated Slope Compensation
• Suitable for Flyback or Forward Converters
• Single Resistor Programmable Oscillator
• 1 A / 2.8 A Source / Sink Gate Driver
• User Adjustable Soft−Start Ramp
• Input Voltage UVLO with Hysteresis
• Shutdown Threshold for External Disable
• Skip Cycle Mode for Low Standby Power
• This is a Pb−Free Device
12700 or 700 = Specific Device Code
x
A
LL
YW
G
= A or B
= Assembly Site
= Wafer Lot Number
= Assembly Start Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Fault Protection Features
Typical Applications
• User Adjustable Over−Power Protection
• Overload Protection with 30 ms Overload Timer
• NTC−Compatible Fault Interface for Thermal
Protection
• Single−ended Power Converters including CCM/DCM
Flyback and Forward Converters
• Telecommunications Power Converters
• Industrial Power Converter Modules
• Transportation & Railway Power Modules
• Output OVP Fault Interface
• Fault Auto−recovery Mode with 1 s Auto−recovery
Period
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
June, 2018 − Rev. 0
NCP12700/D
NCP12700
VOUT
VIN
UVLO VIN
FLT VCC
SS
RT
DRV
GND
COMP CS
FEEDBACK
WITH
ISOLATION
Figure 1. Typical Application Circuit for Vin = 12 − 160 V
VIN
VOUT
UVLO VIN
FLT VCC
SS
DRV
RT GND
COMP CS
FEEDBACK
WITH
ISOLATION
Figure 2. Typical Application Circuit for Vin = 9 − 18 V
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2
NCP12700
V
CC
HV Startup
VIN
C
CC
VCCON
VCC(OVP)
INTERNAL
REGULATOR
VCC
LOGIC
VCC(UVLO)
VDD VDRV
Regulation
GND
Over−Power
Protection
I
CS(OPP)
VCCON
ENABLE
FAULT
START
MAIN
LOGIC
STOP
SHDN
VDD
UVLO
UVLO
Detection
I
ENABLE
SS
I
UVLO(HYS)
START
SS
CONTROL
SS_END
SS
TSD
TSD
V
SS
START
OSC
D
MAX
VDD
RT
I
FLT
CLK
FAULT
TSD
SS_END
FLT
FAULT
Logic
SHDN
OVLD
VDD
VCC(OVP)
I
CS(OPP)
VCC(UVLO)
D
MAX
LEB
Block
STOP
CS
OVLD
Slope
Comp
DRV
VDD
5k
VDRV
CLK
S
PWM
COMP
LOGIC
1/6
DRV
Q
R
V
COMP(skip)
V
COMP(skip_hys)
V
SS
1/6
Figure 3. Block Diagram
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3
NCP12700
PINOUTS
UVLO
FLT
SS
RT
COMP
VIN
VCC
DRV
GND
CS
DRV
GND
CS
UVLO
FLT
EP
(Top Views)
Table 1. PIN FUNCTION DESCRIPTION
MSOP10
WQFN10
Pin Name
Pin Description
1
9
UVLO
The UVLO pin is the input to the Standby and UVLO comparators. A resistor divider between
the power supply input voltage and ground is connected to the UVLO pin to set the input volt-
age level at which the controller will be enabled. UVLO Hysteresis is set by a 5 mA pull−down
current source. An externally supplied pull−down signal can also be used to disable the con-
troller. The UVLO pin is also used to determine the Over−Power Protection current supplied to
the CS pin.
2
10
FLT
SS
The FLT pin is the input to a window comparator which provides an upper and lower fault
threshold. When either threshold is tripped, the controller enters the fault mode which can be a
permanent latch off or a minimum 1 s auto−recovery period. A precision current source is out-
put from the FLT pin allowing an NTC to ground to be placed at the pin for system Over−tem-
perature protection. The upper threshold can be used for output over−voltage protection
sensed through the auxiliary winding or as a general purpose fault.
3
1
The SS pin sets the soft−start ramp of the peak current limit when the controller is enabled. An
internal 15 mA current source and an external capacitor to ground are used to control the ramp
rate. Typical soft start capacitor values will be in the range of 10 nF to 100 nF.
4
5
2
3
RT
The RT pin sets the oscillator frequency in the controller. This pin requires a resistor to ground
located close to the IC. Typical RT values are in the range of 10 kW – 100 kW.
COMP
The COMP pin provides the compensated error voltage for the PWM and Skip comparators.
An internal 5 kW pull−up resistor is connected to the COMP pin and can be used to bias the
transistor of an opto−coupler.
6
4
CS
The CS pin is the current sense input for the PWM and Current Limit comparators. The com-
parator input is held low for 60 ns after the DRV goes high to prevent leading edge current
spikes from tripping the comparators. An external low pass filter is recommended for improved
noise immunity. The external filter resistor is also used to determine the amount of Over−Pow-
er Protection applied to the current sense.
7
8
5
6
7
8
GND
DRV
VCC
VIN
This pin is the controller ground. For the WQFN package the exposed pad (EP) should be
connected to GND.
The DRV pin is a high current output used to drive the external MOSFET gate. DRV has
source and sink capability of 1 A and 2.8 A, respectively.
9
The VCC pin provides bias to the controller. An external decoupling capacitor to ground in the
range of 1 – 10 mF is recommended.
10
The VIN pin is the input to the high voltage startup regulator. The regulator is capable of sourc-
ing > 15 mA to temporarily bias VCC while the application is starting up.
ORDERING INFORMATION
Device
†
Package
MSOP10
MSOP10
WQFN10
OTP Fault
Latch
OVP Fault
Latch
Shipping
NCP12700ADNR2G
NCP12700BDNR2G
NCP12700BMTTXG
4000 / Tape & Reel
4000 / Tape & Reel
3000 / Tape & Reel
Autorecovery
Autorecovery
Autorecovery
Autorecovery
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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4
NCP12700
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
High Voltage Startup Voltage
(MSOP10)
(WQFN10)
V
120
200
V
IN(MAX)
High Voltage Startup Current
Supply Voltage
I
50
−0.3 to 30
50
mA
V
IN(MAX)
CC(MAX)
CC(MAX)
V
Supply Current
I
mA
V
DRV Voltage (Note 1)
DRV Current (Peak)
FLT Voltage
V
−0.3 V to V
DRV(high)
DRV(MAX)
DRV(MAX)
I
3.25
+ 1.25
CC
A
V
V
V
FLT(MAX)
FLT Current
I
10
mA
V
FLT(MAX)
Max Voltage on Signal Pins
Max Current on Signal Pins
V
−0.3 to 5.5
10
SIG(MAX)
SIG(MAX)
I
mA
°C/W
Thermal Resistance Junction−to−Air (Note 2)
(MSOP10)
(WQFN10)
R
165
51
θ
J−A
Junction−to−Top Thermal Characterization Parameter
(MSOP10)
(WQFN10)
Y
J−C
10
12
°C/W
Maximum Junction Temperature
Maximum Power Dissipation
T
150
°C
JMAX
(MSOP10)
(WQFN10)
P
D
Internally Limited
W
Storage Temperature Range
Operating Temperature Range
ESD Capability (Note 3)
T
−55 to 150
−40 to 125
°C
°C
V
STG
T
J
Human Body Model per JEDEC Standard JESD22−A114E
Charge Device Model per JEDEC Standard JESD22−C101E
2000
1000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, V
, when V
DRV(high)
exceeds the driver clamp voltage. Otherwise, the
CC
maximum driver voltage is V
.
CC
2. Per JEDEC specification JESD51.7 using two 1 oz copper planes with board size = 80x80x1.6 mm
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Charge Device Model TBD per JEDEC Standard JESD22−C101E
4. This device contains latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +/−100 mA (TBD).
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
VIN Voltage
(MSOP10)
(WQFN10)
V
IN
9 – 100
V
12 – 160
Supply Voltage − All
V
CC
9 – 20 V
V
Operating Temperature Range
T
J
−40 to 125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NCP12700
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V = 12 V, V
= Open, V
= Open, C
= 1 nF, R = 49.9k V
IN
CC
COMP
FLT
DRV T , CS
= 0 V, V = Open, V
= 1.2, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
SS
UVLO
J
J
Characteristics
HIGH VOLTAGE STARTUP REGULATOR
Regulated Voltage
Test Condition
Symbol
Min
Typ
Max
Unit
V
V
= Open, I = 5 mA
V
7.6
15
8
8.4
V
CC
CC
CC(REG)
Current Source Capability
Current Source Limit
V
= 9 V, V = 7 V
I
mA
mA
mA
mA
IN
CC
VIN(SRC)
= V
+ 100 mV
I
30
CC
CC(off)
VIN(LIM)
VIN(OFF)
VIN(OFF)
Off−State Leakage Current (xMTTXG)
Off−State Leakage Current (xDNR2G)
SUPPLY CIRCUIT
V
= Open, V = 160 V, V
= 0
= 0
I
I
100
100
CC
IN
UVLO
UVLO
V
= Open, V = 120 V, V
IN
CC
Supply Voltage
V
Startup Threshold
V
increasing
decreasing
V
V
V
–
V
–
CC
CC(on)
CC(REG)
350 mV
CC(REG)
100 mV
Minimum Operating Voltage
V
CC
6.2
6.5
28
3
6.8
CC(off)
Supply Over−Voltage Protection
VCC OVP Detection Filter Delay
V
V
CC(OVP)
t
ms
VCCOVP
(DLY)
Startup Delay
Measured from V
to SS
= 2 V
t
25
ms
CC(ON)
ON(Dly)
Supply Current
SHDN
V
UVLO
= 0 V
I
−
−
−
−
−
−
−
−
50
750
4
mA
mA
mA
mA
CC(SHDN)
STBY
V
UVLO
= 0.7 V
I
CC(STBY)
Enable
C
= Open, V
I
DRV
COMP
CC(EN)
Fault
V
FLT
= 0 V
I
500
CC(FLT)
CURRENT SENSE
Current Limit Comparator Threshold
V
465
−
495
−
525
75
mV
ns
CS(LIM)
t
CS(DLY)
Propagation Delay From Current
Sense Limit to DRV Low
Step V from 0 – 0.6 V
CS
Short Circuit Protection (SCP) Current
Limit Threshold
V
625
−
mV
ns
SCP(LIM)
Propagation Delay From Short Circuit
Limit to DRV Low
V
V
= 0.75 V
= 0.75 V
t
−
75
CS
SCP(DLY)
Short Circuit Counter
N
4
100
60
−
CS
SCP
CS Leading Edge Blanking (LEB)
SCP Leading Edge Blanking
CS LEB Pull−down Resistance
Overload Timer Duration
t
75
45
125
75
ns
ns
LEB(CS)
t
LEB(SCP)
R
55
W
PD(LEB)
V
= 0.6 V
t
24
83
30
102
36
ms
mV
CS
CS(OVLD)
Applied Slope Compensation @ Cur-
rent Limit Comparator
V
COMP
= Open; Measured at D
V
SLP(ILIM)
123
80%
Duty Cycle Where Slope Compensat-
ing Ramp Begins
D
40
6
%
40%
COMP SECTION
PWM to COMP Gain Through Resistor
Divider
V
COMP
= 2 V
K
PWM
PWM Propagation Delay to DRV Low
COMP Open Pin Voltage
COMP Output Current
V
COMP
= 2 V, Step from CS 0– 0.4 V
t
−
4.7
1
75
ns
V
PWM(Dly)
V
4
COMP(open)
V
COMP
= 0
I
0.84
76
1.2
84
mA
%
COMP
Maximum Duty Cycle
V
COMP
= Open
D
80
300
MAX
COMP(skip)
COMP Skip Threshold
V
mV
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6
NCP12700
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V = 12 V, V
= Open, V
= Open, C
= 1 nF, R = 49.9k V
IN
CC
COMP
FLT
DRV T , CS
= 0 V, V = Open, V
= 1.2, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
SS
UVLO
J
J
Characteristics
COMP SECTION
Test Condition
Symbol
Min
Typ
Max
Unit
COMP Skip Hysteresis
V
25
mV
COMP
(skip_hys)
Minimum Duty Cycle
V
COMP
= 0
D
0
%
MIN
Applied Slope Compensation @ PWM
Comparator
V
COMP
= 2 V; Measured at D
V
77
98
117
mV
80%
SLP(PWM)
SOFT START
Soft−Start Open Pin Voltage
Soft−Start End Threshold
Soft−Start Current
V
5.0
3
V
V
SS(open)
V
2.85
12
3.15
18
SS(end)
V
SS
= 3 V
I
SS
15
6
mA
Soft−Start to CS Divider
Soft−Start Discharge Resistance
OSCILLATOR
K
SS
SS(DIS)
R
100
W
Oscillator Frequency 1
Oscillator Frequency 2
Oscillator Frequency 3
Oscillator Frequency 4
UNDER−VOLTAGE LOCKOUT (UVLO)
Standby Threshold
F
185
95
200
100
215
105
550
kHz
kHz
kHz
kHz
OSC1
OSC2
OSC3
OSC4
R = 100 kW
F
T
R = 20 kW
T
F
F
450
500
R = 9.09 kW
T
1000
V
increasing
decreasing
decreasing
V
0.35
0.3
0.5
0.45
50
0.65
0.6
V
V
UVLO
STBY(th)
Reset Threshold
V
V
V
UVLO
UVLO
RST(th)
STBY(HYS)
STBY(DLY)
Standby Hysteresis
V
mV
ms
Standby Detection RC Filter
UVLO Threshold
t
5
V
increasing
decreasing
V
765
800
15
830
mV
mV
mA
ms
UVLO
UVLO(th)
UVLO Threshold Hysteresis
UVLO Hysteresis Current
UVLO Detection Delay Filter
OVER−POWER PROTECTION (OPP)
V
V
UVLO
UVLO(HYS)
UVLO(HYS)
I
4.5
0.5
5
5.5
1
V
= V
− 20 mV
t
UVLO(DLY)
UVLO
UVLO(th)
UVLO Voltage Above Which OPP Ap-
plied
V
1
V
OPP(START)
OPP Gain
Gm
135
180
150
200
200
165
220
mA / V
mA
(OPP)
I
CS(OPP1)
Maximum Current (Operating Point)
Maximum Current
V
= 2.33 V
UVLO
V
= 4 V
I
mA
UVLO
CS
(OPP_MAX)
COMP Threshold Voltage Above Which
OPP is Applied
V
0.8
2
V
V
OPP(0%)
COMP Threshold Voltage For 100%
OPP
V
OPP(100%)
GATE DRIVE
DRV Rise Time
V
V
= 1.2 V to 10.8 V
= 10.8 V to 1.2 V
t
6
10
4
15
10
ns
ns
A
DRV
DRV(rise)
DRV Fall Time
t
2.5
DRV
DRV(fall)
DRV(SRC)
DRV(SNK)
DRV(clamp)
DRV Source Current
DRV Sink Current
DRV Clamp Voltage
V
= 6 V
= 6 V
I
I
1.0
2.8
12
DRV
DRV
V
A
V
= 20 V, R
= 10 kW
V
10
14
V
CC
DRV
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7
NCP12700
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V = 12 V, V
= Open, V
= Open, C
= 1 nF, R = 49.9k V
IN
CC
COMP
FLT
DRV T , CS
= 0 V, V = Open, V
= 1.2, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
SS
UVLO
J
J
Characteristics
GATE DRIVE
Test Condition
Symbol
Min
Typ
Max
Unit
Minimum DRV Voltage
V
CC
= V
+ 100 mV,
V
6
V
CC(OFF)
DRV(MIN)
R
= 10 kW
DRV
FAULT PROTECTION
Fault Source Current
I
80
0.47
10
85
0.5
20
0.9
3
90
0.53
30
mA
V
FLT
OTP Fault Threshold
V
FLT(OTP)
OTP(DLY)
OTP Detection Filter Delay
OTP Fault Recovery Threshold
OVP Fault Threshold
t
ms
V
V
V
0.846
2.8
0.954
3.2
FLT(REC)
FLT(OVP)
OVP(DLY)
V
OVP Detection Filter Delay
Fault Clamp Voltage
t
3
5
7
ms
V
V
FLT
= Open
V
1.13
1.35
1.6
1
1.57
FLT(CLAMP)
FLT(CLAMP)
Fault Clamp Resistance
Auto−recovery Timer
R
kW
s
t
0.8
1.2
AR
THERMAL SHUTDOWN
Thermal Shutdown
T
150
165
25
180
°C
°C
SHDN
Thermal Shutdown Hysteresis
T
SHDN(hys)
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8
NCP12700
Application Information
The NCP12700 is a fixed frequency, peak current mode,
Figure 4 details the operation of the startup regulator.
When VIN is applied, the regulator will immediately begin
PWM controller containing all of the features necessary for
implementing single−ended power converter topologies.
The device features an ultra−wide range, high voltage
sourcing current to charge V . Initially the startup will
CC
supply approximately 10 mA. Once V builds up to ~ 3 V,
CC
startup regulator capable of regulating V across an input
the control loop for the HV regulator will activate and the
CC
voltage range of 9 – 120 V (xDNR2G) or 9 – 200 V
(xMTTXG). The controller is designed for high speed
operation including a programmable oscillator capable of
operating from 100 kHz to 1 MHz and total propagation
delays less than 75 ns in the PWM path. The NCP12700
integrates slope compensation to prevent subharmonic
source current will be regulated to 30 mA until V reaches
CC
the V
level of 8 V. The HV startup is a linear
CC(REG)
regulator which can continue to supply and regulate V at
CC
8 V. The recommended V capacitance to ensure stability
CC
of the regulator is 1 – 10 mF.
While the V voltage is below the V
threshold the
CC
CC(ON)
oscillations and an Input Voltage Compensation
/
controller will remain in a low quiescent state to allow for
rapid charging of V and fast startup of the application.
Over−Power Protection (OPP) feature that limits the
converter power delivery capability across input voltage,
easing system thermal design. The controller offers an
adjustable soft−start, input voltage UVLO protection, and a
suite of protection features including cycle−by−cycle
current limit and a FLT pin with a NTC interface for system
thermal protection. The UVLO pin also features a shutdown
comparator which allows for an externally applied
pull−down signal to disable switching and bring the
controller into a low quiescent state.
CC
Once the V
approximately 200 mV below the V
voltage reaches the V
threshold,
level, the
CC
CC(ON)
CC(REG)
controller will exit the low quiescent state and begin
delivering drive pulses. While the output voltage is building
up, the startup regulator will continue to supply the current
necessary to maintain V at the V
level. For low
CC
CC(REG)
input voltage applications, the startup regulator has been
designed to guarantee a minimum of 15 mA source
capability with 2 V of headroom.
In typical applications an auxiliary winding will be used
Ultra−Wide Range HV Startup Regulator
to provide bias to V once the converter is switching. This
CC
The NCP12700 features a high voltage startup regulator
capable of operating across input voltage ranges of 9−120 V
(xDNR2G) or 9−200 V (xMTTXG). The ultra−wide range
capability of the regulator allows for direct connection of
VIN to the converter input voltage without requiring
external components. The regulator’s input voltage
capabilities support a wide range of industrial, medical,
telecom, and transportation applications.
allows for the most efficient operation of the system. Once
the auxiliary winding pulls the V
voltage above
CC
V , the HV regulator will shut off. In normal
CC(REG)
operation the V voltage can be biased above the voltage
CC
at VIN and can support voltages up to 28 V. A V OVP
CC
protection feature will trigger at 28 V, disabling switching of
the converter to prevent the auxiliary winding voltage from
damaging the controller.
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9
NCP12700
V
CC
V
= 12 V
IN
V
CC(REG)
V
CC(ON)
V
CC(OFF)
V
= 3 V
CC
Output
Voltage
I
VIN
I
= 30 mA
= I
VIN
I
VIN CC
I
~ 10 mA
VIN
time
Figure 4. Startup Timing Diagram
Once the device has begun delivering drive pulses it will
remain active as long as V remains above the V
When input voltage is initially applied to the converter the
device will be in a shutdown/reset (SHDN) state until the
CC
CC(OFF)
threshold of 6.5 V. Either the auxiliary winding or the HV
UVLO voltage crosses the V
threshold of 0.5 V. In
STBY(th)
startup regulator will provide the bias necessary to keep V
the SHDN state the device consumption will be limited to
the I value of 50 mA. When the UVLO voltage goes
CC
above this level. If V does drop below the V
CC
CC(OFF)
CC(SHDN)
threshold the controller will inhibit drive pulses, the device
will reset and once again enter a low quiescent state. This
should only occur if the input voltage to the converter has
been removed but can also be an indication of excessive
above V
the device transitions into standby mode
STBY(th)
and the consumption increases to the I
750 mA maximum. The low current consumption in the
shutdown and standby modes allow V to rapidly charge
limit of
CC(STBY)
CC
external loading on V
.
to the V
threshold.
CC
CC(ON)
Once V has charged to V
drive pulses when the UVLO voltage exceeds the V
the device will enable
CC
CC(ON)
Input Voltage UVLO Detection
UVLO(th)
The NCP12700 features line voltage UVLO detection to
ensure that the converter becomes operational only after
meeting a minimum input voltage threshold thereby
protecting the converter from thermal stress at low input
voltages. A functional block diagram of the UVLO
detection circuitry is shown in Figure 5. The input line
voltage is monitored through a resistor divider network
allowing the user to set the thresholds for when to enable and
disable the converter. Typical pull−down resistors in the
divider network will be in the range of 5 – 20 kW and pull−up
resistors will typically be in the range of 50 – 500 kW.
External capacitive filtering on the order of 10 nF is also
advisable.
of 0.8 V and disables drive pulses when the UVLO voltage
falls below 0.8 V by V . Prior to enabling drive
UVLO(HYS)
pulses the device also activates a pull−down current source,
, of 5 mA. The current source works in
I
UVLO(HYS)
combination with V
to set the input voltage
UVLO(HYS)
hysteresis for enabling and disabling switching operation of
the converter. A resistor, R , can be used to
UVLO(HYS)
provide additional hysteresis between the enable and disable
thresholds. Equation 1 and Equation 2 can be used to
calculate the necessary component values in the resistor
divider network.
www.onsemi.com
10
NCP12700
5 ms
S
R
Q
Q
STBY
SHDN
V
STBY(th)
V
IN
V
RST(th)
R
UVLO1
V
R
UVLO(th)
UVLO(HYS)
UVLO
ENABLE
I
UVLO(HYS)
R
UVLO2
Figure 5. UVLO Block Diagram
RUVLO1RUVLO2
RUVLO1 ) RUVLO2
RUVLO1 ) RUVLO2
) ǒ
Ǔ
ǒ
Ǔ
VIN,START
+
ǒ
VUVLO(th)
) RUVLO(HYS) IUVLO(HYS)
Ǔ
(eq. 1)
(eq. 2)
RUVLO2
RUVLO1 ) RUVLO2
ǒ
Ǔ
ǒ
Ǔ
VIN,STOP + VUVLO(th) * VUVLO(HYS)
RUVLO2
Input Voltage Compensation / Over−Power Protection
2
P + 0.5 L I P * I2 fSW
input line voltage through the UVLO pin. When the UVLO
voltage crosses the V threshold, typically 1 V, the
OTA begins sourcing a current out of the CS pin. The current
injected out of the CS pin will be according to Equation 4
ǒ
Ǔ
(eq. 3)
V
OPP(START)
In a CCM flyback converter the output power capability
is defined by Equation 3 where I is the peak transformer
current, I is the valley or minimum transformer current, L
P
V
where the typical transconductance, G
, is 150 mA/V
m(OPP)
is the primary inductance, and f is switching frequency.
SW
and the maximum current is limited to the I
CS(OPP_MAX)
In a DCM flyback converter the valley current becomes 0
and Equation 3 still applies. The peak current capability of
the converter can be impacted by several variables including
input voltage and the operating duty cycle due to the internal
slope compensation in the NCP12700. Managing the peak
current limit over the operating input voltage range will limit
the total power capability and ease system thermal design.
The NCP12700 features the Input Voltage Compensation
/ Over−Power Protection (OPP) circuitry shown in Figure 6.
The Over−Power Protection circuit functions as a
transconductance amplifier which senses an image of the
value of 200 mA.
ǒ
Ǔ
(eq. 4)
ICS(OPP) + Gm(OPP) @ VUVLO * VOPP(START)
Good SMPS design practice for current mode control
includes a small RC filter in series between the current sense
resistor and the CS pin of the controller. Typical values for
the resistor in the RC filter are 500 – 1 kW. The user can then
limit the peak current capability of the converter by setting
the R resistor value and can reduce the peak current
CS
capability of the converter by 20 – 40% with these values.
V
IN
V
DD
R
R
UVLO1
UVLO
COMP
DRV
R
CS
V
CS
I
CS(OPP)
OPP(START)
UVLO2
C
CS
R
SNS
Figure 6. Over−Power Protection Diagram
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11
NCP12700
Another aspect of the Over−Power Protection feature is
that the current sourced out of the CS pin is modulated as a
function of the COMP voltage to ensure that the current is
only available when necessary. This is detailed in Figure 7
V
= 2 V. The typical values of 0.8 V and 2 V equate
OPP(100%)
to ~ 27% and 67% of the full load capability of the device,
hence the OPP current should begin being applied at 27%
load and should ramp up to 100% OPP current at 67% load.
below with typical values for V
= 0.8 V and
OPP(0%)
V
COMP
2 V
0.8 V
I
CS(OPP)
100%
0
time
Figure 7. OPP Current Profile vs. COMP Voltage
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12
NCP12700
PWM Operation
RT Pin & Oscillator
where F
is the switching frequency. The curve in
OSC
Figure 8 below shows the Oscillator frequency vs. RT
resistor for values between ~10 kW to 100 kW. The
NCP12700 is designed to operate between 100 kHz and
1 MHz but will have tighter tolerance at lower switching
frequencies.
The oscillator in the NCP12700 uses an external resistor
from the RT pin to ground to set the switching frequency of
the converter. The frequency set by the RT resistor follows
1
FOSC
+
(eq. 5)
RT 100 10−12
1,000
900
800
700
600
500
400
300
200
100
0
0
10
20
30
40
50
RT Resistor Value (kΩ)
60
70
80
90
100
Figure 8. Oscillator Frequency vs. RT Resistor Value
PWM Reset Path
Gate Driver (DRV)
The NCP12700 is equipped with a gate driver for driving
the primary side MOSFET. The driver applies V up to the
The NCP12700 is intended for isolated DC−DC
converters where the control loop compensation circuitry is
located on the secondary side of the power converter. The
converter output voltage is compared against a reference
voltage and an error amplifier produces a compensated error
signal which is communicated to the NCP12700 through an
optocoupler. The compensated error signal interfaces with
the COMP pin where it is divided down by a 5R/R voltage
divider and sent to the PWM S/R to modulate the switching
duty cycle. A detailed functional diagram of the PWM path
is shown in Figure 9. The PWM comparator compares the
attenuated error signal from the COMP pin to the current
ramp signal sensed at the CS pin to determine when the drive
pulse should be terminated. This comparator serves as the
primary modulation path for the converter duty cycle.
CC
clamped voltage, V , of 12 V as a high signal and
DRV(clamp)
0 V to the gate of the power MOSFET as a low signal. The
rate of charging and discharging of the gate of the MOSFET
is dependent upon the input capacitance of the MOSFET and
the impedance of the driver. The NCP12700 is equipped
with an I
pull−up current, typically 1 A, and a pull
DRV(SRC)
down current of I , typically 2.8 A ensuring fast
DRV(SNK)
turn on/off transitions of the power MOSFET and
minimizing the switching losses.
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13
NCP12700
SCP
COMPARATOR
V
SCP(LIM)
N
SCP
Counter
SCP
VDD
I
t
LEB(SCP)
CS(OPP)
SLOPE
COMPENSATION
CS
t
CS(OVLD)
OVLD
DRV
V
LEB
CURRENT LIMIT
COMPARATOR
CS(LIM)
VDD
I
t
LEB(CS)
SS
SCP
D
MAX
CLK
S
R
Soft−Start
COMPARATOR
Q
SS
PWM
LOGIC
Switching Disabled
DRV
1/6
SLOPE
COMPENSATION
VDD
5k
PWM
COMPARATOR
5R
COMP
R
SKIP
COMPARATOR
V
COMP(skip)
V
COMP(skip_hys)
Figure 9. NCP12700 PWM Path
DRV
V
PWM
V
SLP
0
D
40%
D
80%
Figure 10. Slope Compensation Timing Diagram
Slope Compensation
sub−harmonic oscillation the NCP12700 implements an
internal slope compensation circuit which is applied to the
attenuated COMP signal at the input of the PWM
comparator.
The slope compensation timing diagram is shown in
Figure 10. The compensating ramp begins reducing the
In fixed frequency peak current mode control, converters
operating at duty cycles greater than 50% of the switching
period are susceptible to sub−harmonic oscillation,
characterized by successive switching cycles with
alternating wide and narrow pulse−widths. To avoid
www.onsemi.com
14
NCP12700
attenuated COMP voltage when the switching duty cycle is
nominally 40% and reduces the voltage by a peak, V
frequency. An image of the slope compensating ramp is also
,
applied at the input of the Current Limit comparator to
prevent sub−harmonic oscillations from occurring during
overload conditions. The chart below summarizes the dv/dt
of the compensating ramp at some common operating
frequencies.
SLP(PK)
of 98 mV at the 80% duty cycle limit. The slope
compensating ramp is synchronized to the duty cycle of the
oscillator, effectively adjusting itself based on the switching
frequency, providing the converter with a compensating
dv/dt ramp appropriate for the particular switching
F
SW
(kHz)
T
SW
(ms)
D = 40% (ms)
4.00
D = 80% (ms)
8.00
V (mV)
SLP
Ramp (mV/ms)
100
10.00
5.00
4.00
3.03
2.50
2.00
98
25
49
200
250
330
400
500
2.00
4.00
98
98
98
98
98
1.60
3.20
61
1.21
2.42
81
1.00
2.00
98
0.80
1.60
123
Cycle−by−Cycle Current Limit and Overload Protection
The NCP12700 implements cycle−by−cycle current
limiting with a dedicated Current Limit Comparator. The
input to the comparator is the primary FET current ramp
sensed at the CS pin. If the sensed voltage exceeds the
pulses and take the device into a Fault mode when the timer
has expired. The 30 ms timer allows the converter to sustain
a short term overload but still protects the converter from
thermal overstress in the event of a continuously applied
overload condition. The overload timer is also an integrating
timer, it will continue ramping up while the Current Limit
Comparator is terminating drive pulses but will begin
ramping down, not reset completely, if the drive pulse is
terminated by another signal such as the PWM comparator.
This operation is depicted in Figure 11.
current limit threshold, V
, of 495 mV then the drive
CS(LIM)
pulse is terminated. The Current Limit Comparator is very
fast with a total propagation delay, t , of 75 ns
CS(DLY)
maximum ensuring that drive pulses are quickly terminated
minimizing current overshoot in the converter.
The Current Limit comparator also triggers an overload
timer, t
, nominally 30 ms, and will disable drive
CS(OVLD)
V
COMP
V
DRV
Overload
Timer
time
t
t
t
t
t
t
6
1
2
3
4
5
Figure 11. Integrating Overload Timer
Short Circuit (SCP) Comparator
side rectifier or a shorted winding in the transformer it may
be possible to sense an abnormally high current pulse at the
CS pin and disable drive pulses to prevent the converter from
The NCP12700 also includes a fast Short Circuit
Comparator with a threshold, V , of 625 mV. In
SCP(LIM)
certain extreme fault conditions such as a shorted secondary
www.onsemi.com
15
NCP12700
further damage. If the voltage at the CS pin rapidly exceeds
dedicated Skip Comparator which monitors the voltage at
the COMP pin and blanks drive pulses if the COMP voltage
625 mV and the SCP comparator trips, then the drive pulse
will be terminated and a counter will be incremented. If the
SCP comparator trips on 4 consecutive drive pulses then
drive pulses will be disabled and the controller is put into the
Fault mode.
falls below the V
threshold of 300 mV. To
COMP(skip)
re−enable new drive pulses, the COMP voltage must exceed
a skip hysteresis, V of 25 mV above the
COMP(skip_hys)
300 mV threshold. The skip hysteresis is designed to
prevent the converter from oscillating in and out of skip
mode due to noise on the COMP pin.
Leading Edge Blanking (LEB)
Converters operating in peak current mode control require
a high quality current ramp signal to ensure stable and clean
PWM operation. In the NCP12700 the current ramp signal
is sensed at the CS pin and is routed through a LEB circuit
which blanks the current sense information for a brief period
after the DRV voltage is delivered to the primary MOSFET.
The LEB prevents noise generated during the switching
transition from terminating drive pulses prematurely. The
blanking is performed by an internal pulldown switch and
series disconnect switch. The internal pulldown switch has
Maximum Duty Cycle
The NCP12700 also includes a maximum duty cycle
clamp which terminates a drive pulse which has been high
for D
of the switching period. The default value of
MAX
D
MAX
will be 80%.
Soft Start
The soft start feature in the NCP12700 is implemented
with a dedicated comparator that compares the current ramp
signal from the CS pin against an attenuated soft start ramp
generated at the SS pin. Prior to enabling switching, an
internal pull−down transistor with an on resistance,
an on resistance, R
, specified as 55 ohms maximum.
PD(LEB)
The pulldown switch is turned on whenever the DRV is low
and remains on for a period of time equal to t
typical, after the DRV is set high.
, 60 ns
LEB(SCP)
R
, of 100 W is activated to discharge the external soft
SS(DIS)
start capacitor and hold the SS pin to GND. Once switching
is enabled the pull−down transistor is released and a current
After t
has expired the current ramp signal is
LEB(SCP)
delivered to the SCP comparator allowing it to sense an
abnormal overcurrent situation. A longer series LEB,
source, I , of 15 mA charges the soft start capacitor forming
SS
the soft start ramp voltage. The soft start ramp voltage is then
divided down by a factor of 6 and fed into the soft start
comparator which resets drive pulses when the CS voltage
exceeds the soft start voltage. The soft start comparator will
continue to reset drive pulses until another comparator
enters the reset path which typically occurs when the
secondary side control loop responds allowing the PWM
comparator to take control.
The NCP12700 monitors the external soft start voltage
and sets a flag when the voltage exceeds 3 V, declaring that
the soft start period has ended. At 3 V, the drive pulse reset
control will have been handed off to either the PWM
comparator or the Current limit comparator. The SS_END
flag is used internally by the controller for fault
management, gating detection of certain faults that may be
erroneously triggered during power up of the converter. This
is shown in the FLT pin block diagram of Figure 12.
t
, of 100 ns continues to hold open the signal path to
LEB(CS)
the CS and PWM comparators. This switch closes when
has expired, allowing the CS information to be
t
LEB(CS)
delivered to the other two comparators. In addition to the
LEB network, the user of the controller will usually place a
small RC filter in between the current sense components and
the CS pin to provide noise suppression. The resistor value
in the RC filter is typically in the range of 500 – 1 kW, sized
appropriately for the Over−Power protection feature, and
the capacitor value is typically chosen to provide a time
constant for the RC filter of about 50 – 100 ns.
Skip Comparator
For a power converter operating at light loads it is
sometimes desired to skip drive pulses in order to maintain
output voltage regulation or improve the light load
efficiency of the system. The NCP12700 features a
To V
VDD
CC
I
FLT
SS_END
To Fault Logic
t
OTP(DLY)
V
FLT(OTP)
FLT(OVP)
V
FLT(OTP_HYS)
t
OVP(DLY)
V
Figure 12. FLT Pin Block Diagram
www.onsemi.com
16
NCP12700
Fault (FLT) Pin
Summary of Fault Handling
The FLT pin is intended to provide the system with a NTC
interface for thermal protection and a pull−up fault which
can be coupled to the auxiliary winding to provide output
over−voltage protection. The FLT pin can also be used as a
general purpose fault where it interfaces with a simple
pull−down BJT, open collector comparator, or optocoupler
for monitoring of secondary side faults. The internal
The NCP12700 has 6 fault detectors which will place the
device into the fault mode. In the fault mode switching is
inhibited and the controller bias is maintained by the HV
startup regulator. The controller also reduces current
consumption to I
, 500 mA maximum, so that the
CC(FLT)
regulator is not thermally overstressed. The NCP12700
remains in the fault mode until the fault signal has been
cleared and/or the auto−recovery timer has expired. The
fault signal can be cleared when the fault detector senses that
the fault has been removed or by a controller reset which
circuitry includes a precision pull−up current source, I , of
FLT
85 mA and a window comparator to signal a fault whenever
the pin voltage goes below the OTP fault threshold,
V
V
, of 0.5 V or above the OVP fault threshold,
, of 3 V. Both of the fault comparators also include
occurs if V drops below V
or the UVLO pin is
FLT(OTP)
CC
CC(OFF)
pulled below the V
level. Below is a brief summary
FLT(OVP)
RST(th)
a delay filter to prevent noise or glitches from setting the
fault. The over−temperature fault filter, t , is
of the different fault detectors and their basic operation.
• Thermal Shutdown (TSD): Thermal shutdown is
declared when the internal junction temperature of the
OTP(DLY)
nominally 20 ms and the over−voltage fault filter, t
,
OVP(DLY)
is typically 5 ms. An external filter capacitor is also
advisable.
device exceeds the T
thermal shutdown fault is auto−recoverable when the
device junction temperature reduces to T
temperature of 165°C. The
SHDN
Both faults have an option to permanently latch off the
controller or restart after a 1 s auto−recovery period. The
OVP fault is intended to monitor an auxiliary winding and
when triggered, the controller will disable switching which
will inhibit the aux winding from generating voltage and
allow the controller to restart after the auto−recovery timer
has expired. If the OVP fault comparator is continuously
held above 3 V, the NCP12700 will remain in the fault mode
and not restart.
The OTP fault detection is gated by the SS_END flag to
prevent the comparator from triggering while the external
filter capacitor charges up. Once the SS_END flag is set the
OTP fault can be acknowledged so there is a practical limit
on the size of the filter capacitor. Equation 6 and Equation 7
should assist the user with properly setting the external
capacitance of the fault pin.
–
SHDN
T
where T
is typically 25°C.
SHDN(hys)
SHDN(hys)
• Fault OTP: An OTP fault is declared when fault pin
voltage decreases below the V threshold of
FLT(OTP)
0.5 V and the OTP filter, t
, expires. The OTP
OTP(DLY)
filter delay is typically 20 ms. The OTP fault is blanked
at startup until the SS_END flag has been set to allow
the external capacitance of the pin to charge up. For the
device to recover from the Fault OTP, the
auto−recovery timer must expire and the voltage at the
fault pin must recover to V
value of 0.9 V.
FLT(REC)
• Fault OVP: The OVP fault is declared when fault pin
the voltage exceeds the V threshold of 3 V and
FLT(OVP)
, expiring. The OVP filter
the OVP filter, t
OVP(DLY)
delay is typically 5 ms. The OVP fault is cleared when
the auto−recovery timer expires. There is no hysteresis
on the OVP fault but if the pin voltage is permanently
held above 3 V, DRV will pulses will be permanently
inhibited.
CSS VSS_END
(eq. 6)
tSS_END
+
ISS
IFLT tSS_END
(eq. 7)
CFLT
t
• Overload (OVLD): The OVLD fault is set when the
VFLT(OTP)
overload timer, t
, expires. The overload timer is
OVLD
When the OTP fault is triggered the NCP12700 will again
disable drive pulses and transition into a fault mode. The
OTP fault is auto−recoverable based on the auto−recovery
an integrating timer which counts up as long as the
Current Limit comparator is terminating DRV pulses.
The typical value for t
is 30 ms. The controller
OVLD
timer and a hysteresis set by the V
threshold of
FLT(REC)
will recover from the OVLD fault when the
auto−recovery timer expires.
0.9 V. The auto−recovery timer must expire and the voltage
at the fault pin must exceed 0.9 V. This methodology
guarantees a minimum amount of time for the system to
recover from thermal overstress but will not allow the
converter to restart unless the hysteresis is met. Given the
• SCP Fault: The SCP fault occurs when the N
SCP
counter has reaches 4 consecutive DRV pulses
terminated by the SCP comparator. The controller will
recover from the SCP fault when the auto−recovery
timer expires.
I
and V
specifications the critical NTC
FLT
FLT(OTP)
resistance for declaring a fault is ~ 5.9 kW. The critical
resistance for recovering from the OTP fault becomes ~
10.6 kW. This fault recovery threshold provides for about
~20°C of hysteresis for many NTC resistors.
• V OVP: The V OVP is set when V voltage
CC
CC
CC
exceeds the V
threshold of 28 V and the V
CC(OVP)
CC
OVP filter, t
, expires. The V OVP
CC
VCC_OVP(DLY)
filter is typically 3 ms. V OVP will permanently latch
CC
the device off so that it remains in the Fault mode
indefinitely until the controller is reset.
www.onsemi.com
17
NCP12700
Evaluation Board Designs
Two evaluation boards have been developed to highlight
DN05109 describes the operation of a 18 – 160 V input
flyback converter delivering 12 V out at 15 W. This
demonstration board switches at 100 kHz and operates in
discontinuous conduction mode across the entire input
voltage range. The key performance specifications are
shown in Table 6.
the features of the NCP12700. Detailed schematics,
operating waveforms, and bill of materials are available in
the design notes, DN05108 and DN05109. DN05108
describes the operation of a 9 – 36 V input flyback converter
delivering 12 V out at 15 W. This evaluation board switches
at 200 kHz and operates in both continuous and
discontinuous conduction modes. The key performance
specifications are shown in Table 5 below.
Table 6. WIDE RANGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 2
Table 5. LOW VOLTAGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Vin
Vo
18 − 160 V Operating
12 V − 1.25 A
15 W
Evaluation Board # 1
Po
Vin
Vo
9 − 36 V Operating
12 V − 1.25 A
15 W
Specifications
< 20 ms
Startup time
Po
Full Load Efficiency
Transient Response
Over Power Protection
Over Voltage Protection
No Load Output Ripple
No Load Power Dissipation
Input Current in SHDN
> 85 %
Specifications
< 30 ms
< 250 ms
Startup time
115% − 155%
16 VDC Max
150 mVpp Max
500 mW Max
< 1 mA
Full Load Efficiency
Transient Response
Over Power Protection
Over Voltage Protection
No Load Output Ripple
No Load Power Dissipation
Input Current in SHDN
> 87 %
< 250 ms
120% − 150%
16 VDC Max
200 mVpp Max
120 mW Max
< 1 mA
www.onsemi.com
18
NCP12700
PACKAGE DIMENSIONS
MSOP10, 3x3
CASE 846AE
ISSUE A
A
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN
EXCESS OF MAXIMUM MATERIAL CONDITION.
D
F
B
10
6
q
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15
MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTER-
LEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 MM PER SIDE.
DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DATUMS A AND B TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE
BODY.
E
E1
L
L1
L2
C
PIN ONE
INDICATOR
DETAIL A
1
5
e
10X b
M
S
S
0.08
C
B
A
TOP VIEW
MILLIMETERS
DETAIL A
DIM MIN
NOM
−−−
0.05
0.85
−−−
−−−
3.00
4.90
3.00
MAX
1.10
0.15
0.95
0.27
0.23
3.10
5.05
3.10
A
A
A1
A2
b
c
D
E
E1
e
−−−
0.00
0.75
0.17
0.13
2.90
4.75
2.90
A1
0.10 C
c
SEATING
PLANE
C
END VIEW
SIDE VIEW
0.50 BSC
0.70
L
0.40
0.80
L1
L2
q
0.95 REF
0.25 BSC
−−−
RECOMMENDED
SOLDERING FOOTPRINT*
0°
8°
10X
0.85
10X
0.29
5.35
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
19
NCP12700
PACKAGE DIMENSIONS
WQFN10 4x3, 0.8P
CASE 511DV
ISSUE A
NOTES:
L
L
A
B
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.20 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE PLATED TERMINALS.
L1
PIN ONE
REFERENCE
ALTERNATE A−1 ALTERNATE A−2
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
MILLIMETERS
A3
DIM MIN
0.70
A1 0.00 0.025
NOM MAX
TOP VIEW
EXPOSED Cu
MOLD CMPD
A
0.75
0.80
0.05
A3
b
D
0.20 REF
0.30
4.00
1.80
3.00
DETAIL B
0.25
3.90
0.35
4.10
1.85
3.10
1.63
A
0.10
0.08
C
A1
D1 1.75
2.90
ALTERNATE B−1
ALTERNATE B−2
E
E1 1.53
e
K
K1
L
1.58
C
DETAIL B
0.80 BSC
0.30 REF
0.36 REF
0.35
A1
SIDE VIEW
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
NOTE 4
C
0.30
0.40
L1
0.05 REF
D1
DETAIL A
e
K
e
4
RECOMMENDED
3
1
7
SOLDERING FOOTPRINT*
E1
K1
4.60
0.30
10X L
10X b
0.10
10
M
C A
B
0.80 PITCH
2X 0.36
1.58
1.59
M
NOTE 3
C
0.05
3.60
BOTTOM VIEW
1.80
10X 0.65
10X 0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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