NCP4354BDR2G [ONSEMI]
Secondary Side SMPS OFF Mode Controller for Low Standby Power; 二次侧开关电源OFF的低待机功耗模式控制器
| 型号： | NCP4354BDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Secondary Side SMPS OFF Mode Controller for Low Standby Power |
| 文件： | 总17页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP4353, NCP4354
Secondary Side SMPS OFF
Mode Controller for Low
Standby Power
The NCP4353/4 is a secondary side SMPS controller designed for
use in applications which require extremely low no load power
consumption. The device is capable of detecting “no load” conditions
and entering the power supply into a low consumption OFF mode.
During OFF mode, the primary side controller is turned off and energy
is provided by the output capacitors thus eliminating the power
consumption required to maintain regulation. During OFF mode, the
output voltage relaxes and is allowed to decrease to an adjustable
level. Once more energy is required, the NCP4353/4 automatically
restarts the primary side controller. The NCP4353/4 controls the
primary side controller with an “Active OFF” signal, meaning that it
drives optocoupler current during OFF mode to pull−down the FB pin
of the primary controller.
During normal power supply operation, the NCP4353/4 provides
integrated voltage feedback regulation, replacing the need for a shunt
regulator. The A versions include a current regulation loop in addition
to voltage regulation. Feedback control as well as ON/OFF signal can
be provided with only one optocoupler.
The NCP4354 includes a LED driver pin implemented with an open
drain MOSFET driven by a 1 kHz square wave with a 12.5% duty
cycle when primary side is in regulation for indication purpose.
The NCP4353 is available in TSOP−6 package while the NCP4354
is available in SOIC−8 package.
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MARKING
DIAGRAMS
TSSOP−6
CASE 318G
XXXAYWG
G
1
1
8
SOIC−8
CASE 751
XXXXX
ALYW G
G
8
1
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 15 of this data sheet.
Features
• Operating Input Voltage Range: 2.5 V to 36.0 V
• Supply Current < 100 mA
•
0.5% Reference Voltage Accuracy (T = 25°C)
J
• Constant Voltage and Constant Current (A versions) Control Loop
• Indication LED PWM Modulated Driver (NCP4354x)
• Designed for use with NCP1246 Fixed Frequency PWM Controller
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Offline Adapters for Notebooks, Game Stations and Printers
• High Power AC−DC Converters for TVs, Set−Top Boxes, Monitors, etc.
DEVICE OPTIONS
NCP4353A
NCP4353B
NCP4354A
NCP4354B
Adjustable
No
Yes
Yes
Yes
V
min
Current
Regulation
Yes
No
Yes
No
LED Driver
Package
No
No
Yes
Yes
TSOP−6
TSOP−6
SOIC−8
SOIC−8
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2013 − Rev. 3
NCP4353/D
NCP4353, NCP4354
Current
Regulation
ISNS
VCC
OTA
Sink only
VCC
management
VREFC
IBIASV
Power
RESET
VDD
SW3
VDD
VREF
VSNS
DRIVE
OTA
Sink only
Voltage
Regulation
VREF
Power
RESET
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
VCC
SW1
Off Mode
Detection
Q
Q
S
R
10%VCC
OFFDET
GND
VCC
Power RESET
NCP4353A
VCC
management
IBIASV
Power
RESET
SW3
VDD
VDD
VREF
VSNS
DRIVE
OTA
Sink only
Voltage
Regulation
VREF
0.9 x VREF
Power
RESET
IDRIVEOFF
IBIASV
Enabling
VCC
SW1
Off Mode
Detection
Q
Q
S
R
10%VCC
OFFDET
VMIN
GND
Power RESET
VREFM
Min Output
Voltage
NCP4353B
Figure 1. Simplified Block Diagrams NCP4353A and NCP4353B
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2
NCP4353, NCP4354
Current
Regulation
ISNS
VCC
OTA
Sink only
VCC
management
VREFC
IBIASV
Power
RESET
VDD
SW3
VDD
VREF
VSNS
OTA
DRIVE
Sink only
Voltage
Regulation
VREF
Power
RESET
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
VCC
SW1
Off Mode
Detection
Q
Q
S
R
10%VCC
LED
OFFDET
VMIN
SW2
1 kHz, 12% D.C.
Oscillator
GND
Power RESET
VREFM
Min Output
Voltage
NCP4354A
VCC
VCC
management
IBIASV
Power
RESET
SW3
VDD
VDD
VREF
VSNS
OTA
FBC
Sink only
Voltage
Regulation
VREF
Power
RESET
ON/OFF
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
VCC
SW1
Off Mode
Detection
Q
Q
S
R
10%VCC
LED
OFFDET
VMIN
SW2
1 kHz, 12% D.C.
Oscillator
GND
Power RESET
VREFM
Min Output
Voltage
NCP4354B
Figure 2. Simplified Block Diagrams NCP4354A and NCP4354B
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3
NCP4353, NCP4354
PIN FUNCTION DESCRIPTION
NCP4353A
NCP4353B
NCP4354A
NCP4354B
Pin Name
VCC
Description
1
2
6
1
2
6
8
7
1
8
7
1
Supply voltage pin
Ground
GND
VSNS
Output voltage sensing pin, connected to output
voltage divider
5
5
2
2
OFFDET
OFF mode detection input. Voltage divider
provides adjustable off mode detection threshold
−
4
3
4
3
VMIN
ISNS
Minimum output voltage adjustment
4
−
−
Current sensing input for output current regulation,
connect it to shunt resistor in ground branch.
−
−
−
−
5
4
6
LED
FBC
PWM LED driver output. Connected to LED cath-
ode with current define by external serial resist-
ance
−
Output of current sinking OTA amplifier or amplifi-
ers driving feedback optocoupler’s LED. Connect
here compensation network (networks) as well.
−
−
−
5
ON/OFF
DRIVE
OFF mode current sink. This output keeps primary
control pin at low level in off mode.
3
3
6
−
Combination of FBC and ON/OFF pins
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage
V
CC
−0.3 to 40
DRIVE, ON/OFF, FBC, LED Voltage
V
, V
FBC
,
−0.3 to V + 0.3
V
DRIVE
ONOFF
LED
CC
V
, V
VSNS, ISNS, OFFDET, VMIN Voltage
V
, V
,
−0.3 to 10
V
SNS
ISNS
V
, V
OFFDET MIN
LED Current
I
10
mA
LED
Thermal Resistance − Junction−to−Air (Note 1)
NCP4353A
R
315
324
260
277
°C/W
q
JA
NCP4353B
NCP4354A
NCP4354B
Junction Temperature
T
−40 to 150
−60 to 150
2000
°C
°C
V
J
Storage Temperature
T
STG
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD
HBM
ESD
250
V
MM
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2
1. 50 mm , 1.0 oz. Copper spreader.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JESD22−A114F
ESD Machine Model tested per JESD22−A115C
Latchup Current Maximum Rating tested per JEDEC standard: JESD78D.
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4
NCP4353, NCP4354
ELECTRICAL CHARACTERISTICS
0°C ≤ T ≤ 125°C; V = 15 V; unless otherwise noted. Typical values are at T = +25°C.
J
CC
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Maximum Operating Input
Voltage
VCC
36.0
V
VCC UVLO
V
rising
falling
V
3.3
2.3
0.8
3.5
2.5
1.0
101
82
3.7
2.7
V
CC
CCUVLO
V
CC
VCC UVLO Hysteresis
V
V
CCUVLOHYS
NCP4353A
NCP4353B
NCP4354A
NCP4354B
I
125
105
145
120
110
mA
CC
Quiescent Current in Regulation
118
95
Quiescent Current in OFF Mode
VOLTAGE CONTROL LOOP OTA
Transconductance
V
< 1.12 V
I
90
mA
SNS
CC,OFFmode
Sink current only
2.8 V ≤ V ≤ 36.0 V, T = 25°C
gm
1
S
V
V
Reference Voltage
V
REF
1.244
1.240
1.230
2.5
1.250
1.250
1.250
1.256
1.264
1.270
CC
J
2.8 V ≤ V ≤ 36.0 V, T = 0 − 85°C
CC
J
2.8 V ≤ V ≤ 36.0 V, T = 0 − 125°C
CC
J
Sink Current Capability
In regulation, V
or V
> 1.5 V
> 1.5 V
FBC
I
SINKV
mA
mA
nA
mA
V
DRIVE
FBC
In OFF mode, V
or V
1.2
1.5
2.0
100
−10
1.17
DRIVE
Inverting Input Bias Current
In regulation, V
= V
I
−100
−13
SNS
SNS
REF
BIASV
In OFF mode, V
> 1.12 V
−11
Inverting Input Bias Current
Threshold
In OFF mode
V
1.07
1.12
SNSBIASTH
CURRENT CONTROL LOOP OTA (NCP435xA only)
Transconductance
Sink current only
gm
3
S
C
Reference Voltage
V
60
2.5
62.5
65
mV
mA
nA
REFC
Sink Current Capability
Inverting Input Bias Current
V
or V
> 1.5 V
I
SINKC
DRIVE
FBC
I
= V
I
BIASC
−100
100
400
SNS
REFC
MINIMUM VOLTAGE COMPARATOR (except NCP4353A)
Threshold Voltage
V
REFM
355
377
40
mV
mV
Hysteresis
Output change from logic high to logic low
V
MINH
OFF MODE DETECTION COMPARATOR
Threshold Value
2.5 V ≤ V ≤ 36.0 V
V
10% V
1.50
40
V
CC
OFFDETTH
CC
V
CC
= 15 V
1.47
1.53
Hysteresis
Output change from logic high to logic low
V
mV
OFFDETH
LED DRIVER (NCP4354x only)
Switching Frequency
Duty Cycle
f
1
kHz
%
SWLED
D
10.0
140
12.5
50
15.0
180
LED
Switch Resistance
OFF MODE CONTROL
Sink Current
I
= 5 mA
R
W
LED
SW2
In OFF mode, V
or V
> 0.6 V
I
DRIVEOFF
160
mA
DRIVE
ONOFF
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5
NCP4353, NCP4354
TYPICAL CHARACTERISTICS
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
−40 −20
0
20
40
60
80
100 120
0
6
12
18
(V)
24
30
36
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 3. VREF at VCC = 15 V
Figure 4. VREF at TJ = 255C
63
62.9
62.8
62.7
62.6
62.5
62.4
62.3
62.2
62.1
62
63
62.9
62.8
62.7
62.6
62.5
62.4
62.3
62.2
62.1
62
0
6
12
18
(V)
24
30
36
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 5. VREFC at VCC = 15 V
Figure 6. VREFC at TJ = 255C
410
400
390
380
370
360
350
410
400
390
380
370
360
350
−40 −20
0
20
40
60
80
100 120
0
6
12
18
(V)
24
30
36
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 7. VREFM at VCC = 15 V
Figure 8. VREFM at TJ = 25 5C
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6
NCP4353, NCP4354
TYPICAL CHARACTERISTICS
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
1.53
1.52
1.51
1.50
1.49
1.48
1.47
VCCUVLO_R
VCCUVLO_F
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. VCCUVLO
Figure 10. VOFFDETTH at VCC = 15 V
175
170
165
160
155
150
145
140
135
−10
−10.2
−10.4
−10.6
−10.8
−11
−11.2
−11.4
−11.6
−11.8
−12
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. IONOFF at VCC = 15 V
Figure 12. IBIASV at VCC = 15 V, VSNS
VSNSBIASTH
>
150
140
130
120
110
100
90
150
140
130
120
110
100
90
−40 −20
0
20
40
60
80
100 120
0
6
12
18
(V)
24
30
36
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 13. ICC in Regulation at VCC = 15 V for
NCP4354A
Figure 14. ICC in Regulation at TJ = 255C for
NCP4354A
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7
NCP4353, NCP4354
TYPICAL CHARACTERISTICS
120
115
110
105
100
95
120
115
110
105
100
95
90
90
85
85
80
80
75
75
70
70
−40 −20
0
20
40
60
80
100 120
0
6
12
18
(V)
24
30
36
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 15. ICC in OFF Mode at VCC = 15 V,
SNS < VSNSBIASTH, for NCP4354A
Figure 16. ICC in OFF Mode at TJ = 255C,
V
V
SNS < VSNSBIASTH, for NCP4354A
120
115
110
105
100
95
120
115
110
105
100
95
90
90
85
85
80
80
75
75
70
70
−40 −20
0
20
40
60
80
100 120
0
6
12
18
(V)
24
30
36
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 17. ICC in Regulation at VCC = 15 V for
NCP4354B
Figure 18. ICC in Regulation at TJ = 255C for
NCP4354B
120
115
110
105
100
95
120
115
110
105
100
95
90
90
85
85
80
80
75
75
70
70
−40 −20
0
20
40
60
80
100 120
0
6
12
18
(V)
24
30
36
T , JUNCTION TEMPERATURE (°C)
V
J
CC
Figure 19. ICC in OFF Mode at VCC = 15 V,
SNS < VSNSBIASTH, for NCP4354B
Figure 20. ICC in OFF Mode at TJ = 255C,
V
VSNS < VSNSBIASTH, for NCP4354B
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8
NCP4353, NCP4354
TYPICAL CHARACTERISTICS
3.5
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. Voltage OTA Current Sink
Capability in Regulation
Figure 22. Voltage OTA Current Sink
Capability in OFF Mode
3.5
1.40
1.30
1.20
1.10
1.00
0.90
0.80
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. Current OTA Current Sink
Capability
Figure 24. LED Switching Frequency at
CC = 15 V
V
100
90
80
70
60
50
40
30
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. RSW2 at VCC = 15 V
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NCP4353, NCP4354
APPLICATION INFORMATION
VOUT
VOUT
A typical application circuit for NCP435x series is shown
in Figure 28, done with an imaginary IC with all features in
one. Pin functions are available in pin description table.
Simplified typical application circuit for NCP4353B that
shows only available features in this IC is shown in
Figure 27. Figure 29 shows possible connection of the
NCP4353B to flyback primary controller.
R4
R4
R7
VMIN
VSNS
VSNS
VMIN
R5
R6
R5
R6
R7
IC will be derived in multiple versions with different
features for each of them.
Power Supply
The NCP435x is designed to operate from a single supply
up to 36 V. It starts to operate when VCC voltage reaches
TYPE 1
TYPE 2
3.5 V and stops when VCC voltage drops below 2.5 V. V
CC
can be supplied by direct connection to the VOUT voltage
of the power supply. It is highly recommended to add a RC
filter (R1 and C3) in series from VOUT to VCC pin to reduce
voltage spikes and drops that are produced at the converter’s
output capacitors. Recommended values for this filter are
220 W and 1 mF.
Figure 26. Shared Dividers Type
Current Regulation Path (A versions only)
The output current is sensed by the shunt resistor R12 in
series with the load. Voltage drop on R12 is compared with
internal precise voltage reference
transconductance amplifier input.
V
REFC
at I
SNS
Voltage Regulation Path
The output voltage is detected on the VSNS pin by the R4,
R5 and R6 voltage divider. This voltage is compared with
the internal precise voltage reference. The voltage
Voltage difference is amplified by gm to output current
C
of amplifier, connected to FBC or DRIVE pin.
Compensation network is connected between this pin and
ISNS input to provide frequency compensation for current
regulation path. Resistor R13 separates compensation
network from sense resistor. Compensation network works
into low impedance without this resistor that significantly
decreases compensation network impact.
difference is amplified by gm of the transconductance
V
amplifier. The amplifier output current is connected to the
FBC or DRIVE pin. The compensation network is also
connected to this pin to provide frequency compensation for
the voltage regulation path. This FBC (DRIVE) pin drives
regulation optocoupler that provides regulation of primary
side. The optocoupler is supplied via direct connection to
VOUT line through resistor R2.
Regulation information is transferred through the
optocoupler to the primary side controller where its FB pin
is usually pulled down to reduce energy transferred to
secondary output.
Current regulation point is set to current given by
Equation 4.
VREFC
(eq. 4)
IOUTLIM
OFF Mode Detection
+
R12
OFF mode operation is advantageous for ultra low or zero
output current condition. The very long off time and the ultra
low power mode of the whole regulation system greatly
reduces the overall consumption.
The output voltage is varying between nominal and
minimal in OFF mode. When output voltage decreases
below set (except NCP4353A) minimum level, primary
controller is switched on until output capacitor C1 is charged
again to the nominal voltage.
The VSNS voltage divider is shared with VMIN voltage
divider. The shared voltage divider can be connected in two
ways as shown in Figure 26. The divider type is selected
based on the ratio between V
and V . When the
OUT
MIN
condition of Equation 1 is true, divider type 1 should be
used.
VOUT VREFM
(eq. 1)
V
MIN u
VREF
The OFF mode detection is based on comparison of output
voltage and voltage loaded with fixed resistances (D2, C2,
R8 and R9). Figure 30 shows detection waveforms. When
output voltage is loaded with very low current, primary
controller goes into skip mode (primary controller stops
switching for some time). While output capacitor C1 is
discharged very slowly (no load condition), the capacitor C2
Output voltage for divider type 1 can be computed by
Equation 2
R4 ) R5 ) R6
(eq. 2)
V
OUT + VREF
R5 ) R6
and for type 2 by Equation 3.
R4 ) R5 ) R6
(eq. 3)
V
OUT + VREF
R6
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10
NCP4353, NCP4354
is discharged through a fixed load, by R8 and R9 faster than
output voltage on C1.
over UVLO level (3), primary controller starts to operate.
VCC capacitor is charged above DSS level from auxiliary
Once OFFDET pin voltage is lower than V
(this
winding, V
is slowly rising according to primary
OFFDETTH
OUT
threshold is derived from V ), OFF mode is detected. In
OUT
controller start up ramp to nominal voltage (4).
OFF mode SW1 is switched on to allow I
current,
Primary FB pin voltage is above regulation range until
DRIVEOFF
going through ON/OFF pin (NCP4354B) or DRIVE pin, to
keep switch off primary controller.
A higher sink current on primary FB pin is needed to keep
primary controller FB below the skip level until the OFF
mode is detected on primary side.
V
is at set level. Once V
is at set level, the secondary
OUT
OUT
controller starts to sink current from optocoupler LED’s and
primary FB voltage is stabilized in regulation region. With
nominal output power (without skip mode) OFFDET pin
voltage is higher than V
(typically 10% of V ).
OFFDETTH
CC
Despite output voltage on C1 may go down, the current
After some time, the load current decreases to low level
(5) and primary convertor uses skip mode (6) to keep
regulation of output voltage at set level. The skip mode
consists of few switching cycles followed by missing ones
to provide limited energy by light load. The number of
missing cycles allows regulation for any output power.
While both C1 and C2 are discharged during the missing
cycles, C2 discharge will be faster than C1 without output
I
injected into VSNS pin provides the requested offset
BIASV
(VSNS voltage is higher than V ). Primary IC should
REF
detect OFF mode before VSNS is lower than 90% of V
REF
while I
is switched off to reduce consumption.
BIASV
This offset, defined by R7 and the internal current source,
should be large enough to secure off mode detection of the
primary controller and avoid restart when V
< V
.
SNS
REF
current, V
drops below V
and OFF mode
OFFDET
OFFDETTH
Minimum Output Voltage Detection (Except
NCP4353A)
Minimum output voltage level defines primary controller
restart from OFF mode. It can be set by shared voltage
divider with voltage regulation loop. When VMIN voltage
is detected (7). This situation is shown in Figure 30 in detail.
When OFF mode is detected, internal pull−up current
I
I
is switch on (7), VSNS voltage increases (due to
) and voltage amplifier sinks full current to keep
BIASV
BIASV
primary FB voltage below skip level until OFF mode is
detected by the primary side controller (8). Current into
ONOFF pin or DRIVE pin begins to flow at the same time,
when entering into OFF mode (7). When OFF mode is
detected by primary side controller (8a), primary FB
injected current decreases to a lower level to reduce overall
power consumption. Optocoupler current, can also be
reduced from that time to keep the level below restart level.
Secondary side controller decreases optocoupler current
(voltage transconductance amplifier stops to sink current)
when VSNS voltage drops below V
also switch off when V
reduce overall consumption. This point is defined by I
current, R6, R4 and R5 resistors and discharging time of
output capacitor C1. Discharging of C1 continues (10) until
output voltage drops below level set by voltage divider at
drops below V , OFF mode is ended and primary
REFM
controller restarts.
Minimum voltage level is given by Equation 5 for divider
type 1
R4 ) R5 ) R6
(eq. 5)
V
MIN + VREF
R6
and for type 2 by Equation 6.
R4 ) R5 ) R6
R5 ) R6
(eq. 6)
V
MIN + VREF
(9) and I
is
REF
BIASV
NCP4353A has no external adjustment and uses the
internal minimum voltage level specified by minimum
falling operation supply voltage.
is lower than 90% of V
to
SNS
REF
BIASV
LED Driver (NCP4354x only)
LED driver is active when VCC is higher than V
CCMIN
VMIN pin (except NCP4353A where minimum V
is
OUT
and output voltage is in regulation (driver is off in OFF
mode). LED driver consists of an internal power switch
controlled by a PWM modulated logic signal and an external
current limiting resistor R3. LED current can be computed
by Equation 7.
defined only by VCC UVLO) (11). ONOFF current stops
and thanks to internal pull−up, the primary FB voltage rises
above restart level (12) and primary controller starts
switching (13). Output capacitor C1 is recharged (14) to set
voltage. If there is still light load condition primary
controller goes to skip mode (15) again and after some time
secondary controller detects OFF mode by very light or no
load condition (16) and whole cycle is repeated.
V
OUT * VF_LED
(eq. 7)
ILED
+
R3
PWM modulation is used to increase efficiency of LED.
Fast Restart From OFF Mode
The IC ends OFF mode when a load is connected to the
Operation in OFF Mode Description
Operation waveforms in off mode and transition into OFF
mode with NCP1246 primary controller are shown in
Figure 31.
Figure shows waveforms from the first start (1) of the
convertor. At first, primary controller’s DSS charges VCC
output and V
is discharged to V
level. There exists
OUT
MIN
another connection that allows transition to normal mode
faster without waiting some time for V to discharge to
OUT
V
MIN
. This schematic is shown at Figure 32. The basic idea
is that C3 is discharged by the IC faster than C1 by output
capacitor over the UVLO level (2). When primary V is
CC
http://onsemi.com
11
NCP4353, NCP4354
load in OFF mode. When an output load is applied, capacitor
mode because voltage at its FB pin rises above OFF mode
end level and switching resumes.
Normal operation waveforms for typical load detection
connection and improved load detection waveforms are
shown in Figure 33.
C1 is discharged faster and this creates a voltage drop at D8.
When there is enough voltage at D8, T2 is opened and
current is injected into the OFFDET divider through R17.
OFFDET voltage higher than 10% of V ends OFF mode
CC
and ON/OFF current stops. Primary controller leaves OFF
OFF Supply
D2
D1
VOUT
R4
R1
C1
C2
VCC
VCC
management
C3
IBIASV
Power
RESET
C4
SW3
VDD
VDD
R10
VREF
R7
Feedback
&
ON / OFF
Opto
OTA
VSNS
Sink only
DRIVE
R2
Voltage
Regulation
VREF
Power
RESET
R8
R5
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
VCC
SW1
Off Mode
Detection
Q
Q
S
R
10%VCC
OFFDET
VMIN
GND
R6
Power RESET
R9
VREFM
Min Output
Voltage
Figure 27. Typical Application Schematic for NCP4353B
OFF Supply
D2
D1
VOUT
R12
R1
C1
C2
R4
Current
Regulation
ISNS
VCC
OTA
Sink only
VCC
management
C3
R13
VREFC
IBIASV
Power
RESET
C4
C5
R11
SW3
VDD
VDD
R10
VREF
R7
Feedback
&
OTA
VSNS
ON / OFF
Opto
Sink only
FBC
R2
Voltage
Regulation
VREF
Power
RESET
R8
ON/OFF
R5
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
VCC
SW1
Off Mode
Detection
Q
Q
S
R
10%VCC
ON / OFF
LED
OFFDET
VMIN
LED
R3
SW2
1 kHz, 12% D.C.
Oscillator
GND
R6
Power RESET
R9
VREFM
Min Output
Voltage
Figure 28. Typical Application Schematic for All Features
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12
NCP4353, NCP4354
D3
VCC
D2
D1
D4
D5
R1
VIN
C1
C2
~
C6
VOUT
R4
R5
R10 C4
C3
D6
D7
VCC
DRIVE
VMIN
R14
R2
OPTO1
R8
R9
T1
HV
DRV
CS
OFFDET
VSNS
VCC
VCC
GND
R15
R7
C7
FB
NCP4353B
R6
GND
C8
Figure 29. Typical Application Schematic for NCP4353B with Flyback
Normal operation
Skip
Off mode
Primary
Controller
Activity
Very low or no load detected,
off mode activated
VOFFDET
10% VOUT(VCC)
IOUT
Figure 30. OFF Mode Detection
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13
NCP4353, NCP4354
Figure 31. Typical Application States and Waveforms in OFF Mode with NCP1246 Primary Controller
D2
D1
R16
D8
C1
C2
VOUT
R4
R5
R10 C4
FBC
T2
C3
VCC
VMIN
R8
R2
ON/OFF
OPTO1
OFFDET
VSNS
LED
R7
LED1 R3
GND
R17
NCP4354B
R6
R9
Figure 32. Improved Load Detection Connection
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14
NCP4353, NCP4354
Figure 33. Typical and Improved Load Detection Comparison Waveforms
ORDERING INFORMATION
Adjustable
Current
Regulation
LED
Driver
†
V
min
Device
Marking
Package
Shipping
NCP4353ASNT1G
A53
No
Yes
Yes
Yes
Yes
No
TSOP−6
3000 / Tape & Reel
3000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
(Pb−Free)
NCP4353BSNT1G
NCP4354ADR2G
NCP4354BDR2G
B53
No
No
TSOP−6
(Pb−Free)
NCP4354A
NCP4354B
Yes
No
Yes
Yes
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
NCP4353, NCP4354
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE U
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
PLANE
M
C
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
L
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0°
10°
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
0.95
3.20
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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16
NCP4353, NCP4354
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NCP4353/D
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