NCP4355BDR2G [ONSEMI]
Secondary Side SMPS OFF Mode Controller;
| 型号： | NCP4355BDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Secondary Side SMPS OFF Mode Controller 开关 光电二极管 |
| 文件： | 总17页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP4355
Secondary Side SMPS OFF
Mode Controller for Low
Standby Power
Description
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The NCP4355 is a secondary side SMPS controller designed for use
in applications which require extremely low no load power
consumption. The device is capable of detecting “no load” conditions
and entering the power supply into a low consumption OFF mode.
During OFF mode, the primary side controller is turned off and energy
is provided by the output capacitors thus eliminating the power
consumption required to maintain regulation. During OFF mode, the
output voltage relaxes and is allowed to decrease to an adjustable
level. Once more energy is required, the NCP4355 automatically
restarts the primary side controller by ONOFF current that flows
through ONOFF optocoupler. The NCP4355 controls the primary
controller with an “Active ON” signal, meaning that it only drives
optocoupler current during ON mode to minimize consumption during
OFF mode.
8
1
SOIC−8
D SUFFIX
CASE 751
8
XXXXX
ALYWG
G
1
During normal power supply operation, the NCP4355 provides
integrated voltage feedback regulation, replacing the need for a shunt
regulator. The A and C versions include a current regulation loop in
addition to voltage regulation.
The NCP4355 includes a LED driver pin (except C version)
implemented with an open drain MOSFET driven by a 1 kHz square
wave with a 12.5% duty cycle for indication purpose.
XXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
The NCP4355 is available in SOIC−8 package.
DEVICE OPTIONS
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 16 of this data sheet.
NCP4355A
No
NCP4355B
Yes
NCP4355C
Yes
Adjustable Vmin
Current Regulation
LED driver
Yes
No
Yes
Yes
Yes
No
Features
• Operating Input Voltage Range: 3.5 V to 36.0 V
• Supply Current < 100 mA
•
0.5% Reference Voltage Accuracy (T = 25°C)
J
• Constant Voltage and Constant Current (A and C versions) Control
Loop
• Indication LED PWM Modulated Driver (except NCP4355C)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Offline Adapters for Notebooks, Game Stations and Printers
• High Power AC−DC Converters for TVs, Set−Top Boxes, Monitors etc.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2013 − Rev. 1
NCP4355/D
NCP4355
Current
Regulation
ISNS
VCC
OTA
Sink only
V
CC
V
REFC
management
I
Power
RESET
BIASV
SW3
V
DD
V
DD
V
REF
VSNS
OTA
FBC
Sink only
Voltage
V
ON/OFF
REF
Power
RESET
Regulation
0.9 x V
I
REF
DRIVEON
I
BIASV
Enabling
VCC
SW1
SW2
Off Mode
Detection
Q
Q
S
R
10%V
CC
LED
OFFDET
1 kHz, 12% D.C.
Oscillator
GND
PowerRESET
Figure 1. Simplified Block Diagram − NCP4355A
VCC
V
CC
management
I
BIASV
Power
RESET
SW3
V
DD
V
DD
V
REF
VSNS
OTA
FBC
Sink only
Voltage
Regulation
V
REF
Power
ON/OFF
RESET
0.9 x V
I
REF
DRIVEON
I
BIASV
Enabling
VCC
SW1
SW2
Off Mode
Q
S
R
Detection
10%V
CC
Q
LED
OFFDET
VMIN
1 kHz, 12% D.C.
Oscillator
GND
PowerRESET
V
REFM
Min Output
Voltage
Figure 2. Simplified Block Diagram − NCP4355B
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2
NCP4355
Current
Regulation
ISNS
VCC
OTA
Sink only
V
CC
V
REFC
management
I
BIASV
Power
RESET
SW3
V
DD
V
DD
V
REF
VSNS
OTA
FBC
Sink only
Voltage
Regulation
V
REF
ON/OFF
Power
RESET
0.9 x V
REF
I
DRIVEON
I
BIASV
Enabling
VCC
SW1
Off Mode
Q
S
R
Detection
10%V
CC
Q
OFFDET
VMIN
GND
PowerRESET
V
REFM
Min Output
Voltage
Figure 3. Simplified Block Diagram − NCP4355C
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3
NCP4355
PIN FUNCTION DESCRIPTION
NCP4355A
NCP4355B
NCP4355C
Pin Name
VCC
Description
8
7
1
2
8
7
1
2
8
7
1
2
Supply voltage pin
Ground
GND
VSNS
Output voltage sensing pin, connected to output voltage divider
OFFDET
OFF mode detection input. Voltage divider provides adjustable off mode
detection threshold
−
3
3
4
VMIN
ISNS
Minimum output voltage adjustment
3
−
Current sensing input for output current regulation, connect it to shunt
resistor in ground branch.
4
6
5
4
6
5
−
6
5
LED
FBC
PWM LED driver output. Connected to LED cathode with current define by
external serial resistance
Output of current sinking OTA amplifier or amplifiers driving feedback op-
tocoupler’s LED. Connect here compensation network (networks) as well.
ON/OFF
ON mode current sink. This output keeps primary control pin at low level
in on mode.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage
V
CC
−0.3 to 40.0
ON/OFF, FBC, LED Voltage
VSNS, ISNS, OFFDET, VMIN Voltage
LED Current
V
, V
, V
−0.3 to V + 0.3
V
ONOFF FBC
LED
CC
V
, V
, V
, V
−0.3 to 10.0
V
SNS
ISNS
OFFDET MIN
LED
I
10
mA
°C/W
Thermal Resistance − Junction−to−Air (Note 1)
NCP4355A/C
NCP4355B
R
260
277
q
JA
Junction Temperature
T
−40 to 150
−60 to 150
2000
°C
°C
V
J
Storage Temperature
T
STG
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD
HBM
ESD
250
V
MM
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2
1. 50 mm , 1.0 oz. Copper spreader.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JESD22−A114F
ESD Machine Model tested per JESD22−A115C
Latchup Current Maximum Rating tested per JEDEC standard: JESD78D.
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4
NCP4355
ELECTRICAL CHARACTERISTICS
0°C ≤ TJ ≤ 125°C; V = 15 V; unless otherwise noted. Typical values are at TJ = +25°C.
CC
Parameter
Maximum Operating Input Voltage
VCC UVLO
Test Conditions
Symbol
Min
Typ
Max
36.0
4.25
3.78
Unit
V
VCC
V
V
rising
falling
V
3.75
3.22
0.4
4.00
3.50
0.5
V
CC
CCUVLO
CC
VCC UVLO Hysteresis
V
V
CCUVLOHYS
Quiescent Current In Regulation
NCP4355A
NCP4355B
NCP4355C
I
125
107
115
90
155
135
155
110
mA
CC
Quiescent Current In OFF mode
VOLTAGE CONTROL LOOP OTA
Transconductance
V
SNS
< 1.12 V
I
mA
CCOFF
Sink current only
3.8 V ≤ V ≤ 36.0 V, T = 25°C
gm
1
S
V
V
Reference Voltage
V
REF
1.244
1.240
1.230
2.5
1.250
1.250
1.250
1.256
1.264
1.270
CC
J
3.8 V ≤ V ≤ 36.0 V, T = 0 − 85°C
CC
J
3.8 V ≤ V ≤ 36.0 V, T = 0 − 125°C
CC
J
Sink Current Capability
In regulation, V
> 1.5 V
I
mA
mA
nA
mA
V
FBC
SINKV
In OFF mode, V
In regulation
> 1.5 V
1.2
1.5
2.0
100
−1.9
1.17
FBC
Inverting Input Bias Current
I
−100
−2.6
1.07
BIASV
In OFF mode, V
> 1.12 V
−2.3
SNS
Inverting Input Bias Current Threshold In OFF mode
V
1.12
SNSBIASTH
CURRENT CONTROL LOOP OTA (except NCP4355B)
Transconductance
Sink current only
gm
3
S
C
Reference Voltage
V
60.0
2.5
62.5
65.0
100
400
mV
mA
nA
REFC
Sink Current Capability
Inverting Input Bias Current
V
> 1.5 V
I
SINKC
FBC
I
= V
I
−100
SNS
REFC
BIASC
MINIMUM VOLTAGE COMPARATOR (except NCP4355A)
Threshold Voltage
V
REFM
355
377
40
mV
mV
Hysteresis
Output change from logic high to logic low
V
MINH
OFF MODE DETECTION COMPARATOR
Threshold Value
2.5 V ≤ V ≤ 36.0 V
V
10% V
CC
V
V
CC
OFFDETTH
V
= 15 V
1.47
1.50
40
1.53
CC
Hysteresis
Output change from logic high to logic low
V
mV
OFFDETH
LED DRIVER (except NCP4355C)
Switching Frequency
Duty Cycle
f
1
kHz
%
SWLED
D
10.0
140
12.5
50
15.0
180
LED
Switch Resistance
ON MODE CONTROL
Sink Current
I
= 5 mA
R
W
LED
SW2
In ON mode, V
> 0.6 V
I
160
mA
ONOFF
DRIVEON
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5
NCP4355
TYPICAL CHARACTERISTICS
1.29
1.28
1.27
1.26
1.25
1.24
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.23
1.22
−40 −20
0
20
40
T (°C)
60
80
100 120
100 120
100 120
0
0
0
6
6
6
12
18
(V)
24
30
30
30
36
36
36
V
J
CC
Figure 4. VREF at VCC = 15 V
Figure 5. VREF at TJ = 255C
63.0
62.9
62.8
62.7
62.6
62.5
62.4
62.3
62.2
63.0
62.9
62.8
62.7
62.6
62.5
62.4
62.3
62.2
62.1
62.0
62.1
62.0
−40 −20
0
20
40
T (°C)
60
80
12
18
(V)
24
V
J
CC
Figure 6. VREFC at VCC = 15 V
Figure 7. VREFC at TJ = 255C
410
400
410
400
390
380
370
390
380
370
360
350
360
350
−40 −20
0
20
40
T (°C)
60
80
12
18
(V)
24
V
J
CC
Figure 8. VREFM at VCC = 15 V
Figure 9. VREFM at TJ = 255C
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NCP4355
TYPICAL CHARACTERISTICS
4.2
4.1
4.0
3.9
3.8
3.7
3.6
1.53
1.52
1.51
1.50
1.49
VCCUVLO_R
VCCUVLO_F
1.48
1.47
3.5
3.4
−40 −20
0
20
40
T (°C)
60
80
100 120
100 120
100 120
−40 −20
0
20
40
T (°C)
60
80
100 120
J
J
Figure 10. VCCUVLO
Figure 11. VOFFDETTH at VCC = 15 V
175
170
165
160
155
150
145
−1.9
−2.0
−2.1
−2.2
−2.3
−2.4
−2.5
−2.6
140
135
−40 −20
0
20
40
T (°C)
60
80
−40 −20
0
20
40
T (°C)
60
80
100 120
J
J
Figure 12. IONOFF at VCC = 15 V
Figure 13. IBIASV at VCC = 15 V,
SNS > VSNSBIASTH
V
120
115
110
120
115
110
105
100
95
105
100
95
90
90
85
85
80
80
75
70
−40 −20
75
70
0
20
40
T (°C)
60
80
0
6
12
18
(V)
24
30
36
V
J
CC
Figure 14. ICC in Regulation at VCC = 15 V for
NCP4355B
Figure 15. ICC in Regulation at TJ = 255C
for NCP4355B
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NCP4355
TYPICAL CHARACTERISTICS
110
105
100
95
110
105
100
95
90
90
85
85
80
80
75
75
70
70
65
60
−40 −20
65
60
0
20
40
T (°C)
60
80
100 120
0
6
12
18
(V)
24
30
36
V
J
CC
Figure 16. ICC in OFF Mode at VCC = 15 V,
SNS < VSNSBIASTH, for NCP4355B
Figure 17. ICC in OFF Mode at TJ = 255C,
V
VSNS < VSNSBIASTH, for NCP4355B
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
2.6
2.5
−40 −20
0
20
40
T (°C)
60
80
100 120
−40 −20
0
20
40
T (°C)
60
80
100 120
J
J
Figure 18. Voltage OTA Current Sink
Capability in Regulation
Figure 19. Voltage OTA Current Sink
Capability in OFF Mode
1.4
1.3
1.2
1.1
1.0
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
0.9
0.8
2.6
2.5
−40 −20
0
20
40
T (°C)
60
80
100 120
−40 −20
0
20
40
T (°C)
60
80
100 120
J
J
Figure 20. Current OTA Current Sink
Capability
Figure 21. LED Switching Frequency
at VCC = 15 V
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8
NCP4355
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
−40 −20
0
20
40
T (°C)
60
80
100 120
J
Figure 22. RSW2 at VCC = 15 V
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NCP4355
APPLICATION INFORMATION
Typical application circuits for NCP4355x are shown in
Figure24, Figure 25 and Figure 26. Each IC version contains
different features. Please see Device options table or Block
diagrams for detail information. NCP4355A does not have
a VMIN pin for setting the minimum voltage level, therefore
it needs a special circuit shown in Figure 24 in the dashed
box. This is needed for correct detection of load connection
in OFF mode. The same circuit can be used for other versions
when high speed detection of load connection is needed.
Supply Voltage
The IC is supplied through VCC pin. Supply voltage
should be taken from output voltage in range from 4.5 V up
to 36 V. Power supply voltage should be separated from
output voltage by a diode D3 and some energy should be
stored in a VCC cap C6. Cap should be high enough to keep
enough energy for ONOFF optocoupler and NCP4355x
before primary controller is started. Time constant of the
VCC cap C6 and the IC supply current should be smaller
than time constant of power supply output filter and
maximum output current in OFF mode. VCC pin should also
be decoupled by 100 nF decoupling cap C5.
Figure 23. Shared Dividers Type
Current Regulation Path (A and C versions only)
The output current is sensed by the shunt resistor R11 in
series with the load. Voltage drop on R11 is compared with
internal precise voltage reference V
ductance amplifier input.
at I
transcon−
REFC
SNS
Voltage difference is amplified by gm to output current
C
of amplifier, connected to FBC pin. Compensation network
is connected between this pin and ISNS input to provide
frequency compensation for current regulation path.
Resistor R12 separates compensation network from sense
resistor. Compensation network works into low impedance
without this resistor that significantly decreases
compensation network impact.
Voltage Regulation Path
The output voltage is detected on the VSNS pin by the R4,
R5 and R6 voltage divider. This voltage is compared with
the internal precise voltage reference. The voltage
difference is amplified by gm of the transconductance
V
amplifier. The amplifier output current is connected to the
FBC pin. The compensation network is also connected to
this pin to provide frequency compensation for the voltage
regulation path. This FBC pin drives an optocoupler that
provides regulation of primary side. The optocoupler is
supplied via direct connection to VOUT line through
resistor R1.
Regulation information is transferred through the
optocoupler to the primary side controller where its FB pin
is usually pulled down to reduce energy transferred to
secondary output.
The VSNS voltage divider is shared with VMIN voltage
divider. The shared voltage divider can be connected in two
ways as shown in Figure 23. The divider type is selected
based on the ratio between V
condition of Equation 1 is true, divider type 1 should be used.
Current regulation point is set to current given by
Equation 4.
VREFC
R11
IOUTLIM
+
(eq. 4)
OFF Mode Detection
OFF mode operation is advantageous for ultra low or zero
output current condition. The very long off time and the ultra
low power mode of the whole regulation system greatly
reduces the overall consumption.
The output voltage is varying between nominal and
minimal in OFF mode. When output voltage decreases
below set (except NCP4355A) minimum level, primary
controller is switch on until output capacitor C1 is charged
again to the nominal voltage.
The OFF mode detection is based on comparison of output
voltage and voltage loaded with fixed resistances (D2, C2,
R7 and R8). Figure 27 shows detection waveforms. When
output voltage is loaded with very low current, primary
controller goes into skip mode (primary controller stops
switching for some time). While output capacitor C1 is
discharged very slowly (no load condition), a fixed load R7
and R8 discharges the capacitor C2 faster than load current
discharges output voltage on C1.
and V
. When the
MIN
OUT
VOUT VREFM
V
MIN u
(eq. 1)
VREF
Output voltage for divider type 1 can be computed by
Equation 2
R4 ) R5 ) R6
V
OUT + VREF
(eq. 2)
R5 ) R6
and for type 2 by Equation 3.
R4 ) R5 ) R6
V
OUT + VREF
(eq. 3)
R6
Once OFFDET pin voltage is lower than V
(this
OFFDETTH
threshold is derived from V that is very close to V
),
OUT
CC
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10
NCP4355
OFF mode is detected. In OFF mode SW1 is switched off
and no I current is going through ON/OFF pin. The
Primary FB pin voltage is above regulation range until
is at set level. Once V is at set level, the secondary
V
OUT
ONOFF
OUT
primary controller’s REM pin voltage increases and primary
IC goes in to off mode.
controller starts to sink current from optocoupler LED’s and
primary FB voltage is stabilized in regulation region. With
nominal output power (without skip mode) OFFDET pin
I
current flow from VSNS pin to feedback divider
BIASV
is also activated when OFF mode is detected. This current
increases voltage at VSNS pin and due to it voltage OTA
sinks reduced current through regulation optocoupler. OTA
voltage is higher than V
(typically 10% of V ).
OFFDETTH CC
After some time, the load current decreases to low level
(5) and primary convertor uses skip mode (6) to keep
regulation of output voltage at set level and save some
energy. The skip mode consists of few switching cycles
followed by missing ones to provide limited energy by light
load. The number of missing cycles allows regulation for
any output power.
stops to sink current when VSNS voltage drops below V
.
REF
I
current disappears when VSNS voltage is lower than
BIASV
90% of V . This feature helps to avoid primary side
REF
switching when OFF mode is detected at secondary side and
primary side is waiting for correct information at REM pin.
While both C1 and C2 are discharged during the missing
cycles, C2 discharge will be faster than C1 without output
Minimum Output Voltage Detection (except NCP4355A)
Minimum output voltage level defines primary controller
restart from OFF mode. It can be set by shared voltage
divider with voltage regulation loop. When VMIN voltage
current, V
drops below V
and OFF mode
OFFDET
OFFDETTH
is detected (7). This situation is shown in Figure 27 in detail.
When OFF mode is detected, current into ONOFF pin stops
to flow (7) and voltage at primary REM pin increases over
threshold level that forces primary controller into OFF
drops below V , OFF mode is ended and primary
REFM
controller restarts.
NCP4355A has no external adjustment and uses the
internal minimum voltage level specified by minimum
falling operation supply voltage and special load detection
circuit for faster detection of load connection (T2, R16 and
R17 at Figure 24). Principe of load connection detection is
that when load is connected, output capacitor C1 is
discharged faster than C6 capacitor by IC supply current.
Voltage across D3 increases and when there is enough
voltage to open T2 some current is injected into OFFDET
mode. Internal pull−up current I
VSNS pin voltage increases (thanks to I
is switched on (7),
BIASV
) and voltage
BIASV
amplifier sinks reduced current at time (8), when VSNS is
higher than V (9), to keep primary FB voltage below
REF
switching level until REM pin voltage is high enough.
current stops when VSNS voltage drops below 90%
I
BIASV
of V
.
REF
Discharging of C1 continues (10) until output voltage
drops below level set by voltage divider at VMIN pin
(except NCP4355A where minimum V
divider. Voltage at OFFDET pin goes above 10% of V and
CC
is defined only
OUT
OFF mode ends. This circuit can also be used with B and C
versions to dramatically speed up wakeup time from OFF
mode. If this circuit is not used, it is necessary to wait for C6
discharge below VCC UVLO falling level before the
primary controller is restarted.
by VCC UVLO) (11). ONOFF current starts to flow,
primary REM voltage decreases and primary VCC voltage
is rising (12). Primary controller starts to operate, when
VCC voltage is enough and FB voltage is at regulation area
(13). Output capacitor C1 is recharged (14) to set voltage. If
there is still light load condition primary controller goes to
skip mode (15) again and after some time secondary
controller detects OFF mode by very light or no load
condition (16) and whole cycle is repeated.
LED Driver (except NCP4355C)
LED driver is active when VCC is higher than V
CCMIN
and output voltage is in regulation (it is off during OFF
mode). LED driver consists of an internal power switch
controlled by PWM modulated logic signal and an external
current limiting resistor R3. LED current can be computed
by Equation 5
Fast Restart From OFF Mode
The IC ends OFF mode when a load is connected to the
output and V
is discharged to V
level. There exists
OUT
MIN
V
OUT * VF_LED
another connection that allows transition to normal mode
faster without waiting some time for V to discharge to
ILED
+
(eq. 5)
R3
OUT
V
MIN
(it is necessary to use it with NCP4355A). This
PWM modulation is used to increase efficiency of LED.
schematic is shown at Figure 24 in dashed box. The basic
idea is that C6 is discharged by the IC faster than C1 by
output load in OFF mode. When an output load is applied,
capacitor C1 is discharged faster and this creates the voltage
drop at D3. When there is enough voltage at D3, T2 is
conducting and current is injected into the OFFDET divider
Operation in OFF Mode Description
Operation waveforms in off mode and transition into OFF
mode with primary controller are shown in Figure 28.
Figure shows waveforms from the first start (1) of the
convertor. At first, primary controller charges VCC
capacitor over the V
level (2). When primary V is
CCON
CC
through R16. OFFDET voltage higher than 10% of V
CC
over this level (3), primary controller starts to operate and
is slowly rising according to primary controller start
ends OFF mode and ON/OFF current starts to flow. Primary
controller leaves OFF mode because voltage at REM pin
increase above OFF mode detection threshold.
V
OUT
up ramp to nominal voltage (4). When V
VCC capacitor is charged from auxiliary winding.
is high enough,
OUT
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11
NCP4355
Normal operation waveforms for typical load detection
when load is connected during OFF mode. It can be seen that
connection and improved load detection waveforms are
shown in Figure 29. Figure 30 shows waveforms for
NCP4355A (without VMIN detection) in OFF mode and
the application is waiting not for low V
and then OFF mode is ended.
, but for low V
OUT CC
D4
VCC
D2
D1
D5
D6
C4
C2
R10
R9
D3
~VIN
C1
C7
VOUT
C3
C6
D7
D8
R4
C5
ISNS
VSNS
OPTO1
FBC
LED
VCC
R13
R1
R3
R12
R5
R15
T2
R16
T1
DRV
CS
HV
R11
VCC
LED1
VCC
R7
R8
R14
FB
REM
C8
ON/OFF
GND
GND
C9
OFFDET
R2
OPTO2
C10
OPTO1
NCP4355A
OPTO2
OPTIONAL FOR
OTHER VERSIONS
Figure 24. Typical Application Schematic for NCP4355A
D4
VCC
D2
D1
C2
D5
D6
D3
~VIN
C7
C1
VOUT
R9
C3
C6
C5
R4
D7
D8
OPTO1
FBC
LED
VCC
R13
R1
R3
T1
DRV
CS
HV
VCC
VSNS
VCC
R5
R6
LED1
R7
R14
OPTO2
FB
C8
OFFDET
VMIN
ON/OFF
GND
GND REM
R2
C10
OPTO1
NCP4355B
R8
C9
OPTO2
Figure 25. Typical Application Schematic for NCP4355B
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12
NCP4355
D4
VCC
D2
D1
D5
D6
C2
R10 C4
R9 C3
D3
~VIN
C1
C7
VOUT
R11
C6
R4
D7
D8
C5
OPTO1
FBC
VCC
ISNS
VSNS
R13
R1
R12
T1
HV
DRV
CS
VCC
VCC
R7
R5
R6
R14
ON/OFF
GND
FB
REM
C8
OPTO2
OFFDET
VMIN
GND
C9
R2
C10
OPTO1
NCP4355C
R8
OPTO2
Figure 26. Typical Application Schematic for NCP4355C
Normal operation
Skip
Off mode
Primary
Controller
Activity
Very low or no load detected,
off mode activated
V
OFFDET
10%
V (V
OUT CC
)
I
OUT
Figure 27. OFF Mode Detection
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13
NCP4355
Start up, I
nominal or low
Very low I
activates OFF mode with rarely C
charging
OUT
OUT
OUT
V
AUX
V
CCON
V
CC_Prim
Status
OFF
ON
ON
SKIP
OFF
V
FB_Prim
V
OUT
I
OUT
Max I
off mode
at
FBC
I
FBC
I
ONOFF
V
REM_prim
10% V
CC
V
OFFDET
I
switched on
BIASV
V
REF
V
SNS
MIN
I
BIASV
switched off
V
VMIN Threshold
1 kHz
12%
I
LED
1 kHz 12% wide
pulses
wide
pulses
Figure 28. Typical Application States and Waveforms in OFF Mode with Active On Primary Controller
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14
NCP4355
NO LOAD
LOAD IS CONNECTED
I
OUT
Primary side start delay
Secondary side detects low V
VMIN level
OUT
V
OUT
Vout is
discharged faster
V
CC
V
REMprim
Primary off mode ends
V
OFFDET
Typical load detection behavior
NO LOAD
LOAD IS CONNECTED
I
OUT
T2 is conducting
V
OUT
V
CC
VMIN level
Primary side start delay
V
REMprim
Primary off mode ends
V
OFFDET
Voltage delivered through T2 and R16
Improved load detection behavior
Figure 29. Typical and Improved Load Detection Comparison Waveforms
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15
NCP4355
LOAD IS CONNECTED
NO LOAD
I
OUT
Primary side start delay
Detection
delay
Secondary side detects low V
VCCmin level
CCmin
V
OUT
Vout is
discharged faster
V
CC
Primary side
start delay
V
REMprim
Primary off mode ends
V
OFFDET
Figure 30. Typical Load Detection of NCP4355A Without External Detection Circuit Waveforms
ORDERING INFORMATION
Adjustable
Current
LED
V
MIN
Regulation
Driver
Device
Marking
Package
Shipping
NCP4355ADR2G
NCP4355A
NCP4355B
NCP4355C
No
Yes
Yes
Yes
Yes
Yes
No
SOIC−8
2500 / Tape & Reel
(Pb−Free)
NCP4355BDR2G
NCP4355CDR2G
No
SOIC−8
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
Yes
SOIC−8
(Pb−Free)
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16
NCP4355
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP4355/D
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