NCP436 [ONSEMI]
3A Ultra-Small Controlled Load Switch;
| 型号： | NCP436 |
| 厂家： | 
ONSEMI |
| 描述： | 3A Ultra-Small Controlled Load Switch |
| 文件： | 总7页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP436, NCP437
3A Ultra-Small Controlled
Load Switch with
Auto-Discharge Path
The NCP436 and NCP437 are very low Ron MOSFET controlled
by external logic pin, allowing optimization of battery life, and
portable device autonomy.
Indeed, due to a current consumption optimization with PMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output rail for the NCP437 part only.
Proposed in a wide input voltage range from 1.0 V to 3.6 V, in a
small 1 x 1.5 mm WLCSP6, pitch 0.5 mm.
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MARKING DIAGRAM
XXX
AYW
G
WLCSP6
CASE 567FH
A
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Y
W
G
Features
• 1.0 V − 3.6 V Operating Range
• 20 mW P MOSFET at 3.6 V
• DC Current Up to 3 A
• Output Auto−discharge
• Active High EN Pin
PIN DIAGRAM
A
B
C
OUT
OUT
IN
IN
• WLCSP6 1 x 1.5 mm
• These are Pb−Free Devices
Typical Applications
• Mobile Phones
• Tablets
• Digital Cameras
• GPS
• Portable Devices
GND
EN
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
V+
LS
NCP437
DCDC Converter
A2
A1
Platform IC’n
IN
IN
OUT
OUT
or
B2
C2
B1
LDO
EN
ENx
EN
0
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
April, 2014 − Rev. 1
NCP436/D
NCP436, NCP437
PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2, B2
POWER
Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC.
GND
EN
C1
C2
POWER
INPUT
Ground connection.
Enable input, logic high turns on power switch.
OUT
A1, B1
OUTPUT
Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
BLOCK DIAGRAM
IN: Pin A2, B2
OUT: Pin A1, B1
Gate driver and soft
start control
Control
logic
EN: Pin C2
Optional: NCP437
EN block
GND: Pin C1
Figure 2. Block Diagram
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2
NCP436, NCP437
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
V
V
OUT
EN , IN,
V
IN, OUT, EN, Pins: (Note 1)
−0.3 to + 4
V
V
IN ,
From IN to OUT Pins: Input/Output (Note 1)
0 to + 4
V
V
OUT
T
Maximum Junction Temperature
−40 to + 125
8000
°C
J
ESD
HBM
Human Body Model (HBM) ESD Rating are (Notes 2 and 3)
V
ESD MM
Machine Model (MM) ESD Rating are (Notes 2 and 3)
250
V
V
ESD
Charge Device Model (CDM) ESD Rating are (Notes 2 and 3)
2000
CDM
LU
Latch−up Protection (Note )
− Pins IN, OUT, EN
100
mA
T
Storage Temperature Range
Moisture Sensitivity (Note 2)
−40 to + 150
Level 1
°C
STG
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
3. This device series contains ESD protection and passes the following tests
Human Body Model (HBM) 8.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) 250 V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM) 2.0 kV per JEDEC standard: JESD22−C101 for all pins.
4. Latch−up Current Maximum Rating: 100 mA per JEDEC standard: JESD78 Class II.
OPERATING CONDITIONS
Symbol
Parameter
Operational Power Supply
Enable Voltage
Conditions
Min
1.0
0
Typ
Max
3.6
Unit
V
IN
V
V
EN
3.6
T
Ambient Temperature Range
Junction Temperature Range
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction to Air
Maximum DC current
−40
−40
1
25
25
+85
+125
°C
°C
A
T
J
C
mF
mF
°C/W
A
IN
C
1
OUT
R
WLCSP package (Note 5)
100
q
JA
I
3
OUT
P
D
Power Dissipation Rating (Note 6)
T
≤ 25°C
WLCSP package
WLCSP package
0.66
0.26
W
A
T = 85°C
A
W
5. The R
is dependent of the PCB heat dissipation and thermal via.
q
JA
6. The maximum power dissipation ( ) is given by the following formula:
PD
TJMAX * TA
PD
+
RqJA
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3
NCP436, NCP437
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for T between −40°C to +85°C for
between 1.0 V to 3.6 V
VIN
A
(Unless otherwise noted). Typical values are referenced to T = +25°C and V = 3.3 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POWER SWITCH
I = 200 mA, 25°C
15
26
28
29
30
32
35
40
42
44
80
84
85
I = 200 mA, T = 85°C
V
V
V
= 3.6 V
= 2.5 V
= 1.8 V
= 1.2 V
A
IN
IN
IN
IN
T = 125°C
J
I = 200 mA, 25°C
18
23
45
I = 200 mA, T = 85°C
A
T = 125°C
J
Static drain−source on−state
resistance
I = 200 mA, 25°C
R
mW
DS(on)
I = 200 mA, Full Ta
T = 125°C
J
I = 200 mA, 25°C
I = 200 mA, Full Ta
V
T = 125°C
J
V
= 1.1 V
= 3.3 V
I = 200 mA, 25°C
62
65
IN
IN
R
Output discharge path
High−level input voltage
Low−level input voltage
V
EN = low
50
90
W
dis
V
1.1
IH
V
V
0.5
IL
QUIESCENT CURRENT
I
Standby current
V
V
= 3.3 V
= 3.3 V
EN = low, No load
EN = high, No load
0.01
0.2
0.6
0.6
std
IN
mA
Iq
Quiescent current
IN
TIMINGS
T
Enable time
R = 25 W, C
= 1 mF
= 1 mF
= 1 mF
= 1 mF
20
10
30
39
25
64
20
55
40
95
EN
L
OUT
OUT
OUT
OUT
T
Output rise time
R = 25 W, C
L
R
T
ON
ON time (T
T )
R
R = 25 W, C
L
V
= 3.6 V
(Note 8)
EN +
IN
ms
T
DIS
Disable time
R = 25 W, C
L
NCP437. R = 25 W,
L
T
F
Output fall time
20
55
80
C
= 1 mF
OUT
7. Guaranteed by design and characterization
8. Parameters are guaranteed for C and R
connected to the OUT pin with respect to the ground
LOAD
LOAD
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4
NCP436, NCP437
TIMINGS
V
IN
EN
V
OUT
T
T
F
T
T
R
DIS
EN
T
OFF
T
ON
Figure 3. Enable, Rise and Fall Time
FUNCTIONAL DESCRIPTION
Overview
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path (Pull down NMOS) stays activated as
The NCP437 is a high side P channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 1.0 V to 3.6 V.
long as EN pin is set at low level and V > 1.2 V.
IN
In order to limit the current across the internal discharge
N−MOSFET, the typical value is set at 65 W.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
CIN and COUT Capacitors
IN and OUT, 1 mF, at least, capacitors must be placed as
close as possible the part to for stability improvement.
The IN/OUT path is activated with a minimum of V of
IN
1.2 V and EN forced to high level.
Auto Discharge
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
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5
NCP436, NCP437
APPLICATION INFORMATION
Power Dissipation
TJ + RD RqJA ) TA
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
T
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
J
R
T
qJA
A
PCB Recommendations
Ǔ2
The NCP437 integrates an up to 3 A rated PMOS FET, and
the PCB design rules must be respected to properly evacuate
the heat out of the silicon. By increasing PCB area,
ǒ
PD + RDS(on) IOUT
P
D
= Power dissipation (W)
especially around IN and OUT pins, the R
of the package
R
I
= Power MOSFET on resistance (W)
= Output current (A)
qJA
DS(on)
OUT
can be decreased, allowing higher power dissipation.
Routing example: 2 oz, 4 layers with vias across two
internal inners.
Figure 4.
Example of application definition.
At 3 A, 25°C ambient temperature, R
20 mW @ V
DS(on IN
5 V, the junction temperature will be:
2
T
* T + R
P + R
R
I
DS(on)
J
A
qJA
D
qJA
2
Ǔ
+ 25 ) ǒ0.02 3
P
D
T
+ R
100 + 43° C
J
qJA
T : Junction Temperature.
J
T : Ambient Temperature.
A
Taking into account of R obtain with:
q
R = Thermal resistance between IC and air, through PCB.
• 2 oz, 4 layers: 60°C/W.
q
R : Intrinsic resistance of the IC MOSFET.
DS(on)
At 3 A, 65°C ambient temperature, R
5 V, the junction temperature will be:
24 mW @ V
IN
DS(on)
I: Load DC current.
Taking into account of R obtain with:
• 1 oz, 2 layers: 100°C/W.
2
Ǔ
q
+ 65 ) ǒ0.024 3
+ T ) R P
D
T
60 + 78° C
q
J
A
ORDERING INFORMATION
†
Device
Marking
Option
Package
Shipping
NCP437FCT2G
AR
Auto discharge
WLCSP 1 x 1.5 mm
(Pb−Free)
3000 / Tape & Reel
NCP436FCT2G
AQ
Without Auto discharge
WLCSP 1 x 1.5 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NCP436, NCP437
PACKAGE DIMENSIONS
WLCSP6, 1.00x1.50
CASE 567FH
ISSUE O
D
A
NOTES:
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
MILLIMETERS
DIM
A
A1
A2
b
D
E
e
MIN
0.54
0.22
0.33 REF
0.29
1.00 BSC
1.50 BSC
0.50 BSC
MAX
0.63
0.28
2X
0.05
0.05
C
0.34
2X
C
TOP VIEW
A2
0.05
C
RECOMMENDED
SOLDERING FOOTPRINT*
A
PACKAGE
OUTLINE
0.05
C
A1
A1
SEATING
PLANE
NOTE 3
C
SIDE VIEW
eD/2
eD
6X
b
eE
0.50
PITCH
0.05
0.03
C
C
A B
6X
0.25
C
0.50
PITCH
DIMENSIONS: MILLIMETERS
B
A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
2 3
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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NCP436/D
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