NCP5425DBR2 [ONSEMI]
Dual Synchronous Buck Controller; 双路同步降压控制器
| 型号： | NCP5425DBR2 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Synchronous Buck Controller |
| 文件： | 总22页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5425
Dual Synchronous
Buck Controller
The NCP5425 is a highly flexible dual buck controller with internal
gate drivers that can be used with two input power supplies and one or
two outputs in multiple configurations. The part contains all the
circuitry required for two independent synchronous dual NFET buck
regulators utilizing a feed forward voltage mode control method. The
NCP5425 can run from a single supply ranging from 4.6 to 12 volts
and support a single two phase or dual single phase outputs. When
used as a dual output controller, the second output tracks voltage
transients from the first. Power blanking for low noise applications is
supported as well as independent cycle−by−cycle current limiting. The
part is available in a 20 pin TSSOP package allowing the designer to
minimize PCB area.
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TSSOP−20
DB SUFFIX
CASE 948E
20
1
PIN CONNECTIONS AND
MARKING DIAGRAM
Features
• Operation Over 4.6 to 13.2 Volts
• Dual Synchronous Buck Design
20
1
GATEH1
GATEL1
GATEH2
GATEL2
• Configurable as a Single Two Phase Output or Two Single Phase
Outputs
GND
BST
NC
NC
IS+1
IS−1
V
R
CC
NCP
5425
AWLYWW
OSC
• Programmable Power Sharing and Budgeting from Two Independent
Supplies
MODE
IS−2
IS+2
V
V
• 0.8 Volt "1% Reference for Low Voltage Outputs
• 1.5 A Peak Power Drive
REF2
V
FB1
FB2
COMP1
COMP2
• Switch Blanking for Noise Sensitive Applications through use of
R
OSC
Pin
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
• Programmable Frequency, 150 kHz to 750 kHz Operation
• Programmable Soft Start
• Cycle−by−Cycle Overcurrent Protection
• Independent Programmable Current Limits
• 100% Duty Cycle for Fast Transient Response
• Internal Slope Compensation
Y
ORDERING INFORMATION
†
Device
Package
Shipping
61 Units/Rail
• Out−of−Phase Synchronization between the Controllers
• Input Undervoltage Lockout
NCP5425DB
TSSOP−20
TSSOP−20
2500 Units/Reel
NCP5425DBR2
• On/Off Enable through use of the COMP Pins
• Power Supply Sequencing
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• DDR Memory Power
• Graphics Cards
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
January, 2005 − Rev. 6
NCP5425/D
NCP5425
12 V
3.3 V
+
C1
220 µF
5 V
+
C12
220 mF
C6
C10
C11
0.1 mF
1 mF
1 mF
R1
R2
1.5 V/
10 A
NTD60N02R
Q3
NTD60N02R
Q1
1.8 V/
5 A
4 k
4 k
L2
20
1
L1
1.3 mH
GATE(H)1 GATE(H)2
NTD110N02RT4
Q4
NTD110N02RT4
Q2
1.3 mH
C14
+
680 mF2
+
C3
680 mF1
19
14
15
2
GATE(L)1
IS+1
GATE(L)2
IS+2
7
4K
R11
C9
IS−2
13
R9
0.4 k
V
REF2
R3
0.4 k
0.1 mF
8
IS−1
11
COMP2
R7
5 k
10
COMP1
C8
0.1 mF
C7
0.1 mF
12
17
V
FB2
R5
9
V
FB1
R
OSC
3.5 k
R8
4 k
R10
18 k
R12
30.9 k
R4
15 k
R6
4 k
Figure 1. Application Diagram, 3.3 V to 1.5 V/10 A and 1.8 V/5.0 A Converter
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2
NCP5425
MAXIMUM RATINGS
Rating
Value
150
Unit
°C
°C
kV
V
Operating Junction Temperature, T
J
Storage Temperature Range, T
−65 to 150
2.0
J
ESD Susceptibility (Human Body Model)
ESD Susceptibility (Machine Model)
Moisture Sensitivity Level (MSL)
Lead Temperature Soldering:
200
1
Reflow: (Note 1)
260 peak
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 to 150 seconds maximum above 183°C, 260°C peak.
MAXIMUM RATINGS
Pin Symbol
Pin Name
V
MAX
V
MIN
I
I
SINK
SOURCE
V
IC Power Input
16 V
4.0 V
6.0 V
−0.3 V
−0.3 V
−0.3 V
N/A
2.0 A Peak
200 mA DC
CC
COMP1, COMP2
Compensation Capacitor for
Channel 1 or 2
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
V
FB1
, V , V
FB2 REF2
Voltage Feedback Input for
Channel 1 or 2
R
Oscillator Resistor
5.0 V
20 V
−0.3 V
−0.3 V
OSC
GATE(H)1 GATE(H)2
High−Side FET Driver
for Channel 1 or 2
2.0 A Peak
200 mA DC
2.0 A Peak
200 mA DC
,
GATE(L)1 GATE(L)2
Low−Side FET Driver for
Channel 1 or 2
16 V
6.0 V
6.0 V
100 mV
20 V
−0.3 V
−0.3 V
−0.3 V
0 V
2.0 A Peak
200 mA DC
2.0 A Peak
200 mA DC
,
IS+1, IS+2
IS−1, IS−2
GND
Positive Current Sense for
Channel 1 or 2
1.0 mA
1.0 mA
1.0 mA
N/A
Negative Current Sense for
Channel 1 or 2
1.0 mA
Ground
2.0 A Peak
200 mA DC
BST
Power Input for GATE(H)1
GATE(H)2
−0.3 V
−0.3 V
N/A
2.0 A Peak
200 mA DC
MODE
Dual or Single Output Select
3.5 V
N/A
N/A
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3
NCP5425
ELECTRICAL CHARACTERISTICS (0°C < T < 125°C; R
= 30.9 k, C
= 0.1 µF, 4.75 V < V
< 13.2 V; 10.8 V
CC
J
OSC
COMP1,2
< BST < 20 V, C
= C
= 1.0 nF; unless otherwise specified.)
GATE(L)1,2
GATE(H)1,2
Characteristic
Error Amplifier
Test Condition
Min
Typ
Max
Unit
V
Input Bias Current
V
V
= 0 V
−
−
0.1
0.1
−
1.0
1.0
mA
mA
V
FB1
FB2
FB1
V
, V
REF2
Input Bias Current
, V
REF2
= 0.8 V
FB2
Input Voltage Range
COMP1(2) Source Current
COMP1(2) Sink Current
Reference Voltage
−
0.3
15
1.9
COMP1(2) = 1.2 V to 2.5 V; V
= 0.6 V
30
60
mA
mA
V
FB1(2)
COMP1(2) = 1.2 V; V
= 1.0 V
15
30
60
FB1(2)
COMP1 = V
0.792
0.800
0.808
FB1
COMP1 Max Voltage
COMP2 Max Voltage, Mode Floating
COMP2 Max Voltage, Mode = 0
V
FB1(2)
V
FB1(2)
V
FB1(2)
= 0.6 V
= 0.6 V
= 0.6 V
−
3.0
−
2.0
3.1
2.0
2.1
−
2.1
V
COMP1(2) Min Voltage
Open Loop Gain
V
= 1.2 V
−
−
−
−
−
−
0.10
95
0.20
−
V
dB
FB1(2)
Unity Gain Bandwidth
PSRR @ 1.0 kHz
40
−
kHz
dB
70
−
Transconductance
Output Impedance
GATE(H) and GATE(L)
High Voltage (AC)
−
32
−
mmho
MΩ
−
2.5
−
V
CC
− GATE(L)1,2
−
0
0.5
V
BST − GATE(H)1,2 (Note 2)
Low Voltage (AC)
Rise Time
GATE(L)1,2 or GATE(H)1,2 (Note 2)
−
−
0
0.5
80
V
1.0 V < GATE(L)1,2 < V − 1.0 V
25
ns
CC
1.0 V < GATE(H)1,2 < BST − 1.0 V
Fall Time
V
− 1.0 > GATE(L)1,2 > 1.0 V
−
25
40
80
80
ns
ns
ns
kΩ
CC
BST − 1.0 > GATE(H)1,2 > 1.0 V
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE(H)1,2 < 2.0 V
GATE(L)1,2 > 2.0 V
20
20
50
GATE(L)1,2 < 2.0 V
GATE(H)1,2 > 2.0 V
40
80
GATE(H)1(2) and GATE(L)1(2) Pull−Down
PWM Comparator
Resistance to GND (Note 2)
125
280
Propagation Delay
COMP1(2) = 1.0 V
−
200
300
ns
V
V
FB1(2)
= 0 to 1.2 V
Note 2
PWM Comparator Offset
V
FB1(2)
= 0 V; Increase COMP1(2) until
GATE(H)1(2) starts switching
0.20
55
−
0.30
95
0.45
150
130
Artificial Ramp
Duty Cycle = 50%
(Note 2)
mV
ns
Minimum Pulse Width
80
2. Guaranteed by design, not 100% tested in production.
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4
NCP5425
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 125°C; R
= 30.9 k, C
= 0.1 µF, 4.75 V < V
<
CC
J
OSC
COMP1,2
13.2 V; 10.8 V < BST < 20 V, C
= C
= 1.0 nF; unless otherwise specified.)
GATE(L)1,2
GATE(H)1,2
Characteristic
Test Condition
Min
Typ
Max
Unit
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
R
= 61.9 k; Measure GATE(H)1
= 30.9 k; Measure GATE(H)1
= 11.8 k; Measure GATE(H)1
= 30.9 k
112
224
562
150
300
750
1.000
180
3.1
188
376
938
1.030
−
kHz
kHz
kHz
V
OSC
OSC
OSC
OSC
R
R
R
R
Voltage
0.970
OSC
Phase Difference
−
−
−
°
Low Noise Disable
Guaranteed By Design
3.5
V
Overcurrent Protection
OVC Comparator Offset Voltage
0 V < IS+1(2) < 5.5 V
0 V < IS−1(2) < 5.5 V
55
70
85
mV
IS+1(2) Bias Current
IS−1(2) Bias Current
0 V < IS+1(2) < 5.5 V
0 V < IS−1(2) < 5.5 V
−1.0
−1.0
0.1
0.1
1.0
1.0
mA
mA
OVC Common Mode Range
−
0
−
5.5
V
Supply Currents
V
Current
COMP = 0 V (No Switching)
COMP = 0 V (No Switching)
−
−
16
22
mA
mA
CC
BST Current
3.5
6.0
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1(2) Charging
3.8
3.6
4.2
4.0
4.6
4.4
V
V
Stop Threshold
GATE(H) Not Switching; COMP1(2)
Discharging
Hysteresis
Start−Stop
0.1
0.2
0.25
V
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NCP5425
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
GATE(H)1
GATE(L)1
GND
Description
1
2
High Side Switch FET driver pin for the channel 1 FET.
Low Side Synchronous FET driver pin for the channel 1 FET.
Ground. All circuits are referenced to this pin. IC substrate connection.
Power input for GATE(H)1 and GATE(H)2 pins.
No connection.
3
4
BST
5
NC
6
NC
No connection.
7
IS+1
Positive input for channel 1 overcurrent comparator.
Negative input for channel 1 overcurrent comparator.
Error amplifier inverting input for channel 1.
8
IS−1
9
V
FB1
10
COMP1
COMP2
Channel 1 Error Amp output. PWM comparator reference input. A capacitor to GND provides Error
Amp compensation. The same capacitor provides soft−start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.2 V.
11
Channel 2 Error Amp output. PWM comparator reference input. A capacitor to GND provides Error
Amp compensation and soft−start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.2 V.
12
13
14
15
16
V
Error amplifier inverting input for channel 2.
FB2
V
REF2
Error amplifier noninverting input for channel 2.
Positive input for channel 2 overcurrent comparator.
Negative input for channel 2 overcurrent comparator.
IS+2
IS−2
MODE
Input pin used to inform internal circuitry of dual output or single output operation. Ground this pin for
dual output operation, leave open for single output operation.
17
18
19
20
R
A resistor from this pin to ground sets switching frequency.
Input Power supply pin. Power input for GATE(L)1 and GATE(L)2 pins.
Low Side Synchronous FET driver pin for the channel 2 FET.
High Side Switch FET driver pin for the channel 2 FET.
OSC
V
CC
GATE(L)2
GATE(H)2
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6
NCP5425
IRAMP1
IRAMP2
OSCILLATOR
AND
3.1 V
CLK1
CLK2
R
OSC
RAMP
CURRENT
GENERATOR
IRAMP1
RAMP1
BST
LNDM
Low noise disable mode
(pull R
high to activate)
OSC
3.1 V
REFERENCE
AND BIAS
RAMP1
0.8 V
0.3 V
+
GATE(H)1
GATE(L)1
CLK1
LNDM
LNDM
3.1 V
Q
S
Reset
Dominant
−
+
PWM
COMP1
V
CC
+
R
Q
V
FB1
−
−
+
−
0.8 V
EA1
+
−
COMP1 CLAMP
REFERENCE
IS+1
IS−1
+
OC1
OC2
−
+
70 mV
−
COMP1
IS+2
IS−2
+
−
UVLO
−
+
V
CC
−
+
UVLO
70 mV
RAMP2
+
BST
−
4.2 V
4.0 V
0.3 V
+
GATE(H)2
CLK2
LNDM
3.1 V
Q
S
Reset
Dominant
−
+
PWM
COMP2
V
CC
+
R
Q
LNDM
−
V
−
+
FB2
GATE(L)2
GND
−
V
REF2
EA2
3.1 V
3.1 V
3.1 V
IRAMP2
COMP2
3.1 V
RAMP2
UVLO
S/D
Single
or dual
output
mode
COMP2
CLAMP
REFERENCE
MODE
Figure 2. Block Diagram
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7
NCP5425
APPLICATIONS INFORMATION
Theory of Operation
the main switch. The comparator response time and the
transition speed of the main switch determine the load
transient response. Unlike traditional control methods, the
reaction time to the output load step is not related to the
crossover frequency of the error signal loop. The error signal
loop can have a low crossover frequency, since the transient
response is handled by the ramp signal loop. The main
purpose of this ‘slow’ feedback loop is to provide DC
accuracy. Noise immunity is significantly improved, since
the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote
sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered. Line and
load regulation are drastically improved because there are
two independent control loops. A voltage mode controller
relies on the change in the error signal to compensate for a
deviation in either line or load voltage. This change in the
error signal causes the output voltage to change
corresponding to the gain of the error amplifier, the
consequence of which is normally specified as line or load
regulation. A current mode controller maintains a fixed error
signal during line transients, since the slope of the ramp
signal changes in this case. However, regulation of load
The NCP5425 is a very versatile buck controller using
t
2
V
control method. It can be configured as:
• Dual output Buck Controller.
• Two phase Buck Controller with current limit.
• Two phase Buck Controller with input power ratio and
current limit.
The fixed−frequency architecture, driven from a common
oscillator, ensures a 180° phase differential between
channels.
V2 Control Method
2
The V method of control uses a ramp signal generated by
the ESR (Effective Series Resistance) of the output
capacitors. This ramp is proportional to the AC current
through the main inductor and is offset by the DC output
voltage. This control scheme inherently compensates for
variation in either line or load conditions, since the ramp
2
signal is generated from the output voltage itself. The V
method differs from traditional techniques such as voltage
mode control, which generates an artificial ramp, and
current mode control, which generates a ramp using the
inductor current.
2
transients still requires a change in the error signal. The V
method of control maintains a fixed error signal for both line
and load variation, since the ramp signal is affected by both
line and load.
PWM
GATE(H)
GATE(L)
−
+
The stringent load transient requirements of modern
power supplies require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple
can lead to pulse width jitter and variation caused by both
random and synchronous noise. A ramp waveform
generated in the oscillator is added to the ramp signal from
the output voltage to provide the proper voltage ramp at the
beginning of each switching cycle. This slope compensation
increases the noise immunity, particularly at higher duty
cycle (above 50%).
RAMP
Output
Voltage
Slope
Compensation
Error
Amplifier
V
FB
−
+
COMP
Reference
Voltage
Error Signal
Start Up
The NCP5425 features a programmable soft start
function, which is implemented through the error amplifier
and external compensation capacitor. This feature reduces
stress to the power components and limits overshoot of the
output voltage, during startup. As power is applied to the
regulator, the NCP5425 Undervoltage Lockout circuit
Figure 3. V2 Control with Slope Compensation
2
The V control method is illustrated in Figure 3. The
output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch to 0% or 100% duty cycle as required.
A variation in line voltage changes the current ramp in the
(UVLO) monitors the IC’s supply voltage (V ). The
CC
UVLO circuit prevents the MOSFET gates from switching
until V
exceeds 4.2 V. Internal UVLO threshold
CC
hysteresis of 200 mV improves noise immunity. During start
up, the external Compensation Capacitor connected to the
COMP pin is charged by an internal 30 mA current source.
When the capacitor voltage exceeds the 0.3 V offset of the
PWM comparator, the PWM control loop will allow
switching to occur. The upper gate driver GATE(H) is now
activated, turning on the upper MOSFET. The output current
then ramps up through the main inductor and linearly
powers the output capacitors and load. When the regulator
2
inductor, which causes the V control scheme to compensate
the duty cycle. Since any variation in inductor current
modifies the ramp signal, as in current mode control, the V
control scheme offers the same advantages in line transient
response. A variation in load current will affect the output
voltage, modifying the ramp signal. A load step immediately
changes the state of the comparator output, which controls
2
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8
NCP5425
Transient Response
output voltage exceeds the COMP pin voltage, minus the
0.3 V PWM comparator offset threshold and the artificial
ramp, the PWM comparator terminates the initial pulse.
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage or
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, a combination of
several high frequency and bulk output capacitors are
typically used.
V
IN
4.2 V
V
COMP
V
FB
0.3 V
Out−of−Phase Synchronization
GATE(H)1
GATE(H)2
The turn−on of the second channel is delayed by half the
switching cycle. This delay is supervised by the oscillator,
which supplies a clock signal to the second channel that is
180° out of phase with the clock signal of the first channel.
Advantages of out−of−phase synchronization are many.
Since the input current pulses are interleaved with one
another, the overlap time is reduced. Overlap reduction
reduces the input filter requirement, allowing the use of
smaller components. In addition, since peak current occurs
during a shorter time period, emitted EMI is also reduced,
potentially reducing shielding requirements. Interleaving
the phases in a two phase application reduces ripple voltage
and allows supplies with tighter tolerances to be built.
UVLO STARTUP
NORMAL OPERATION
t
s
Figure 4. Idealized Start Up Waveforms
Normal Operation
During normal operation, the duty cycle remains
approximately constant as the V control loop maintains
regulated output voltage under steady state conditions.
Variations in supply line or output load conditions will result
in changes in duty cycle to maintain regulation.
2
Overvoltage Protection
Gate Charge Effect on Switching Times
Overvoltage Protection (OVP) is provided as
a
When using the on board gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading,
according to the following graphs.
2
consequence of the normal operation of the V control
method, and requires no additional external components to
implement. The control loop responds to an overvoltage
condition within 200 ns, turning off the upper MOSFET and
disconnecting the regulator from its input voltage. This
results in a crowbar action to clamp the output voltage,
preventing damage to the load. The regulator remains in this
state until the overvoltage condition clears.
90
80
70
Low Noise Disable Mode
Average Rise Time
A PWM converter operating at a constant frequency
concentrates its noise output over a small frequency band. In
noise−sensitive applications, this frequency can be chosen
to prevent interference with other system functions. Some
applications may have even more stringent requirements,
where absolutely no noise may be emitted for a short period
of time.
60
50
40
Average Fall Time
30
20
10
0
The user may disable the clock during noise sensitive
periods to temporarily inhibit switching noise by
0
0
2
3
4
5
6
7
8
disconnecting or pulling the R
pin to 3.3 V. This disables
OSC
both gate drivers, leaving the switch node floating, and
discharges the internal ramp.
The control circuitry remains enabled while the clock and
drivers are disabled, so the COMP pins will charge up to a
higher voltage. The COMP pins are clamped to prevent
excessive overshoot when switching is resumed.
LOAD (nF)
Figure 5. Average Rise and Fall Times
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NCP5425
Current Sharing
Channel 1 is connected to the reference input of the Channel
2 error amplifier. Current information from Channel 2 is fed
back to the error amplifier’s inverting input. Channel 2 will
therefore act to adjust its current to match the current
information fed to its reference input from Channel 1. If this
information is one−half the voltage developed across the
Channel 1 output inductor, Channel 2 will run at half the
current and supply a approximately 33% of the total load
current. This application is illustrated in Figure 7.
When used in a two separate input to a single output mode,
the NCP5425 dual controller can provide input power
sharing in either of two ways:
• A preset ratio. For example, Channel 1 could provide
70% of the load current, and Channel 2, the remaining
30%. Practical ratios for Channel 1/Channel 2
contribution to total load current range from 50%−50%
to 80%−20%.
In some applications the power supply designer may not
only wish to draw a known percentage of power from one
source, but also limit the power drawn from that source. The
current limit amplifier on Channel 2 can be programmed to
budget the maximum input power into Channel 2 and all
power in excess of that limit will be supplied solely by
Channel 1. This is accomplished by setting the Channel 2
cycle−by−cycle current limit in conjunction with
programming the current ratio as described above.
• A preset ratio up to a specific current contribution from
Channel 2. In excess of that limit, all of the additional
load current would be supplied by Channel 1. Figure 7
depicts the actual performance of a NCP5425
configured in a 70%−30% share ratio, with Channel 2
output current limited to 5.0 Amps.
The availability both Channel 2 error amplifier inputs
(signal and reference) at device pins is key to programmable
current ratio sharing. Current sense information from
V
V
in
in
Q1
Q2
Q3
Q4
L1
L2
V
out
R3
R4
R1
R
C3
C
C2
C
R2
R
R
C1
C
Master
Slave
Error Amp
V
V
FB2
Error Amp
R
FB1
−
+
−
+
U2
U2
V
REF2
Internal
Reference
0.8 V
Figure 6. Two Phase Current Sharing Circuit
14.00
12.00
10.00
8.00
Channel 1 output current
share begins to increase
Iout(1)
Channel 2 output current
begins to level off at 5
Amps
6.00
Iout(2)
4.00
Iin(1)
Iin(2)
2.00
0.00
0
5
10
15
20
TOTAL OUTPUT CURRENT, AMPS
Figure 7. 70%/30% Current Sharing with Channel 2 Current Limiting
NOTE: Channel 1 input voltage = Channel 2 input voltage = 5.0 V
Output voltage = 1.5 V
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NCP5425
Inductor Current Sensing
current sense signal will have the same wave shape as the
inductor current and the voltage signal on C1 will represent
the instantaneous value of inductor current. The voltage
across C1 can be used as though it were a sense resistor with
the same value as the inductor’s ESR, thus avoiding a sense
resistor’s power loss.
Examples of lossless current sensing across an output
inductor are shown in Figure 8. Lx is the output inductance
and Rx represents its equivalent series resistance. To
compensate the current sense signal, the values of R1 and C1
are chosen so that Lx/Rx = R1 x C1. With these values, the
Switch
Node
Switch
Node
R1
C1
R1
Lx
Lx
+ls
−ls
+ls
Rx*I *R2
+
+
Rx
Rx
L
Rx X I
−
C1
R2
L
(R1 + R2)
_
_
+
+
−
−ls
DC
DC
70 mV
70 mV
Output
Output
(8A)
(8B)
Switch
Node
Switch
Node
R1
C1
R1
Lx
Lx
+ls
−ls
+ls
+
+
Rx
Rx
(Rx*I ) + (E
)
L
R3
Rx X I
−
C1
L
_
_
+
+
−
−ls
DC
Output
R3
R3
DC
Output
R4
70 mV
70 mV
E
R3
= (Vo*R3)/R3 + R4)
(8C)
(8D)
Figure 8. Inductor Current Sensing − Circuit Configurations
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NCP5425
Figure 8A − Basic Current Sensing
Figure 8D – Decreasing the Current Threshold
Represents a basic inductor sensing configuration. When
the voltage at pin +Is exceeds the voltage at pin –Is by 70 mV
(nominal), the internal current sense comparator offset will
be overcome. For this case, the current limit threshold is
equal to (70 mV/Rx) amps. An obvious disadvantage of the
basic configuration is the power supply designer has no
control over the 70 mV offset, and limited control over the
value of Rx. Therefore, he or she has little flexibility to set
a specific current limit. Configurations (8B) and (8D) depict
techniques to increase and decrease, respectively, the
threshold current.
A voltage divider comprised of R3 and R4 is introduced
to develop, by scaling the output voltage, a small voltage
drop across R3 that opposes the internal current sense
comparator offset. For example, if Vout = 1.2 V, R3 = 200 W,
and R4 = 11.8 K, a DC voltage drop of 20 mV will be
established across R3. The polarity of that voltage is such
that it opposes the internal 70 mV offset, effectively
reducing it to 50 mV. The current threshold is now given by
(50 mV/Rx) instead of (70 mV/Rx).
Current Limiting
Both channels of the NCP5425 employ identical
Cycle−by−Cycle current limiting. Comparators with
internal 70 mV offsets provide the references for setting
current limit. Once a voltage greater than 70 mV is applied
to the current limiting comparator, it resets that channel’s
output RS flip flop. This terminates the PWM pulse for the
cycle and limits the energy delivered to the load. One
advantage of this current limiting scheme is that the
NCP5425 will limit large transient currents yet resume
normal operation on the following cycle. A second benefit
of limiting the PWM pulse width is, in an input power
sharing application, one controller can be current limiting
while the other supplies the remaining load current.
Figure 8B – Increasing the Current Threshold
Addition of resistor R2 forms a voltage divider such that
only a portion of the voltage across Rx appears across C1.
If, for example, R1 = R2, it will require a 140 mV drop
across Rx to overcome the internal 70 mV current sense
comparator offset. For optimum compensation with this
configuration, R1 and R2 should be selected such that Rx is
equal to their equivalent parallel resistance.
Figure 8C – Bias Current Compensation
Configurations 8A, 8B and 8D all introduce a potential
error, since the bias currents of the current sense comparator
inputs flow through unbalanced resistance paths. The
addition of R3 in configuration 8C, where R3 = R1, restores
a balanced input resistance, such that any voltage drops
introduced by bias currents will cancel (assuming the +Is
and –Is bias currents are equal). In the case of configuration
8B, R3 would be made equal to the equivalent resistance of
R1 and R2 in parallel.
Output Enable
On/Off control of the regulator outputs can be
implemented by pulling the COMP pins low. Driving the
COMP pins below the 0.20 V PWM comparator offset
voltage disables switching of the GATE drivers.
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NCP5425
Calculating Duty Cycle
DESIGN GUIDELINES
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
General
The output voltage tolerance can be affected by any or all
of the following:
V
) (V
) V )
L
OUT
) V
HFET
+ V
Duty Cycle + D +
V
+ V
L
IN
LFET
HFET
1. Buck regulator output voltage set point accuracy.
2. Output voltage change due to discharging or
charging of the bulk decoupling capacitors during
a load current transient.
3. Output voltage change due to the ESR and ESL of
the bulk and high frequency decoupling capacitors,
circuit traces, and vias.
where:
V
V
= buck regulator output voltage;
OUT
= high side FET voltage drop due to RDS(ON);
HFET
V = output inductor voltage drop due to inductor wire
L
DC resistance;
V
V
= buck regulator input voltage;
IN
4. Output voltage ripple and noise.
= low side FET voltage drop due to RDS(ON).
LFET
Budgeting the tolerance is left to the designer who must
consider all of the above effects and provide an output
voltage that will meet the specified tolerance at the load. The
designer must also ensure that the regulator component
temperatures are kept within the manufacturer’s specified
ratings at full load and maximum ambient temperature.
Switching Frequency Select and Set
Selecting the switching frequency is a trade−off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values. Nevertheless, it is common to select lower
frequency operation because a higher frequency also
diminishes efficiency due to MOSFET gate charge losses.
Additionally, low value inductors at higher frequencies
result in higher ripple current, higher output voltage ripple,
and lower efficiency at light load currents. The value of the
oscillator resistor is designed to be linearly related to the
switching period. If the designer prefers not to use Figure 10
to select the appropriate resistance, the following equation
is a suitable alternative:
Selecting Feedback Divider Resistors
V
OUT
R1
V
FB
R2
21700 * f
SW
R
+
OSC
2.31 f
SW
Figure 9. Feedback Divider Resistors
where:
R
= oscillator resistor in kW;
= switching frequency in kHz.
OSC
The feedback pins (VFB1(2)) are connected to external
resistor dividers to set the output voltages. The error
amplifier is referenced to 0.8 V and the output voltage is
determined by selecting resistor divider values. Resistor R1
is selected based on a design trade−off between efficiency
and output voltage accuracy. The output voltage error
resulting from the bias current of the error amplifier can be
estimated, neglecting resistor tolerance, from the following
equation:
f
SW
800
700
600
500
400
300
200
100
0
−6
%Error + (100)(1 10 )(R1)ń0.8
−4
Rearranging, R1 + (%Error)(0.8)ń(1 10
)
After R1 has been chosen, R2 can be calculated from:
R2 + (R1)ń((V
ń0.8 V) * 1)
OUT
Example:
60
70
10
30
40
20
50
Assume the desired V
= 1.2 V, and the tolerable error
OUT
R
(kW)
OSC
due to input bias current is 0.2%.
Figure 10. Switching Frequency vs. ROSC
−4
R1 + (0.2)(0.8)ń(1 10 ) + 1.6 K
R2 + 1.6 Kń((1.2ń0.8) * 1) + 1.6 Kń0.5 + 3.2 K
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NCP5425
Output Inductor Selection
The number of output capacitors is determined by:
The inductor should be selected based on the criteria of
inductance, current capability, and DC resistance.
Increasing the inductor value will decrease output voltage
ripple, but degrade transient response. There are many
factors to consider in selecting inductors including cost,
efficiency, EMI and ease of manufacture. The inductor must
be able to handle the peak current at the switching frequency
without saturating, and the copper resistance in the winding
should be kept as low as possible to minimize resistive
power loss.
There are a variety of materials and types of magnetic
cores that could be used, such as ferrites, molypermalloy
cores (MPP), and amorphous and powdered iron cores.
Powdered iron cores are particularly suitable due to high
saturation flux density and low loss at high frequencies, a
distributed gap, and they produce very low EMI. The
minimum value of inductance to prevent inductor
saturation, or exceeding the rated FET current, can be
calculated as follows:
ESR
ESR
CAP
MAX
Number of capacitors +
where:
ESR
= maximum ESR per capacitor
CAP
(specified in manufacturer’s data sheet).
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
DI
2
DI
L
2
L
I
+ I
OUT
)
I
+ I )
OUT
L(PEAK)
L(VALLEY)
where:
I
I
I
= inductor peak current;
L(PEAK)
= inductor valley current;
L(VALLEY)
= load current;
DI = inductor ripple current.
OUT
L
Output Capacitor Selection
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are ESR
(Equivalent Series Resistance) and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required. To determine the number of
output capacitors the maximum voltage transient allowed
during load transitions has to be specified. The output
capacitors must hold the output voltage within these limits
since the inductor current can not change at the required slew
rate. The output capacitors must therefore have a very low
ESL and ESR.
(V
* V
)V
OUT OUT
I
SW(MAX)
IN(MIN)
V
L
MIN
+
f
SW
IN(MIN)
where:
L
= minimum inductance value;
V (MIN) = minimum design input voltage;
MIN
IN
V
OUT
= output voltage;
= switching frequency;
(MAX) = maximum design switch current.
f
I
SW
SW
The inductor ripple current can then be determined by:
V
(1 * D)
OUT
DI
+
L
L f
SW
where:
The voltage change during the load current transient is
given by:
D
IL
= inductor ripple current;
V
= output voltage;
OUT
t
ESL
Dt
TR
ǒ
Ǔ
DV
+ DI
OUT
) ESR )
L = inductor value;
D = duty cycle;
OUT
C
OUT
where:
f
= switching frequency.
SW
DI
DI
/DD = load current slew rate;
After inductor selection, the designer can verify if the
number of output capacitors will provide an acceptable
output voltage ripple (1.0% of output voltage is common).
The formula below is used;
OUT
= load transient;
OUT
Dt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
DV
OUT
ESR
DI
L
+
MAX
where:
t
TR
= output voltage transient response time;
C = output capacitance.
OUT
ESR
= maximum allowable ESR;
MAX
DV
= 1.0% VOUT = maximum allowable output
voltage ripple (budgeted by the designer);
The designer must independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike,
depending on the load current transition) results from the
total output capacitor ESR.
OUT
DI = inductor ripple current;
L
V
OUT
= output voltage.
Rearranging, we have:
DV
OUT
DI
ESR
+
MAX
L
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NCP5425
Maximum allowable ESR can then be determined
according to the formula:
double−pole network with a slope of −2.0, a roll−off rate of
−40 dB/decade, and a corner frequency given by:
1
DV
DI
ESR
OUT
f
C
+
ESR
+
MAX
Ǹ
2p LC
where:
L = input inductor;
C = input capacitor(s).
where:
DV
=change in output voltage due to ESR
(assigned by the designer)
ESR
Once the maximum allowable ESR is determined, the
number of output capacitors can be calculated:
POWER FET SELECTION
FET Basics
ESR
ESR
CAP
MAX
Number of capacitors +
The use of a MOSFET as a power switch is compelled by
two reasons: 1) high input impedance; and 2) fast switching
times. The electrical characteristics of a MOSFET are
considered to be nearly those of a perfect switch. Control
and drive circuitry power is therefore reduced. Because the
input impedance is so high, it is voltage driven. The input of
the MOSFET acts as if it were a small capacitor, which the
driving circuit must charge at turn on. The lower the drive
where:
ESR
= maximum ESR per capacitor
(specified in manufacturer’s data sheet);
= maximum allowable ESR.
CAP
ESR
MAX
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
impedance, the higher the rate of rise of V , and the faster
GS
the turn−on time. Power dissipation in the switching
MOSFET consists of: (1) conduction losses, (2) leakage
losses, (3) turn−on switching losses, (4) turn−off switching
losses, and (5) gate−transitions losses. The latter three losses
are all proportional to frequency. The most important aspect
of FET performance is the Static Drain−to−Source
DV
+ DI ESR
OUT MAX
ESR
Similarly, the maximum allowable ESL is calculated from
the following formula:
DV
Dt
ESL
ESL
MAX
+
DI
On−Resistance (R ), which affects regulator
DS(ON)
Input Inductor Selection
efficiency and FET thermal management requirements. The
On−Resistance determines the amount of current a FET can
handle without excessive power dissipation that may cause
overheating and potentially catastrophic failure. As the
drain current rises, especially above the continuous rating,
the On−Resistance also increases. Its positive temperature
coefficient is between +0.6%/_C and +0.85%/_C. The
higher the On−Resistance, the larger the conduction loss is.
Additionally, the FET gate charge should be low in order to
minimize switching losses and reduce power dissipation.
Both logic level and standard FETs can be used. Voltage
applied to the FET gates depends on the application circuit
used. Both upper and lower gate driver outputs are specified
to drive to within 1.5 V of ground when in the low state and
to within 2.0 V of their respective bias supplies when in the
high state. In practice, the FET gates will be driven
rail−to−raildue to overshoot caused by the capacitive load
they present to the controller IC.
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors during power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. An input inductor successfully blocks the ripple
current while placing the transient current requirements on
the input bypass capacitor bank, which has to initially
support the sudden load change. The minimum value for the
input inductor is:
DV
L
IN
+
(dlńdt)
MAX
Switching (Upper) FET Selection
where:
= input inductor value;
DV =voltage seen by the input inductor during a full load
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150_C. The maximum RMS
current through the switch can be determined by the
following formula:
L
IN
swing;
(dI/dt)
= maximum allowable input current slew rate.
MAX
The designer must select the LC filter pole frequency such
that a minimum of 40 dB attenuation is obtained at the
regulator switching frequency. The LC filter is a
ƪ
2
2
) ) I
L(VALLEY)
ƫ
D
I
) (I
I
L(PEAK)
L(PEAK)
L(VALLEY)
3
+ Ǹ
I
RMS(H)
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NCP5425
Synchronous (Lower) FET Selection
where:
The switch conduction losses for the lower FET are
calculated as follows:
I
I
I
= maximum switching MOSFET RMS current;
= inductor peak current;
RMS(H)
L(PEAK)
2
= inductor valley current;
P
+ I
RMS
R
L(VALLEY)
RMS(L)
DS(ON)
D = duty cycle.
Ǹ
2
+ ƪI
(1 * D)ƫ
R
OUT
DS(ON)
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated by:
where:
2
P
= lower MOSFET conduction losses;
= load current;
P
+ I
RMS(H)
R
RMS(L)
RMS(H)
DS(ON)
I
OUT
where:
P
D = Duty Cycle;
= lower FET drain−to−source on−resistance.
= switching MOSFET conduction losses;
= maximum switching MOSFET RMS current;
= FET drain−to−source on−resistance.
R
RMS(H)
DS(ON)
I
RMS(H)
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
R
DS(ON)
Upper MOSFET switching losses occur during MOSFET
switch−on and switch−off, and can be calculated by:
P
+ P
) P
SWH
SWH(ON)
I
SWH(OFF)
(t ) t )
FALL
V
IN
OUT
RISE
6T
+
P
+ V
I
SD LOAD
non−overlap time f
SW
SWL
where:
where:
P = lower FET switching losses;
SWL
P
P
V
= upper MOSFET switch−on losses;
= upper MOSFET switch−off losses;
= input voltage;
= load current;
SWH(ON)
SWH(OFF)
V
SD
= lower FET source−to−drain voltage;
I
= load current;
LOAD
IN
Non−overlap time = GATE(L)−to−GATE(H) or
I
OUT
GATE(H)−to−GATE(L) delay
(from NCP5425 data sheet
Electrical Characteristics section);
T
=MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
RISE
TFALL = MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
f
= switching frequency.
SW
T = 1/f = period.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
SW
The total power dissipation in the switching MOSFET can
then be calculated as:
P
+ P
) P
RMS(L) SWL
LFET(TOTAL)
P
+ P
RMS(H)
) P
SWH(ON)
) P
SWH(OFF)
HFET(TOTAL)
where:
where:
P
P
P
= Synchronous (lower) FET total losses;
= Switch Conduction Losses;
RMS(L)
= Switching losses.
SWL
LFET(TOTAL)
P
P
P
P
= total switching (upper) MOSFET losses;
= upper MOSFET switch conduction Losses;
= upper MOSFET switch−on losses;
HFET(TOTAL)
RMS(H)
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
SWH(ON)
SWH(OFF)
= upper MOSFET switch−off losses.
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
T + T ) [P
R
]
qJA
J
A
LFET(TOTAL)
where:
T = MOSFET junction temperature;
[
]
T + T ) P
R
qJA
J
A
HFET(TOTAL)
J
where:
T = FET junction temperature;
T = ambient temperature;
A
P
= total synchronous (lower) FET losses;
= lower FET junction−to−ambient thermal
resistance.
LFET(TOTAL)
J
R
qJA
T = ambient temperature;
A
P
R
= total switching (upper) FET losses;
= upper FET junction−to−ambient thermal
resistance.
HFET(TOTAL)
qJA
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NCP5425
Control IC Power Dissipation
Sense Resistor
The power dissipation of the IC varies with the MOSFETs
used, VCC, and the NCP5425 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation, and is given by:
A sense resistor can be added in series with the inductor.
When the voltage drop across the sense resistor exceeds the
internal voltage threshold of 70 mV, a limit condition is set.
The sense resistor value is calculated by:
P
+ I
) P
V
) I
V
0.070 V
CONTROL(IC)
CC1 CC1
BST BST
R
+
SENSE
I
LIMIT
) P
) P
GATE(H)1
GATE(H)2
GATE(L)1
GATE(L)2
In a high current supply, the sense resistor will be a very
low value, typically less than 10 mW. Such a resistor can be
either a discrete component or a PCB trace. The resistance
of a discrete component can be more precise than a PCB
trace, but the cost is also greater. Setting the current limit
using an external sense resistor is very precise because all
the values can be designed to specific tolerances. However,
the disadvantage of using a sense resistor is its additional
constant power loss and heat generation. Trace resistance
can vary as much as "10% due to copper plating variations.
) P
where:
P
I
V
P
P
= control IC power dissipation;
CONTROL(IC)
= IC quiescent supply current;
CC1
= IC supply voltage;
CC1
= upper MOSFET gate driver (IC) losses;
= lower MOSFET gate driver (IC) losses.
GATE(H)
GATE(L)
The upper (switching) MOSFET gate driver (IC) losses
are given by:
P
+ Q
f V
SW BST
GATE(H)
GATE(H)
Inductor ESR
Another means of sensing current is to use the intrinsic
resistance of the inductor. A model of an inductor reveals
that the windings have an effective series resistance (ESR).
The voltage drop across the inductor ESR can be measured
with a simple parallel circuit: an RC integrator. If the value
of RS1 and C are chosen such that:
where:
P
= upper MOSFET gate driver (IC) losses;
= total upper MOSFET gate charge at VCC;
= switching frequency.
GATE(H)
Q
GATE(H)
f
SW
The lower (synchronous) MOSFET gate driver (IC)
losses are:
L
+ R
C
S1
ESR
P
+ Q
f V
SW CC
GATE(L)
GATE(L)
then the voltage measured across the capacitor C will be:
where:
V
+ ESR I
LIM
C
P
= lower MOSFET gate driver (IC) losses;
= total lower MOSFET gate charge at VCC;
= switching frequency.
GATE(L)
Q
GATE(L)
Inductor Sensing Component Selection
Select the capacitor C first. A value of 0.1 mF is
recommended. The value of RS1 can be calculated by:
f
SW
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
L
R
+
S1
ESR C
Typical values for inductor ESR range in the low
milliohms; consult manufacturer’s data sheets for specific
values. Selection of components at these values will result
in a current limit of:
CURRENT SENSING AND CURRENT SHARING
Current Sharing Errors
The three main errors in current are from board layout
imbalances, inductor mismatch, and input offsets in the error
amplifiers. The first two sources of error can be controlled
through careful component selection and good layout
practice. With a 4.0 mW (parasitic winding resistance)
inductor, for example, one mV of input offset error will
represent 0.25 A of measurement error. One way to diminish
this effect is to use higher resistance inductors, but the
penalty is higher power losses in the inductors.
0.070 V
ESR
I
+
LIM
L
ESR
C
V
CC
Co
RS1
GATE(H)
GATE(L)
IS+
Current Limiting Options
The current supplied to the load can be sensed using the
IS+ and IS− pins. These pins sense a voltage, proportional
to the output current, and compare it to a fixed internal
voltage threshold. When the differential voltage exceeds
70 mV, the internal overcurrent protection system goes into
a cycle−by−cycle limiting mode. Two methods for sensing
the current are available.
IS−
Figure 11. Inductor ESR Current Sensing
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NCP5425
Master
Switch
Node
Slave
Switch
Node
Given an ESR value of 3.5 mW, the current limit becomes
20 A. If an increased current limit is required, a resistor
divider can be added (see Figure 8). Advantages of setting
the current limit by using the winding resistance of the
inductor (relative to a sense resistor) are higher efficiency
and lower heat generation. The tolerance of the inductor
ESR must be factored into the design of the current limit.
Finally, one or two more components are required for this
approach than with resistor sensing.
Slave
Error
Amp
Lx
Lx
R1
R2
C1
Rx
Rx
C1
R3
Selecting and Configuring Current Sharing for a 2
Phase Single Output Application
When the two controllers are connected as a single output
two phase Buck Converter, they are in a Master−Slave
configuration. The Slave controller on the right side of
Figure 6 tries to follow information provided by the Master
controller, on the left. This circuit uses inductor current
sensing, in which the parasitic resistances (LSR) of the
controllers’ output chokes are used as current sensing
elements. On the Slave side (Controller Two), both Error
Amplifier inputs are brought to external pins so the
reference is available. The RC network in parallel with the
output inductor on the Master side (Controller One)
generates the reference for the Slave. Current information
from the Slave is fed back to the error amplifier’s inverting
input. In this configuration, the Slave tries to adjust its
current to match the current information fed to its reference
input from the Master Controller. If 50−50 current sharing
is needed, then Figure 8a is used for both sides to generate
the reference and the inverting signals. The values for both
sides should be calculated with the following equation:
DC
Output
Figure 12. 40%/60% Current Sharing
Master
Switch
Node
Slave
Switch
Node
Slave
Error
Amp
Lx
Lx
R2
R1
Rx
Rx
C1
C1
R3
DC
Output
Lx
R1 +
, where,
C1 · Rx
Figure 13. 66.7%/33.3% Current Sharing
L = Inductor value, both controllers should use the same
x
inductor.
R = Internal resistance of L, from the inductor data sheet.
C1 = Select a value such that R1 is less than 15 KW.
x
Example 1
Assume we have elected to source 40% of the output
current from the master controller, and 60% from the Slave.
Figure 12 shows the configuration of the inductor sense
networks and Slave error amplifier. The ratio of
Slave−to−Masterload current is 60%/40%, or 1.5:1. R2 and
R3 must be chosen to satisfy two conditions:
With the RC time constant selected to equal the L /R time
x
x
constant, the voltage across the capacitor will be equal to the
voltage drop across the internal resistance of the inductor.
For proper sharing, the inductors on both Master and Slave
side should be the identical.
If a current share ratio other than 50−50 is desired,
inductor sense resistor network selection is a three step
process:
A parallel equivalent resistance equal to R1, and,
A ratio such that the drop across the parasitic resistance of
the Slave inductor is 1.5 times the drop across the parasitic
resistance of the Master inductor when the inputs to the
Slave error amplifier are equal (assumes the inductors are
identical). The optimum value of R1 is described by the
equation:
1. Decide how the total load current will be budgeted
between the two controllers.
2. Calculate the value of R1 for the controller with
the lesser current share.
3. Calculate the current sense resistor network
(2 resistors) for the controller with the greater
current share.
R1 + Lxń(C1 * Rx)
In the two examples that follow, the inductor sense
resistors are designated R1, R2, and R3, as depicted in
Figures 12 and 13.
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NCP5425
The values of R2 and R3 can be found by solving two
simultaneous equations:
The values of R2 and R3 can be found by solving two
simultaneous equations:
R2 + R3
R1 + (R2 * R3)ń(R2 ) R3)
Solving for R2 and R3 yields:
R2 + 2R1
R2 + R3ń2
R1 + (R2 * R3)ń(R2 ) R3)
Solving for R2 and R3 yields:
R2 + 1.5R1
R3 + 2R1
R3 + 3R1
Note that the Mode pin must be floating for a two−phase,
single output design. This disables the internal Error
Amplifier Reference clamp, and increases its common mode
range.
Example 2
Assume we have elected to source 66.7% output current
from the Master controller, and 33.3% from the Slave.
Figure 13 shows the configuration of the inductor sense
networks and Slave error amplifier for this case. The ratio of
Master−to−Slaveload current is equal to 66.7%/33.3%, or
2:1. Therefore R2 and R3 must be chosen to satisfy two
conditions:
No Load Zero Balance
To improve current matching, a low pass filter can be
inserted between the Master controller inductor sensing RC
network and the Slave controller Vref2 input pin (see
Figure 14). This will attenuate the amplitude of the
out−of−phaseripple current signal superimposed on the DC
current signal, providing a smoother Slave Error Amplifier
reference input.
A parallel equivalent resistance equal to R1, and,
A ratio such that the drop across the parasitic resistance of
the Master inductor is 2 times the drop across the parasitic
resistance of the Slave inductor when the inputs to the
Slave error amplifier are equal (assumes the inductors are
identical). The optimum value of R1 is described by the
equation:
R1 + Lxń(C1 * Rx)
Vin
Vout
Q1
Q2
Q3
L1
L2
C1
C2
Q4
R1
R2
R3
R4
C3
Vfb1
Vfb2
−
+
−
+
Vref2
Master
Error Amp
Slave
Error Amp
R
F
Low Pass
Filter
C
F
Internal
0.8 V Ref.
Figure 14. Addition of a Low Pass Filter to the Current Sense Reference Input
Configuring a Dual Output Application
With the value of R set to approximately two times the
F
To configure the NCP5425 for a dual output application:
value of R1, Cf can be calculated as follows:
• The Mode pin must be grounded
Cf + 1ń(2p · f · R ), where :
F
• An external voltage reference must be provided for
Controller 2, via the Vref2 pin
f = operating frequency of the controller
When a filter is added, the response delay introduced by
the RC time constant must be considered.
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NCP5425
Grounding the Mode pin enables an internal clamp to limit
The simplest way to provide a Controller 2 reference is by
using the Controller 1 feedback voltage. This will provide a
0.8 V reference for regulation, and also causes the
Controller 2 output to track the Controller 1 output during
transients. With a voltage reference established and the
Mode pin floating, Controller 2 can function as an
independent Buck regulator.
the Comp 2 voltage excursions during overcurrent faults.
Without this clamp, the output voltage (Vout1 and Vout2)
can overshoot the regulated output voltages when the fault
is removed. For a single output two−phase application the
Mode pin must be floating, which disables the clamp and
permits a larger current−sharing reference voltage range.
The Comp1 pin is always clamped, because it is regulated to
a fixed internal voltage (0.8 V).
Vin
Q1
Q3
Vout1
Vout2
L1
L2
Q4
C1
C2
Q2
R1
R2
R3
R4
Vfb1
Vfb2
−
+
−
+
Vref1
Vref2
Master
Error Amp
Slave
Error Amp
Internal
0.8 V Ref.
Figure 15. Dual Output Configuration
Adding External Slope Compensation
t = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
Today’s voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (VFB),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
internal slope compensation is insufficient, the performance
of the NCP5425−based regulator can be improved through
the addition of a fixed amount of external slope
compensation at the output of the PWM Error Amplifier (the
COMP pin) during the regulator off−time. Referring to
Figure 8, the amount of voltage ramp at the COMP pin is
dependent on the gate voltage of the lower (synchronous)
FET and the value of resistor divider formed by R1and R2.
COMP
NCP5425
C1
R2
R1
GATE(L)
To Synchronous
FET
Figure 16. RC Filter Provides the Proper Voltage
Ramp at the Beginning of each On−Time Cycle
R2
R1 ) R2
−1
ǒ
Ǔ
V
+ V
GATE(L)
(1−e
)
t
SLOPECOMP
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
where:
V
V
= amount of slope added;
= lower MOSFET gate voltage;
SLOPECOMP
GATE(L)
R1, R2 = voltage divider resistors;
t = t or t (switch off−time);
ON
OFF
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NCP5425
EMI MANAGEMENT
the optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections
and component vias, and the bottom layers for the
noise sensitive traces.
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise
during normal operation. When designing for compliance
with EMI/EMC regulations, additional components may be
necessary to reduce noise emissions. These components are
not required for regulator operation and experimental results
may allow them to be eliminated. The input filter inductor
may not be required because bulk filter and bypass
capacitors, as well as other loads located on the board will
tend to reduce regulator di/dt effects on the circuit board and
input power supply. Placement of the power components to
minimize routing distance will also help to reduce
emissions.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous
FETs close together.
7. The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with wide, thick copper to keep the parasitic
resistance low.
9. Place the switching MOSFET as close to the input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the COMP capacitor as close as possible to
the COMP pin.
12. Connect the filter components of pins ROSC, VFB,
VOUT, and COMP, to the GND pin with a single
trace, and connect this local GND trace to the
output capacitor GND.
13. Place the VCC bypass capacitors as close as possible
to the IC.
14. Place the ROSC resistor as close as possible to the
ROSC pin.
15. Assign the output with lower duty cycle to
channel 2, which has inherently better noise
immunity.
LAYOUT GUIDELINES
When laying out a buck regulator on a printed circuit
board, the following checklist should be used to ensure
proper operation of the NCP5425.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star
or single point grounding.
4. For high power buck regulators on double−sided
PCB’s a single ground plane (usually the bottom)
is recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, four−layer PCB’s are
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NCP5425
PACKAGE DIMENSIONS
TSSOP−20
DB SUFFIX
CASE 948E−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
20X K REF
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
S
0.15 (0.006) T U
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
N
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
F
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
DETAIL E
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
C
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0 8 0 8
0.252 BSC
0.100 (0.004)
−T− SEATING
M
_
_
_
_
PLANE
2
V is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5425/D
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