NCP6343BFCCT1G [ONSEMI]
3 A 处理器 - 带动态电压缩放的内存供应，I2C 编程瞬变负载帮助器;
| 型号： | NCP6343BFCCT1G |
| 厂家： | 
ONSEMI |
| 描述： | 3 A 处理器 - 带动态电压缩放的内存供应，I2C 编程瞬变负载帮助器 |
| 文件： | 总32页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Synchronous Buck
Converter - Step Down
3.0 A
NCP6343
The NCP6343 is a synchronous buck converter optimized to supply
the different sub systems of portable applications powered by one cell
Li−Ion or three cell Alkaline/NiCd/NiMH batteries. The device is able
to deliver up to 3.0 A, with programmable output voltage from 0.6 V
to 1.4 V. It can share the same output rail with another DCDC and
works as a transient load helper. Operation at a 3 MHz switching
frequency allows the use of small components. Synchronous
rectification and automatic PWM/PFM transitions improve overall
solution efficiency. The NCP6343 is in a space saving, low profile
1.99 x 1.34 mm CSP−15 package.
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MARKING
DIAGRAM
6343x
ALYWW
G
WLCSP15
CASE 567GB
x
= P: Prototype
= Blank: 1.225 V − 2.0 A
Features
= A: 1.225 V − 3.0 A
= B: 1.225 V − 3.0 A
= D: 1.18125 V − 3.0 A
= M: 0.925 V − 3.0 A
= S: 1.050 V − 3.0 A
= V: 1.225 V − 3.0 A
= X: 1.225 V − 3.0 A
= Assembly Location
= Wafer Lot
• Input Voltage Range from 2.3 V to 5.5 V: Battery and 5 V Rail
Powered Applications
• Programmable Output Voltage: 0.6 V to 1.4 V in 6.25 mV Steps
• Modular Output Stage Drive Strength for Increased Efficiency
Depending on the Output Current
A
L
Y
• 3 MHz Switching Frequency with On Chip Oscillator
• Uses 470 nH Inductor and 22 mF Capacitors for Optimized Footprint
= Year
WW = Work Week
and Solution Thickness
G
= Pb−Free Package
• PFM/PWM Operation for Optimum Increased Efficiency
Pb−Free indicator, G or microdot (G),
• Ultra Low 0.8 mA Off Mode Current
• Low 35 mA Quiescent Current
may or may not be present
2
• I C Control Interface with Interrupt and Dynamic Voltage Scaling
PINOUT DIAGRAM
NCP6343
Support
2
3
1
• Thermal Protections and Temperature Management
• Transient Load Helper: Share the Same Rail with Another DCDC
• Small 1.99 x 1.34 mm / 0.4 mm Pitch CSP Package
• These are Pb−Free Devices
A
B
C
D
E
PVIN
SW
PGND
Typical Applications
• Smartphones
• Webtablets
PVIN
PVIN
AVIN
SW
PGND
EN
PGND
PGND
SDA
NCP6343
References
Oscillator
A1
PVIN
B1
Supply Input
AVIN
D1
E1
Supply Input
C1
Core
10 uF
AGND
DCDC
3.0 A
SW
A2
B2
470 nH
22 uF
Thermal
Protection
A3
B3
C3
C2
PGND
FB
Enable Control EN
Input
D2
AGND
SCL
FB
Operating
Mode
Control
I@C
E3
Core
Processor
Memory
DCDC
3 MHz
Controller
SDA
SCL
D3
E2
Sense
22 uF
Processor I@C
(Top View)
15−Pin 0.40 mm pitch WLCSP
Control Interface
ORDERING INFORMATION
See detailed ordering and shipping information on page 30 of
this data sheet.
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
August, 2020 − Rev. 13
NCP6343/D
NCP6343
SUPPLY
INPUT
PVIN
POWER
INPUT
AVIN
AGND
Core
3.0 A
DC−DC
ANALOG
GROUND
Thermal
SW
MODULAR
DRIVER
Protection
SWITCH
NODE
Output Voltage
Monitoring
ENABLE
CONTROL
INPUT
3 MHz DC−DC
Converter
Operating
PGND
EN
Mode Control
Controller
POWER
GROUND
2
PROCESSOR I C
Logic Control
Interrupt
SCL
SDA
2
I C
FB
Sense
CONTROL
INTERFACE
FEEDBACK
Figure 2. Simplified Block Diagram
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2
NCP6343
NCP6343
2
3
1
A
B
C
D
E
PVIN
SW
SW
PGND
PVIN
PVIN
AVIN
PGND
PGND
SDA
PGND
EN
AGND
SCL
FB
Figure 3. Pin Out (Top View)
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
REFERENCE
D1
E1
AVIN
AGND
Analog
Input
Analog Supply. This pin is the device analog and digital supply. Could be connected directly to
the VIN plane or to a dedicated 1.0 mF ceramic capacitor. Must be equal to PVIN.
Analog
Ground
Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
CONTROL AND SERIAL INTERFACE
D2
E2
EN
Digital Input
Digital Input
Enable Control. Active high will enable the part. Do not leave this pin floating.
2
SCL
I C interface Clock line. There is an internal pull down resistor on this pin; could be left open if not
used
2
D3
SDA
Digital
I C interface Bi−directional Data line. There is an internal pull down resistor on this pin; could be
Input/Output left open if not used
DCDC CONVERTER
A1, B1,
C1
PVIN
Power Input
Switch Supply. These pins must be decoupled to ground by a 10 mF ceramic capacitor. It should
be placed as close as possible to these pins. All pins must be used with short heavy connections.
Must be equal to AVIN.
A2, B2
SW
Power
Output
Switch Node. These pins supply drive power to the inductor. Typical application uses 0.470 mH
inductor; refer to application section for more information.
All pins must be used with short heavy connections.
A3, B3,
C3, C2
PGND
FB
Power
Switch Ground. This pin is the power ground and carries the high switching current. High quality
ground must be provided to prevent noise spikes. To avoid high−density current flow in a limited
PCB track, a local ground plane that connects all PGND pins together is recommended. Analog
and power grounds should only be connected together in one location with a trace.
Ground
E3
Analog
Input
Feedback Voltage input. Must be connected to the output capacitor positive terminal with a
trace, not to a plane. This is the positive input to the error amplifier.
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3
NCP6343
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Analog and power pins: AVIN, PVIN, SW, FB
V
A
−0.3 to + 6.0
V
Digital pins: SCL, SDA, EN:
Input Voltage
V
DG
−0.3 to V +0.3 ≤ 6.0
V
A
Input Current
I
10
mA
DG
Human Body Model (HBM) ESD Rating (Note 1)
Machine Model (MM) ESD Rating (Note 1)
ESD HBM
ESD MM
2000
150
V
V
Charged Device Model (CDM) ESD Rating (Note 1)
ESD CDM
2000
V
Latch Up Current: (Note 2)
Digital Pins
I
LU
mA
10
100
All Other Pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 3)
T
−65 to + 150
−40 to +150
Level 1
°C
°C
STG
T
JMAX
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) 150 V per JEDEC standard: JESD22−A115.
Charged Device Model (CDM) 2.0 kV per JEDEC standard: JESD22−C101 Class IV.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
Table 3. OPERATING CONDITIONS (Note 4)
Symbol
AV PV
Parameter
Conditions
Min
2.3
−40
−40
−
Typ
Max
5.5
+85
+125
−
Unit
V
Power Supply
AVIN = PVIN
IN,
IN
T
A
Ambient Temperature Range
25
25
°C
T
J
Junction Temperature Range (Note 5)
Thermal Resistance Junction to Ambient (Note 6)
Power Dissipation Rating (Note 7)
°C
R
CSP−15 on Demo−board
65
°C/W
mW
mW
mH
q
JA
P
P
T
A
≤ 85°C
−
615
923
0.47
−
−
D
Power Dissipation Rating (Note 7)
T = 65°C
A
−
−
D
L
Inductor for DCDC converter (Note 4)
Output Capacitor for DCDC Converter (Note 4)
Input Capacitor for DCDC Converter (Note 4)
−
−
Co
28
4.7
55
−
mF
Cin
−
mF
4. Including de−ratings (Refer to the Application Information section of this document for further details)
5. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
6. The R
is dependent of the PCB heat dissipation.
q
JA
7. The maximum power dissipation (P ) is dependent by input voltage, maximum output current and external components selected.
D
125 * TA
RqJA
+
PD
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NCP6343
Table 4. ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Typical values are referenced to T = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Symbol
SUPPLY CURRENT: Pins AVIN – PVINx
Parameter
Conditions
Min
Typ
Max
Unit
I
Operating quiescent current PWM DCDC active in Forced PWM
no load
−
−
−
12
35
7
20
70
15
mA
mA
mA
Q PWM
I
Operating quiescent current PFM
DCDC active in Auto mode
no load − minimal switching
Q PFM
I
Product sleep mode current
EN high, DCDC off or
SLEEP
EN low and Sleep_Mode high
V
IN
= 2.5 V to 5.5 V
I
Product in off mode
EN and Sleep_Mode low
mA
OFF
V
= 2.5 V to 5.5 V (All other parts)
(NCP6343XFCCT1G)
−
−
0.8
7
5
15
IN
DCDC CONVERTER
PV
Input Voltage Range
2.3
2.0
2.5
3.0
−1
−
−
−
−
−
5.5
−
V
A
IN
OUTMAX
I
Maximum Output Current
Ipeak[1..0] = 00/01 (Note 10)
Ipeak[1..0] = 10 (Note 10)
Ipeak[1..0] = 11 (Note 10)
−
−
D
Output Voltage DC Error
Forced PWM mode
No load
1
%
VOUT
Forced PWM mode, V range,
−1
−1
−
−
1
2
IN
I
up to I
(Note 10)
OUT
OUTMAX
Auto mode, V range,
IN
(Note 10)
OUTMAX
I
up to I
OUT
F
Switching Frequency
2.7
3
3.3
64
MHz
SW
R
P−Channel MOSFET
On Resistance
From PVIN to SW (all Modules)
V = 5.0 V
IN
−
36
mW
ONHS
R
N−Channel MOSFET
On Resistance
From SW to PGND (all Modules)
V = 5.0 V
IN
−
19
40
mW
ONLS
I
Peak Inductor Current
Open loop – Ipeak[1..0] = 00/01
Open loop – Ipeak[1..0] = 10
Open loop – Ipeak[1..0] = 11
2.5
3.0
3.5
−
2.9
3.4
3.9
−0.2
0
3.3
3.8
4.3
−
A
PK
DC
Load Regulation
Line Regulation
I
from 0 A to I (Note 10)
OUTMAX
%/A
%
LOAD
OUT
DC
I
= 3 A
−
−
LINE
OUT
2.3 V ≤ V ≤ 5.5 V (Note 10)
IN
AC
Transient Load Response
Transient Line Response
tr = ts = 100 ns
−
50
30
−
mV
mV
LOAD
Load step 1.3 A (Note 10)
AC
tr = ts = 10 ms
100 mA Load (Note 10)
LINE
D
Maximum Duty Cycle
Turn on time
−
−
100
80
−
%
t
t
Time from EN transitions from Low to
High to 95% of Output Voltage
100
ms
START
(DELAY[2..0] = 000b and DVSup = 0)
Turn on time
Time from EN transitions from Low to
High to 95% of Output Voltage
(DELAY[2..0] = 000b and DVSup = 1)
−
−
425
25
550
35
ms
START
R
DCDC Active Output Discharge
Vout = 1.225 V
W
DISDCDC
2
8. Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels to
the V voltage to which the pull−up resistors R are connected.
DD
P
9. Refer to the Application Information section of this data sheet for more details.
10.Guaranteed by design and characterized.
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NCP6343
Table 4. ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Typical values are referenced to T = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Symbol
EN
Parameter
Conditions
Min
Typ
Max
Unit
V
High input voltage
1.05
−
−
−
−
−
V
V
IH
V
Low input voltage
0.4
4.5
IL
T
FTR
Digital input X Filter
EN rising and falling
DBN_Time = 01 (Note 10)
0.5
ms
I
Digital input X Pull−Down
(input bias current)
−
0.05
1.00
mA
PD
2
I C
V 2
I CINT
High level at SCL/SCA line
SCL, SDA low input voltage
SCL, SDA high input voltage
1.7
−
−
−
−
5.0
0.5
−
V
V
V
V 2
I CIL
SCL, SDA pin (Notes 8, 10)
SCL, SDA pin (Notes 8, 10)
V 2
I CIH
0.8 *
V 2
I CINT
V 2
I COL
SDA low output voltage
I
= 3 mA (Note 10)
−
−
−
−
0.4
3.4
V
SINK
2
F
SCL
I C clock frequency
(Note 10)
MHz
TOTAL DEVICE
V
Under Voltage Lockout
V
V
falling
rising
−
−
−
2.3
V
UVLO
IN
V
Under Voltage Lockout
Hysteresis
60
200
mV
UVLOH
IN
T
Thermal Shut Down Protection
Warning Rising Edge
−
−
−
−
−
−
150
135
105
30
−
−
−
−
−
−
°C
°C
°C
°C
°C
°C
SD
T
WARNING
2
T
Pre − Warning Threshold
I C default value
PWTH
T
Thermal Shut Down Hysteresis
Thermal warning Hysteresis
Thermal pre−warning Hysteresis
SDH
WARNINGH
T
15
T
6
PWTH H
2
8. Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels to
the V voltage to which the pull−up resistors R are connected.
DD
P
9. Refer to the Application Information section of this data sheet for more details.
10.Guaranteed by design and characterized.
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NCP6343
TYPICAL OPERATING CHARACTERISTICS AV = PV = 3.6 V, T = +25°C
IN
IN
J
DCDC = 1.225 V, Ipeak = 3.9 A (Unless otherwise noted). L = 0.47 mH PIFE20161B – Cout = 2x 22 mF 0603, Cin = 4.7 mF 0603.
95
95
90
85
80
+25°C
+85°C
V
= 5.0 V
= 2.9 V
IN
90
85
80
−40°C
V
IN
= 3.6 V
V
IN
75
70
75
70
0
0
0
1000
2000
3000
1
1
1
10
100
(mA)
1000
10,000
I
(mA)
I
OUT
OUT
Figure 4. Efficiency vs. ILOAD and VIN
VOUT = 1.39375 V, SPM6530 Inductor
Figure 5. Efficiency vs. ILOAD and Temperature
V
OUT = 1.39375 V, SPM6530 Inductor
95
90
95
90
+25°C
V
= 5.0 V
IN
−40°C
+85°C
85
80
85
80
V
IN
= 3.6 V
V
IN
= 2.9 V
75
70
75
70
1000
2000
3000
10
100
(mA)
1000
10,000
I
(mA)
I
OUT
OUT
Figure 6. Efficiency vs. ILOAD and VIN
VOUT = 1.225 V, SPM6530 Inductor
Figure 7. Efficiency vs. ILOAD and Temperature
V
OUT = 1.225 V, SPM6530 Inductor
90
85
80
75
70
90
85
80
75
70
+25°C
V
IN
= 5.0 V
−40°C
+85°C
V
IN
= 3.6 V
V
IN
= 2.9 V
65
60
65
60
1000
2000
3000
10
100
(mA)
1000
10,000
I
(mA)
I
OUT
OUT
Figure 8. Efficiency vs. ILOAD and VIN
VOUT = 0.60 V, SPM6530 Inductor
Figure 9. Efficiency vs. ILOAD and Temperature
OUT = 0.60 V, SPM6530 Inductor
V
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NCP6343
TYPICAL OPERATING CHARACTERISTICS AV = PV = 3.6 V, T = +25°C
IN
IN
J
DCDC = 1.225 V, Ipeak = 3.9 A (Unless otherwise noted). L = 0.47 mH PIFE20161B – Cout = 2x 22 mF 0603, Cin = 4.7 mF 0603.
95
95
90
85
80
+25°C
+85°C
90
85
80
−40°C
V
= 5.0 V
= 2.9 V
IN
V
IN
= 3.6 V
V
IN
75
70
75
70
0
1000
2000
3000
1
10
100
(mA)
1000
10,000
I
(mA)
I
OUT
OUT
Figure 10. Efficiency vs. ILOAD and VIN
VOUT = 1.225 V, PIFE20161B Inductor
Figure 11. Efficiency vs. ILOAD and Temperature
OUT = 1.225 V, PIFE20161B Inductor
V
1.237
1.231
1.225
1.0
0.5
0
V
= 3.6 V
IN
V
IN
= 2.9 V
+25°C
+85°C
V
= 5.0 V
IN
−40°C
1.219
1.213
−0.5
−1.0
0
1000
2000
3000
0
1000
2000
3000
I
(mA)
I
(mA)
LOAD
LOAD
Figure 12. VOUT Accuracy vs. ILOAD and VIN
VOUT = 1.225 V
Figure 13. VOUT Accuracy vs. ILOAD and
Temperature, VOUT = 1.225 V, VIN = 3.6 V
0.610
0.605
0.600
1.410
1.405
V
V
= 3.6 V
= 2.9 V
IN
V
V
= 3.6 V
= 2.9 V
IN
1.400
1.395
1.390
IN
IN
V
IN
= 5.0 V
V
IN
= 5.0 V
0.595
0.590
1.385
1.380
0
1000
2000
3000
0
1000
2000
3000
I
(mA)
I
(mA)
LOAD
LOAD
Figure 14. VOUT Accuracy vs. ILOAD and VIN
VOUT = 0.60 V
Figure 15. VOUT Accuracy vs. ILOAD and VIN
VOUT = 1.39375 V
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NCP6343
TYPICAL OPERATING CHARACTERISTICS AV = PV = 3.6 V, T = +25°C
IN
IN
J
DCDC = 1.225 V, Ipeak = 3.9 A (Unless otherwise noted). L = 0.47 mH PIFE20161B – Cout = 2x 22 mF 0603, Cin = 4.7 mF 0603.
75
35
30
25
20
+85°C
65
55
45
+85°C
+25°C
+25°C
−40°C
−40°C
35
25
15
10
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
5.5
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
5.5
5.5
V
V
IN
IN
Figure 16. HSS RON vs. VIN and Temperature
Figure 17. LSS RON vs. VIN and Temperature
5
4
3
15
10
+85°C
+25°C
−40°C
2
+85°C
5
0
+25°C
−40°C
1
0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
V
V
IN
IN
Figure 18. IOFF vs. VIN and Temperature
Figure 19. ISLEEP vs. VIN and Temperature
100
80
20
60
+25°C
+85°C
15
10
40
+85°C
−40°C
2.5
−40°C
20
0
+25°C
2.5
3.0
3.5
4.0
(V)
4.5
5.0
3.0
3.5
4.0
(V)
4.5
5.0
V
V
IN
IN
Figure 20. IQ PFM vs. VIN and Temperature
Figure 21. IQ PWM vs. VIN and Temperature
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NCP6343
TYPICAL OPERATING CHARACTERISTICS AV = PV = 3.6 V, T = +25°C
IN
IN
J
DCDC = 1.225 V, Ipeak = 3.9 A (Unless otherwise noted). L = 0.47 mH PIFE20161B – Cout = 2x 22 mF 0603, Cin = 4.7 mF 0603.
600
600
500
500
400
Enter PWM
Exit PWM
Enter PWM
Exit PWM
400
300
200
300
200
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
Figure 22. Switchover Point VOUT = 1.225 V
Figure 23. Switchover Point VOUT = 1.39375 V
17 mV
6.2 mV
3.01 MHz
Figure 24. PWM Ripple
Figure 25. PFM Ripple
85.8 ms
Normal
Power−Up
Figure 26. Normal Power Up, VOUT = 1.225 V
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NCP6343
TYPICAL OPERATING CHARACTERISTICS AV = PV = 3.6 V, T = +25°C
IN
IN
J
DCDC = 1.225 V, Ipeak = 3.9 A (Unless otherwise noted). L = 0.47 mH PIFE20161B – Cout = 2x 22 mF 0603, Cin = 4.7 mF 0603.
51 mV
50 mV
43 mV
44 mV
0.1 A / 1.4 A / 0.1 A
0.1 A / 1.4 A / 0.1 A
Figure 27. Transient Load 0.1 − 1.4 A
Transient Line 4.2 − 3.6 V Auto Mode
Figure 28. Transient Load 0.1 − 1.4 A
Transient Line 3.6 − 4.2 V Auto Mode
52 mV
42 mV
51 mV
48 mV
1 A / 1.3 A / 1 A
1 A / 1.3 A / 1 A
Figure 29. Transient Load 1.0 − 2.3 A
Transient Line 4.2 − 3.6 V Auto Mode
Figure 30. Transient Load 1.0 − 2.3 A
Transient Line 3.6 − 4.2 V Auto Mode
48 mV
41 mV
38 mV
41 mV
1 A / 1.3 A / 1 A
1 A / 1.3 A / 1 A
Figure 31. Fast Transient Load
Figure 32. Fast Transient Load
0.1 − 1.4 A Auto Mode
1.0 − 2.3 A Auto Mode
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11
NCP6343
DETAILED OPERATING DESCRIPTION
Forced PWM
Detailed Descriptions
The NCP6343 is voltage mode stand alone synchronous
DC to DC converter optimized to supply different sub
systems of portable applications powered by one cell Li−Ion
or three cells Alkaline/NiCd/NiMh. The IC can deliver up to
The NCP6343 can be programmed to only use PWM and
disable the transition to PFM if so desired. (PWM bits of
COMMAND register).
Output Stage
2
3 A at an I C selectable voltage ranging from 0.60 V to
NCP6343 is a high output current capable integrated DC
to DC converter. To supply such a high current, the internal
MOSFETs need to be large. The output stage is composed
of 8 modules that can be individually Enabled / Disabled by
setting the MODULE register.
1.40 V. It can share the same output rail with another DCDC
and works as a transient load helper without sinking current
on shared rail. A 3 MHz switching frequency allows the use
of smaller output filter components. Synchronous
rectification and automatic PWM/PFM transitions improve
overall solution efficiency. Forced PWM is also
configurable. Operating modes, configuration, and output
power can be easily selected either by programming a set of
Inductor Peak Current Limitation
NCP6343 is a 2.0 A to 3.0 A output current capable.
During normal operation, peak current limitation will
monitor and limit the current through the inductor. This
current limitation is particularly useful when size and/or
height constrain inductor power. The user can select peak
current to keep inductor within its specifications. The peak
current can be set by writing IPEAK[1..0] bits in LIMCONF
register.
2
registers using an I C compatible interface capable of
2
operation up to 3.4 MHz. Default I C settings are factory
programmable.
DC to DC Buck Operation
The converter is a synchronous rectifier type with both
high side and low side integrated switches. Neither external
transistor nor diodes are required for NCP6343 operation.
Feedback and compensation network are also fully
integrated. The converter can operate in two different
modes: PWM and PFM. The transition between PWM/PFM
modes can occur automatically or the switcher can be placed
Table 5. Ipeak VALUES
IPEAK[1..0]
Default Inductor Peak Current (A)
2.9 A for 2.0 A output current
2.9 A for 2.0 A output current
3.4 A for 2.5 A output current
3.9 A for 3.0 A output current
00
01
10
11
2
in forced PWM mode by I C programming (PWM bits of
COMMAND register).
PWM (Pulse Width Modulation) Operating Mode
In medium and high load conditions, NCP6343 operates
in PWM mode from a fixed clock and adapts its duty cycle
to regulate the desired output voltage. In this mode, the
inductor current is in CCM (Continuous Current Mode) and
the voltage is regulated by PWM. The internal N−MOSFET
switch operates as synchronous rectifier and is driven
complementary to the P−MOSFET switch. In CCM, the
lower switch (N−MOSFET) in a synchronous converter
provides a lower voltage drop than the diode in an
asynchronous converter, which provides less loss and higher
efficiency.
Output Voltage
Output voltage is set internally by integrated resistor
bridge and error amplifier that drives the PWM/PFM
controller. No extra component is needed to set output
voltage. However, writing in the Vout[6..0] bits of the PROG
register will change settings. Output voltage level can be
programmed in the 0.6 V to 1.4 V range by 6.25 mV steps.
Under Voltage Lock Out (UVLO)
NCP6343 core does not operate for voltages below the
Under Voltage lock Out (UVLO) level. Below UVLO
threshold, all internal circuitry (both analog and digital) is
held in reset.
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low loads
the NCP6343 operates in PFM mode as the inductor drops
into DCM (Discontinuous Current Mode). The upper FET
on time is kept constant and the switching frequency is
variable. Output voltage is regulated by varying the
switching frequency which becomes proportional to loading
current. As it does in PWM mode, the internal N−MOSFET
operates as synchronous rectifier after each P−MOSFET
on−pulse. When load increases and current in inductor
becomes continuous again, the controller automatically
turns back to PWM mode.
NCP6343 operation is guaranteed down to VUVLO when
battery voltage is dropping off. To avoid erratic on / off
behavior, a maximum 200 mV hysteresis is implemented.
Restart is guaranteed at 2.5 V when VBAT voltage is
recovering or rising.
Thermal Management
Thermal shutdown (TSD)
The thermal capability of IC can be exceeded due to step
down converter output stage power level. A thermal
protection circuitry is therefore implemented to prevent the
IC from damage. This protection circuitry is only activated
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12
NCP6343
Active Output Discharge
when the core is in active mode (output voltage is turned on).
During thermal shut down, output voltage is turned off.
When NCP6343 returns from thermal shutdown, it can
re−start in 2 different configurations depending on REARM
bit in the LIMCONF register (see register description
section):
To make sure that no residual voltage remains in the power
supply rail, an active discharge path can ground the
NCP6343 output voltage.
For maximum flexibility, this feature can be easily
disabled or enabled with DISCHG bit in PGOOD register
However the discharged path is activated during the first
100 ms after battery insertion.
• If REARM = 0 then NCP6343 does not re−start after
TSD. To restart, an EN pin toggle is required.
• If REARM = 1, NCP6343 re−starts with register values
Enabling
set prior to thermal shutdown.
The EN pin controls NCP6343 start up: EN pin Low to
High transition starts the power up sequencer. If EN is made
low, the DC to DC converter is turned off and device enters:
A Thermal shut down interrupt is raised upon this event.
Thermal shut down threshold is set at 150°C (typical)
when the die temperature increases and, in order to avoid
erratic on / off behavior, a 30°C hysteresis is implemented.
After a typical 150°C thermal shut down, NCP6343 will
resume to normal operation when the die temperature cools
to 120°C.
2
• In Sleep Mode if Sleep_Mode I C bit is high,
2
• In Off Mode if Sleep_Mode I C bit is low.
When EN pin is set to a high level, the DC to DC converter
can be enabled / disabled depending of the state of the EN
2
bit of the PROG register: If EN I C bit is high, DCDC is
activated, If EN I C is low the DC to DC converter is turned
2
Thermal Warnings
off and device enters:
In addition to the TSD, the die temperature monitoring
will flag potential die over temperature. A thermal warning
and thermal pre−warning are implemented which can
inform the processor through two different interrupts
2
• In Sleep Mode if Sleep_Mode I C bit is high,
2
• In Off Mode if Sleep_Mode I C bit is low.
The EN pin should not be left floating.
2
(accessible via I C) that NCP6343 is close to its thermal
Power Up Sequence (PUS)
shutdown so that preventive measures to cool down die
temperature can be taken by software.
In order to power up the circuit, the input voltage AVIN
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up which is the “Wake Up
Time” (including “Bias Time”).
This delay is internal and cannot be bypassed. EN pin
transition within this delay corresponds to the “Initial power
up sequence” (IPUS):
The Warning threshold is set by hardware to 135°C typical
when the die temperature increases. The Pre−Warning
threshold is set by default to 105°C, but can be changed by
user by setting the TPWTH[1..0] bits in the LIMCONF
register.
AVIN
UVLO
POR
EN
DELAY[2..0]
VOUT
~ 50 us
32 us
Wake up
Time
Init
Time
DVS ramp
Time
Figure 33. Initial Power Up Sequence
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13
NCP6343
Normal, Quick and Fast Power Up Sequence
In addition a user programmable delay will also take place
between end of Core circuitry turn on (Wake Up Time and
Bias Time) and Init time: The DELAY[2..0] bits of TIME
register will set this user programmable delay with a 2 ms
resolution. With default delay of 0 ms, the NCP6343 IPUS
takes roughly 85 ms, means DCDC output voltage will be
ready within 110 ms.
The previous description applies only when the EN
transitions during the internal core circuitry power up (Wake
up and calibration time). Otherwise 3 different cases are
possible:
Enabling the part by setting EN pin from Off Mode will
result in “Normal power up sequence” (NPUS, with
DELAY;[2..0]).
Enabling the part by setting EN pin from Sleep Mode will
result in “Quick power up sequence” (QPUS, with
DELAY;[2..0]).
2
NOTE: During the Wake Up time, the I C interface is not
2
active. Any I C request to the IC during this time period will
result in a NACK reply.
Enabling the part by setting EN bits of the PROG register
(whereas EN is already high results in “Fast power up
sequence” (FPUS, without DELAY[2..0]).
AVIN
UVLO
POR
EN
O
F
F
DELAY[2..0]
VOUT
M
O
D
E
20 us
32 us
TFTR Bias
Time
Init
Time
DVS ramp
Time
Figure 34. Normal Power Up Sequence (EN pin)
AVIN
UVLO
POR
EN
S
L
E
E
P
M
O
D
E
DELAY[2..0]
VOUT
32 us
TFTR
Init
Time
DVS ramp
Time
Figure 35. Quick Power Up Sequence (EN pin)
AVIN
UVLO
POR
EN I@C
S
L
E
E
P
M
O
D
E
VOUT
32 us
Init
Time
DVS ramp
Time
Figure 36. Fast Power Up Sequence (EN bit)
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14
NCP6343
In addition the delay set in DELAY[2..0] bits in TIME
register will apply only for the EN pins turn ON sequence
(NPUS and QPUS).
• In Auto mode when output voltage has not to be
discharged. Note that approximately 30 ms is needed to
transition from PFM mode to PWM mode.
Note that the sleep mode needs about 150 ms to be
established.
V2
Output
Voltage
Internal
Reference
nV
DC to DC converter Shut Down
When shutting down the device, no shut down sequence
is required. Output voltage is disabled and, depending on the
DISCHG bit state of PGOOD register, output may be
discharged.
nt
V1
Figure 38. DVS in Auto Mode Diagram
Shutdown is initiated by either grounding the EN pin
2
(Hardware Shutdown) or by clearing the EN I C bit
Power Good
(Software shutdown) in PROG register.
To indicate the output voltage level is established, a power
good signal is available.
In hardware shutdown (EN = 0), the internal core is still
2
active and I C accessible.
The power good signal is high when the channel is off and
goes low when enabling the channel. Once the output
voltage reaches 95% of the expected output level, the power
good logic signal becomes high (ACK_PG, SEN_PG bits).
During operation when the output drops below 90% of the
programmed level the power good logic signal goes low,
indicating a power failure. When the voltage rises again to
above 95% the power good signal goes high again.
During a positive DVS sequence, when target voltage is
higher than initial voltage, the Power Good logic signal will
be set low during output voltage ramping and transition to
high once the output voltage reaches 95% of the target
voltage. When the target voltage is lower than the initial
voltage, Power Good logic signals will remain at high level
during transition.
NCP6343 shuts internal core down when AVIN falls
below UVLO.
Dynamic Voltage Scaling (DVS)
This converter supports dynamic voltage scaling (DVS)
allowing the output voltage to be reprogrammed via I C
2
commands and provides the different voltages required by
the processor. The change between set points is managed in
a smooth fashion without disturbing the operation of the
processor.
When programming a higher voltage, output raises with
controlled dV/dt defined by DVSup bit in TIME register
(default 6.25 mV/0.166 ms). When programming a lower
voltage, output will decrease in equidistant steps defined by
DVSdown[1..0] bits in TIME register (default
6.25 mV/2.666 ms).
DVS sequence is automatically initiated by changing
output voltage settings.
The DVS transition mode can be changed with the
DVSMODE bit in COMMAND register:
• In forced PWM mode when accurate output voltage
control is needed.
Power Good signal during normal operation can be
disabled by clearing the PGDCDC bit in PGOOD register.
Power Good operation during DVS can be controlled by
setting / clearing the bit PGDVS in PGOOD register
DCDC_EN
95%
90%
32 us
min
DCDC
3.5−
14 us
3.5−
14 us
V2
Internal
Output
3.5 us
Reference
Voltage
nV
PG
nt
Figure 39. Power Good Signal
V1
Figure 37. DVS in Forced PWM Mode Diagram
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15
NCP6343
Interrupt
Individual bits generating interrupts will be set to 1 in the
INT_ACK register (I C read only registers), indicating the
2
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual edge monitoring).
interrupt source. INT_ACK register is automatically reset
2
by an I C read. The INT_SEN register (read only register)
contains real time indicators of interrupt sources.
When the host reads the INT_ACK registers the interrupt
register INT_ACK is cleared.
Table 6. INTERRUPT SOURCES
Interrupt Name
TSD
Description
Thermal Shut Down
Figure 40 is UVLO event example:
INT_SEN/INT_MSK/INT_ACK and an I C read access
2
TWARN
TPREW
UVLO
Thermal Warning
behavior.
Thermal Pre Warning
Under Voltage Lock Out
DCDC current Over / below limit
Power Good
IDCDC
PG
UVLO
SEN_UVLO
ACK_UVLO
read
read
read
read
I@C access on INT_ACK
Figure 40. Interrupt Operation Example
Configurations
Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request.
The default configuration pre−defined is depicted below:
Table 7. DEFAULT CONFIGURATIONS
Configuration
NCP6343
NCP6343A
NCP6343B
NCP6343D
2
Default I C address
0x1C
12h
xxh
0x14
12h
xxh
0x1C
12h
xxh
0x14
12h
xxh
PID product id.
RID revision id.
FID feature id.
00h
02h
01h
03h
VOUT
1.225 V
Auto mode
6.25mV/0.166ms
2.9 A
1.225 V
Forced PWM mode
6.25mV/0.166ms
3.9 A
1.225 V
Auto mode
1.18125 V
Forced PWM mode
6.25mV/0.166ms
3.9 A
MODE
DVS Up Timing
Default IPEAK
Marking
6.25mV/0.166ms
3.9 A
6343
6343A
6343B
6343D
OPN
NCP6343FCT1G
NCP6343AFCCT1G
NCP6343BFCCT1G
NCP6343DFCCT1G
Table 8. DEFAULT CONFIGURATIONS
Configuration
NCP6343AV
NCP6343S
NCP6343M
NCP6343X
2
Default I C address
0x14
12h
xxh
0x10
12h
xxh
0x18
12h
xxh
0x1C
12h
xxh
PID product id.
RID revision id.
FID feature id.
02h
00h
00h
01h
VOUT
1.225 V
Auto mode
1.050 V
Auto mode
0.925 V
Auto mode
1.225 V
Auto mode
MODE
DVS Up Timing
Default IPEAK
Marking
6.25mV/2.666ms
3.9 A
6.25mV/2.666ms
3.9 A
6.25mV/2.666ms
3.9 A
6.25mV/0.166ms
3.9 A
6343V
6343S
6343M
6343X
OPN
NCP6343AVFCCT1G
NCP6343SFCCT1G
NCP6343MFCCT1G
NCP6343XFCCT1G
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16
NCP6343
2
I C Compatible Interface
2
NCP6343 can support a subset of I C protocol Detailed below.
I2C Communication Description
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
READ OUT
FROM PART
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA n
à
1
READ
/ACK
ACK
WRITE INSIDE
PART
START
ACK
ACK
STOP
IC ADDRESS
0
DATA 1
DATA n
If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr.
If PART Acknowledges, the ACK can be followed by another data or Stop or Sr
à
0
WRITE
Figure 41. General Protocol Description
The first byte transmitted is the Chip address (with the
LSB bit set to 1 for a read operation, or set to 0 for a Write
operation). The following data will be:
• In case of a Write operation, the register address
(@REG) pointing to the register we want to write in
followed by the data we will write in that location. The
writing process is auto−incremental, so the first data
will be written in @REG, the contents of @REG are
incremented and the next data byte is placed in the
location pointed to by @REG + 1 ..., etc.
• In case of read operation, the NCP6343 will output the
data from the last register that has been accessed by the
last write operation. Like the writing process, the
reading process is auto−incremental.
Read Out from Part
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
then start or a Repeated Start will initiate the read transaction
from the register address the initial write transaction has
pointed to:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
START
ACK
ACK
STOP
IC ADDRESS
0
REGISTER ADDRESS
à
0
WRITE
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA n
REGISTER ADDRESS
VALUE
REGISTER ADDRESS + (n − 1)
VALUE
n REGISTERS READ
à
1
READ
Figure 42. Read Out from Part
The first WRITE sequence will set the internal pointer to the register we want access to. Then the read transaction will start
at the address the write transaction has initiated.
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17
NCP6343
Transaction with Real Write then Read
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0
WRITE VALUE IN
REGISTER REG0 + (n − 1)
START
ACK
ACK
ACK
ACK
STOP
IC ADDRESS
0
REGISTER REG0 ADDRESS
REG VALUE
REG + (n − 1) VALUE
n REGISTERS WRITE
à
0
WRITE
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA k
REGISTER ADDRESS + (n − 1) +
(k − 1) VALUE
REGISTER REG + (n − 1)
VALUE
k REGISTERS READ
à
1
READ
Figure 43. Write Followed by Read Transaction
Write In Part
Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register
we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2, ...., Reg +n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
WRITE VALUE IN
REGISTER REG0
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n − 1)
START
ACK
ACK
ACK
ACK
STOP
IC ADDRESS
0
REGISTER REG0 ADDRESS
REG VALUE
REG + (n − 1) VALUE
n REGISTERS WRITE
à
0
WRITE
Figure 44. Write In n Registers
I2C Address
2
NCP6343 has four available I C address selectable by factory settings (ADD0 to ADD3). Different address settings can be
generated upon request to ON Semiconductor. The default address is set to 38h / 39h since the NCP6343 supports 7−bit address
only and ignores A0.
Table 9. I2C ADDRESS
2
I C Address
Hex
A7
A6
A5
A4
0
A3
A2
A1
A0
R/W
−
W 0x20
R 0x21
0
0
1
0
0
0
ADD0
(NCP6343S)
Add
0x10
0
W 0x28
R 0x29
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
R/W
−
ADD1
(NCP6343AV, NCP6343D)
Add
0x14
1
W 0x30
R 0x31
R/W
−
ADD2
(NCP6343M)
Add
0x18
1
W 0x38
R 0x39
R/W
−
ADD3 (default)
(NCP6343, NCP6343B, NCP6343X)
Add
0x1C
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18
NCP6343
Register Map
Table 10 describes I C registers.
2
Registers can be:
R
RC
Read only register
Read then Clear
RW
Read and Write register
Reserved
Spare
Address is reserved and register is not physically designed
Address is reserved and register is physically designed
Table 10. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
00h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
E4h
00h
19h
00h
80h
23h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 11. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343A)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
02h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
E4h
00h
19h
80h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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19
NCP6343
Table 12. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343B)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
01h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
E4h
00h
19h
00h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 13. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343D)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
03h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
DDh
00h
19h
80h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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20
NCP6343
Table 14. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343AV)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
02h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
E4h
00h
1Dh
00h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 15. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343S)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
00h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
C8h
00h
1Dh
00h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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21
NCP6343
Table 16. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343M)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
00h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
B4h
00h
1Dh
00h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 17. I2C REGISTERS MAP DEFAULT CONFIGURATION (NCP6343X)
Add.
00h
Register Name
Type
RC
R
Def.
00h
00h
−
Function
INT_ACK
INT_SEN
−
Interrupt register
01h
Sense register (real time status)
Reserved for future use
02h
−
03h
PID
R
12h
Metal
01h
−
Product Identification
04h
RID
R
Revision Identification
05h
FID
R
Feature Identification (trim)
06h to 10h
11h
−
−
Reserved for future use
PROG
PGOOD
TIME
RW
RW
RW
RW
RW
RW
−
E4h
00h
19h
00h
80h
E3h
−
Output voltage settings and (trim)
Power good and active discharge settings (partial trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (partial trim)
Active module count settings
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
15h
16h
Reset and limit configuration register (partial trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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22
NCP6343
Registers Description
Table 18. INTERRUPT ACKNOWLEDGE REGISTER
Name: INTACK
Address: 00h
Default: 00000000b (00h)
Type: RC
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_TWARN
ACK_TPREW
Spare = 0
Spare= 0
ACK_UVLO
ACK_IDCDC
ACK_PG
Bit
Bit Description
ACK_PG
ACK_IDCDC
ACK_UVLO
ACK_TPREW
ACK_TWARN
ACK_TSD
Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event detected
DCDC Over Current Sense Acknowledgement
0: Cleared
1: DCDC Over Current Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
Table 19. INTERRUPT SENSE REGISTER
Name: INTSEN
Type: R
Address: 01h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_TWARN
SEN_TPREW
Spare = 0
Spare = 0
SEN_UVLO
SEN_IDCDC
SEN_PG
Bit
Bit Description
SEN_PG
SEN _IDCDC
SEN _UVLO
SEN _TPREW
SEN _TWARN
SEN _TSD
Power Good Sense
0: DCDC Output Voltage below target
1: DCDC Output Voltage within nominal range
DCDC over current sense
0: DCDC output current is below limit
1: DCDC output current is over limit
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
Thermal Pre Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
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23
NCP6343
Table 20. PRODUCT ID REGISTER
Name: PID
Type: R
Address: 03h
Default: 00010010b (12h)
Reset on N/A
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PID_7
PID_6
PID_5
PID_4
PID_3
PID_2
PID_1
PID_0
Table 21. REVISION ID REGISTER
Name: RID
Type: R
Address: 04h
Default: Metal
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Spare = 0
Spare = 0
Spare = 0
RID_3
RID_2
RID_1
RID_0
Bit
RID[3..0]
Bit Description
Revision Identification
0000: First silicon
0100: Optimized silicon
1000: Production
Table 22. FEATURE ID REGISTER
Name: FID
Type: R
Address: 05h
Default: Metal
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Spare = 0
Spare = 0
Spare = 0
FID_3
FID_2
FID_1
FID_0
Bit
FID[3..0]
Bit Description
Feature Identification
0000: Default Configuration
Table 23. DC to DC VOLTAGE PROG REGISTER
Name: PROG
Type: RW
Address: 11h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
EN
Vout[6..0]
Bit
Bit Description
Vout[6..0]
Sets the DC to DC converter output
0000000b = 600 mV − 1111111b = 1393.75 mV (steps of 6.25 mV)
EN
EN Pin Gating
0: Disabled
1: Enabled
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24
NCP6343
Table 24. POWER GOOD REGISTER
Name: PGOOD
Address: 12h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Spare = 0
Spare = 0
DISCHG
Spare = 0
Spare = 0
PGDVS
PGDCDC
Bit
Bit Description
PGDCDC
PGDVS
Power Good Enabling
0 = Disabled
1 = Enabled
Power Good Active On DVS
0 = Disabled
1 = Enabled
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
Table 25. TIMING REGISTER
Name: TIME
Address: 13h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
DVSup
D1
D0
DELAY[2..0]
DVSdown[1..0]
DBN_Time[1..0]
Bit
Bit Description
DBN_Time[1..0]
EN debounce time
00 = No debounce
01 = 1−2 ms
10 = 2−3 ms
11 = 3−4 ms
DVSup
DVS Speed for up DVS
0 = 6.25 mV step / 0.166 ms
1 = 6.25 mV step / 2.666 ms
DVSdown[1..0]
DVS Speed for down DVS
00 = 6.25 mV step / 0.333 ms
01 = 6.25 mV step / 0.666 ms
10 = 6.25 mV step / 1.333 ms
11 = 6.25 mV step / 2.666 ms
DELAY[2..0]
Delay applied upon enabling (ms)
000b = 0 ms − 111b = 14 ms (Steps of 2 ms)
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25
NCP6343
Table 26. COMMAND REGISTER
Name: COMMAND
Type: RW
Address: 14h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PWM
Spare = 0
DVSMODE
Sleep_Mode
Spare = 0
Spare = 0
Spare = 0
Spare = 0
Bit
Bit Description
Sleep_Mode
DVSMODE
PWM
Sleep mode
0 = Low Iq mode when EN low
1 = Force product in sleep mode
DVS transition mode selection
0 = Auto
1 = Forced PWM
DCDC Operating mode
0 = Auto
1 = Forced PWM
Table 27. OUTPUT STAGE MODULE SETTINGS REGISTER
Name: MODULE
Type: RW
Address: 15h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
MODUL[3..0]
Spare =0
Spare =0
Spare =0
Spare =0
Bit
MODUL [3..0]
Bit Description
Number of modules
0000 = 1 Module − 0111 ~ 1111 = 8 Modules (Steps of 1)
Table 28. LIMITS CONFIGURATION REGISTER
Name: LIMCONF
Type: RW
Adress: 16h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
IPEAK[1..0]
Bit
TPWTH[1..0]
Spare = 0
FORCERST
RSTSTATUS
REARM
Bit Description
REARM
Rearming of device after TSD
0: No re−arming after TSD
2
1: Re−arming active after TSD with no reset of I C registers: new power−up sequence is initiated with
2
previously programmed I C registers values
RSTSTATUS
FORCERST
TPWTH[1..0]
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Force Reset Bit
0 = Default value. Self cleared to 0
1: Force reset of internal registers to default
Thermal pre−Warning threshold settings
00 = 83°C
01 = 94°C
10 = 105°C
11 = 116°C
IPEAK
Inductor peak current settings
00 = 2.9 A (Iload 2.0 A)
01 = 2.9 A (Iload 2.0 A)
10 = 3.4 A (Iload 2.5 A)
11 = 3.9 A (Iload 3.0 A)
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26
NCP6343
APPLICATION INFORMATION
NCP6243
Core
References
Oscillator
A1
B1
PVIN
SW
Supply
Input
D1
E1
AVIN
Supply
Input
C1
10 mF
AGND
DCDC
3.0 A
A2
B2
470 nH
Thermal
Protection
22 mF
A3
B3
PGND
FB
C3
Enable
Control
Input
EN
D2
C2
Operating
Mode
E3
Core
Processor
Memory
DCDC
3 MHz
Controller
D3
E2
SDA
SCL
Control
Processor
Sense
2
22 mF
I C
2
I C Control
Interface
Figure 45. Typical Application Schematic
Output Filter Design Considerations
The output filter introduces a double pole in the system at
a frequency of:
Components Selection
Inductor Selection
The inductance of the inductor is determined by given
peak−to−peak ripple current I of approximately 20% to
50% of the maximum output current I
trade−off between transient response and output ripple. The
1
fLC
+
Ǹ
L_PP
2 @ p @ L @ C
for a
OUT_MAX
NCP6343 internal compensation network is optimized for
a typical output filter comprising a 470 nH inductor and
22 mF capacitor as describes in the basic application
schematic is described by Figure 16.
inductance corresponding to the given current ripple is:
ǒV
Ǔ
IN * VOUT @ VOUT
IN @ fSW @ IL_PP
L +
V
Voltage Sensing Considerations
The selected inductor must have high enough saturation
current rating to be higher than the maximum peak current
In order to regulate power supply rail, NCP6343 should
sense its output voltage. Thanks to the FB pin, the IC can
support two sensing methods:
that is
IL_PP
• Normal case: the voltage sensing is achieved close to
the output capacitor. In that case, FB is connected to the
output capacitor positive terminal (voltage to regulate).
• Remote sensing: In remote sensing, the power supply
rail sense is made close to the system powered by the
NCP6343. The voltage to system is more accurate, since
PCB line impedance voltage drop is within the regulation
loop. In that case, we recommend connecting the FB pin
to the system decoupling capacitor positive terminal.
I
L_MAX + IOUT_MAX )
2
The inductor also needs to have high enough current
rating based on temperature rise concern. Low DCR is good
for efficiency improvement and temperature rise reduction.
Table 29 shows recommended.
Table 29. INDUCTOR SELECTION
Supplier
Cyntec
Cyntec
TOKO
TOKO
TOKO
TDK
Part #
Value (mH) Size (mm) (L x l x T) DC Rated Current (A) DCR Max at 255C (mW)
PIFE20161B−R47−MS−11
PIFE25201T−R47−MS−11
DFE201612P−H−R47M
DFE201610R−H−R47N
DFE201612R−H−R47N
TFM252010A−R47M
SPM6530T−R47M170
0.47
0.47
0.47
0.47
0.47
0.47
0.47
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.2
2.0 x 1.6 x 1.0
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.0
7.1 x 6.5 x 3.0
3.9
4.5
4.3
3.3
3.8
4.5
20
36
41
33
48
40
30
4
TDK
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27
NCP6343
Output Capacitor Selection
The input capacitor also needs to be sufficient to protect
the device from over voltage spike, and normally at least
4.7 mF capacitor is required. The input capacitor should be
located as close as possible to the IC. All PGNDs are
connected together to the ground terminal of the input cap
which then connects to the ground plane. All PVIN are
connected together to the Vbat terminal of the input cap
which then connects to the Vbat plane.
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
high transient load performance high output capacitor value
must be used. For a given peak−to−peak ripple current I
L_PP
in the inductor of the output filter, the output voltage ripple
across the output capacitor is the sum of three components
as below.
V
OUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high−frequency loop area. It is also
good for efficiency improvement.
• The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
• SW node should be a large copper, but compact
because it is also a noise source.
Where V
is a ripple component by an equivalent
OUT_PP(C)
total capacitance of the output capacitors, V
a ripple component by an equivalent ESR of the output
capacitors, and V is a ripple component by an
equivalent ESL of the output capacitors. In PWM operation
mode, the three ripple components can be obtained by
is
OUT_PP(ESR)
OUT_PP(ESL)
IL_PP
VOUT_PP(C)
+
,
and
V
OUT_PP(ESR)+IL_PP@ESR
8 @ C @ fSW
ESL
ESL ) L
VOUT_PP(ESL)
+
@ VIN
and the peak−to−peak ripple current is
ǒV
Ǔ
IN * VOUT @ VOUT
IN @ fSW @ L
IL_PP
+
V
• It would be good to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Try best to avoid overlap of input ground loop
and output ground loop to prevent noise impact on
output regulation.
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
So that the minimum output capacitance can be calculated
regarding to a given output ripple requirement V
PWM operation mode.
.
OUT_PP(C)
in
OUT_PP
• Arrange a “quiet” path for output voltage sense, and
make it surrounded by a ground plane.
IL_PP
CMIN
+
8 @ VOUT_PP @ fSW
Thermal Layout Considerations
Good PCB layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC to connect
the inner ground layers to reduce thermal impedance.
• Use large area copper especially in top layer to help
thermal conduction and radiation.
Input Capacitor Selection
One of the input capacitor selection guides is the input
voltage ripple requirement. To minimize the input voltage
ripple and get better decoupling in the input power supply
rail, ceramic capacitor is recommended due to low ESR and
ESL. The minimum input capacitance regarding to the input
ripple voltage V
is
IN_PP
2
( )
OUT_MAX @ D * D
I
VOUT
VIN
D +
CIN_MIN
+
where
V
IN_PP @ fSW
• Use two layers for the high current paths (PVIN,
PGND, SW) in order to split current in two different
paths and limit PCB copper self heating.
In addition, the input capacitor needs to be able to absorb
the input current, which has a RMS value of
Ǹ
I
IN_RMS + IOUT_MAX @ D * D2
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28
NCP6343
(See demo board example Figure 47)
Figure 46. Layout Recommendation
Legend:
In blue are top layer planes and wires
In white are layer1 plane and wires (just below top layer)
Big circles gray are normal vias
Small circles gray are top to layer1 vias
Figure 47. Demo Board Example
Input capacitor placed as close as possible to the IC.
PGND directly connected to Cin input capacitor, and then
connected to the GND plane: Local mini planes used on the
top layer (blue) and layer just below top layer (white) with
laser vias.
PVIN directly connected to Cin input capacitor, and then
connected to the Vin plane. Local mini planes used on the top
layer (blue) and layer just below top layer (white) with laser
vias.
SW connected to the Lout inductor with trace between input
capacitor terminals on top layer (blue) and local mini planes
on the layer just below top layer (white) with laser vias.
AVIN connected to the Vin plane just after the capacitor.
AGND directly connected to the GND plane.
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29
NCP6343
ORDERING INFORMATION
†
Device
Marking
Package
Comment
Shipping
NCP6343FCT1G**
6343
6343A
6343B
6343D
6343V
6343S
6343M
6343X
WLCSP15 without Back Coating
(Pb–Free)
I2C address 0x1C
(0011100x b)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NCP6343AFCCT1G**
NCP6343BFCCT1G**
NCP6343DFCCT1G**
NCP6343AVFCCT1G*
NCP6343SFCCT1G*
NCP6343MFCCT1G*
NCP6343XFCCT1G
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x14
(0010100x b)
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x1C
(0011100x b)
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x14
(0010100x b)
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x14
(0010100x b)
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x10
(0010000x b)
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x18
(0011000x b)
WLCSP15 with Back Coating
(Pb–Free)
I2C address 0x1C
(0011100x b)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Not recommended for new designs.
**This device is End of Life. Please contact sales for additional information and assistance with replacement devices.
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30
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP15, 1.34x1.99x0.548
CASE 567GB
ISSUE D
DATE 02 JUN 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
ALYW
G
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84651E
WLCSP15, 1.34X1.99x0.548
PAGE 1 OF 1
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associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
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