NCP81565MNTXG [ONSEMI]
6+2 Phase Output Controller with SVID Interface for Computer CPU Applications;
| 型号： | NCP81565MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | 6+2 Phase Output Controller with SVID Interface for Computer CPU Applications |
| 文件： | 总18页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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6 + 2 Phase Output
Controller with SVID
Interface for Computer CPU
Applications
1
52
QFN52 6x6, 0.4P
CASE 485BE
NCP81565
MARKING DIAGRAM
The NCP81565 is a dual rail, six plus two phase buck solution
optimized for Intel’s IMVP9.1 CPUs. The multi−phase rail control
system is based on Dual−Edge pulse−width modulation (PWM)
combined with DCR current sensing. This provides an ultra−fast
initial response to dynamic load events and reduced system cost. The
NCP81565 has an ultra−low offset current monitor amplifier with
programmable offset compensation for high accuracy current
monitoring.
NCP81565
AWLYYWWG
A
WL
YY
= Assembly Site
= Wafer Lot
= Year
WW
G
= Work Week
= Pb−Free Package
Features
• Vin Range 4.5 V to 21 V
• Startup into Pre−Charged Loads While Avoiding False OVP
• Digital Soft Start Ramp
ORDERING INFORMATION
• Adjustable Vboot
†
Device
NCP81565MNTXG
Package
Shipping
• High Impedance Differential Output Voltage Amplifier
• Dual VID Table Support to be Compatible with IMVP9.1
• Support High Current Extensions
QFN52
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Dynamic Reference Injection
• Programmable Output Voltage Slew Rates
• Dynamic VID Feed−Forward
• Differential Current Sense Amplifiers for Each Phase
• Programmable Adaptive Voltage Positioning (AVP)
• Adjustable Switching Frequency Range
• Digitally Stabilized Switching Frequency
• UltraSonic Operation
• Supports Acoustic Noise Mitigation Function
• Support for VCCIN_AUX IMON Input
• Meets Intel’s IMVP9.1 Specifications
• Current Mode Dual Edge Modulation for Fast Initial Response to
Transient Loading
• This is a Pb−Free Device
Typical Applications
• Desktop, Notebook and Ultra−book Computers
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
May, 2022 − Rev. 0
NCP81565/D
NCP81565
TSENSE
TSENSEA
VR_HOT#
Thermal
Monitor
UVLO
&
VSPA
VSNA
ENABLE
AUXDAC
GND
DIFFAMP
VSP
VSN
DAC
GND
CSREFA
ENABLE
DIFFAMP
VSP
VSN
DAC
VSPA
CSREF
VR Ready
DIFFA
Comparator
ERROR
AMP
VSNA
AUXDAC
DIFF
FBA
ERROR
AMP
COMPA
FB
VSP
VSN
OVP
OVP
Current
Measurement &
Limit
ILIMA
COMP
AUX
OVP
VSPA
VSNA
IOUTA
ILIM
IOUT
OVPA
Current
Measurement &
Limit
ICC*2 MAIN RAIL
CSSUMA
CSREFA
CSAMP
CSSUM
CSREF
CSAMP
CSCOMPA
ICC*2_MAIN_RAIL
CSCOMP
VSP-VSN
VSPA-VSNA
TSENSE
TSENSEA
IOUT
SDIO
ALERT#
SCLK
Data
SVID
ADC
Registers
Interface
IOUTA
ROSC
MUX
DAC
DAC
DAC
AUXDAC
ROSCA
VBOOT
SV_ADDR_SR
PSYS
ICCMAX_AUXIN
AUX_IN
PH_CONFIG
IPH6
IPH5
IPH4
IPH3
IPH2
RAMP6
CSP6
CSP5
CSP4
CSP3
CSP2
CSP1
RAMP5
RAMP4
RAMP3
RAMP2
Ramp
PWM
Current
Balance
IPH1A
IPH2A
RAMP1A
RAMP2A
CSP1A
CSP2A
Generators
Generators
PWM
Current
Balance
Generators
IPH1
RAMP1
Power State
Stage
Power State Stage
Figure 1. Internal Block Diagram
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2
NCP81565
VIN
VCC
EN
+5V
VRMP
VIN
VR_EN
DrMOS
VCCIO
VCCIO
DRON
DRON
VIN
SW
EN
PWM
SW1
PWM1/SV_ADDR_SR
VCCCORE
SDIO
ALERT
SCLK
CPU_SDIO
CPU_ALERT
CPU_SCLK
SDIO
ALERT#
SCLK
CSP1
CSREF
CSREF
VIN
DrMOS
VPULL-UP
DRON
VIN
SW
EN
SW2
PWM2/VBOOT
CSP2
PWM
VR_HOT#
VR_RDY
VR_HOT#
VR_RDY
VIN
CSREF
CSREF
CSREF
CSREF
CSREF
DrMOS
DRON
DRON
DRON
DRON
VIN
SW
EN
SW3
PSYS
PSYS
PWM3/ICCMAX
CSP3
PWM
(BATTERY CHARGER)
VIN
AUX_IN
AUX_OUT
DrMOS
(AUX Power)
VIN
SW
EN
SW4
PWM4/ROSC
CSP4
PWM
VCCCORE
VCCCORE_SENSE
VSP
VSN
VIN
VSSCORE_SENSE
GND
DrMOS
VIN
SW
EN
SW5
DIFF
FB
PWM5/ROSCA
CSP5
PWM
VIN
COMP
DrMOS
SW1
SW2
SW3
SW4
SW5
SW6
CSSUM
VIN
SW
EN
SW6
PWM6/ICCMAX_AUXIN
CSP6
PWM
NTC
CSCOMP
ILIM
VIN
IOUT
ICC*2_MAIN_RAIL
TSENSE
NTC
VCCGT
VIN
VCCGT_SENSE
VSPA
VSNA
DrMOS
DRON
VSSGT_SENSE
GND
VIN
SW
EN
VCCGT
SW1A
PWM
PWM1A/ICCMAXA
DIFFA
FBA
CSP1A
CSREFA
CSREFA
COMPA
SW1A
SW2A
CSSUMA
VIN
DrMOS
NTC
CSCOMPA
ILIMA
DRON
VIN
SW
EN
SW2A
PWM2A
CSP2A
PWM
IOUTA
TSENSEA
GND
CSREFA
NTC
Figure 2. Typical Application Circuit
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NCP81565
Figure 3. Pinout Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
NC
Description
1
2
3
4
5
6
7
8
9
No Connect
EN
Enable. High enables both rails
Serial VID data interface
Serial VID ALERT#
SDIO
ALERT#
SCLK
VR_RDY
VCC
Serial VID clock
VR_RDY indicates both rails are ready to accept SVID commands
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
System power signal input. A resistor to ground scales this signal.
PSYS
VRMP
Feed−forward input of Vin for the ramp−slope compensation. The voltage fed into this pin is used to
control the ramp of the PWM slopes.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VR_HOT#
AUX_IN
OD output. Indicates high VR temperature or per channel OCP condition.
AUX IMON Input on 0x0Dh SVID domain.
ICC*2_MAIN_RAIL Pulldown on this pin programs ICCMAX on main rail from 255 to 511A.
IOUTA
VSNA
Total output current monitor for regulator 2.
Differential output voltage sense negative for regulator 2.
VSPA
Differential output voltage sense positive for regulator 2.
DIFFA
Output for regulator 2’s differential remote sense amplifier.
FBA
Error amplifier voltage feedback for regulator 2.
COMPA
CSCOMPA
ILIMA
Output of the error amplifier and the inverting inputs of the PWM comparators of output for regulator 2.
Output of total−current−sense amplifier for regulator 2.
Over−current threshold setting – programmed with a resistor to CSCOMPA output for regulator 2.
Inverting input of total−current−sense amplifier of output for regulator 2.
Total−current−sense amplifier reference voltage input output for regulator 2.
Non−inverting input to current−balance amplifier for Phase 1 output for regulator 2.
CSSUMA
CSREFA
CSP1A
CSP2A
Non−inverting input to current−balance amplifier for Phase 2 output for regulator 2. Pull this pin to Vcc
to disable Phase 2.
25
26
NC
No Connect
TSENSEA
Temperature sense input for regulator 2.
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NCP81565
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
27
PWM1A / ICCMAXA PWM1 output for regulator 2. During startup, ICCMAXA for two−phase regulator is programmed with a
pull−down resistor.
28
29
30
PWM2A
DRON
PWM2 output for regulator 2.
External FET driver enable for discrete driver or ONSemi DrMOS.
PWM6 /
ICCMAX_AUXIN
PWM6 output for regulator 1 / Pulldown resistor on this pin programs ICCMAX for the AUX_IN monitor-
ing rail.
31
PWM5 / ROSCA
PWM5 output for regulator 1 / Pulldown on this pin programs RoscA % dependent on main rail value
and ICCMAX range for main rail.
32
33
34
35
PWM4 / ROSC
PWM4 output for regulator 1 / Pulldown on this pin programs Rosc value for main rail.
PWM3 / ICCMAX PWM3 output for regulator 1 / Pulldown on this pin programs ICCMAX for regulator 1 during startup.
PWM2 / VBOOT
PWM2 output for regulator 1 / Pin−program for regulator 1 and regulator 2 Vboot.
PWM1 /
SV_ADDR_SR
PWM1 output for regulator 1 / Pulldown on this pin configures SVID address, slew rate and Intel Propri-
etary Current Protection Feature.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
−
TSENSE
CSP1
CSP2
CSP3
CSP4
CSP5
CSP6
CSREF
CSSUM
ILIM
Temperature sense input for regulator 1.
Differential current sense positive for Phase 1 of regulator 1.
Differential current sense positive for Phase 2 of regulator 1.
Differential current sense positive for Phase 3 of regulator 1.
Differential current sense positive for Phase 4 of regulator 1.
Differential current sense positive for Phase 5 of regulator 1.
Differential current sense positive for Phase 6 of regulator 1.
Total−current−sense amplifier reference voltage input for regulator 1.
Inverting input of total−current−sense amplifier for regulator 1.
Over−current threshold setting – programmed with a resistor to CSCOMP for regulator 1.
Output of total−current−sense amplifier for regulator 1.
Output of the error amplifier and the inverting inputs of the PWM comparators for regulator 1.
Error amplifier voltage feedback for regulator 1.
CSCOMP
COMP
FB
DIFF
Output of the regulator 1 differential remote sense amplifier.
Differential output voltage sense positive for regulator 1.
Differential output voltage sense negative for regulator 1.
Total output current monitor for regulator 1.
VSP
VSN
IOUT
FLAG
GND
1. ‘Regulator 1’ is referred to as ‘Main’ rail throughout the datasheet. ‘Main’ is the primary rail with the highest phase count.
2. ‘Regulator 2’ is referred to as ‘A’ rail throughout the datasheet.
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NCP81565
Table 2. MAXIMUM RATINGS (Note 3)
V
V
I
I
SINK
Pin Symbol
COMP
MAX
MIN
SOURCE
2 mA
2 mA
2 mA
2 mA
VCC + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
GND + 0.3 V
GND + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
6.0 V
−0.3 V
−0.3 V
2 mA
2 mA
2 mA
2 mA
1 mA
2 mA
2 mA
2 mA
2 mA
COMPA
CSCOMP
CSCOMPA
PWMX
−0.3 V
−0.3 V
−0.3 V
VSN
GND – 0.3 V
GND – 0.3 V
−0.3 V
1 mA
1 mA
2 mA
2 mA
2 mA
VSNA
DIFF
DIFFA
−0.3 V
VR_RDY
VCC
−0.3 V
−0.3 V
VRMP
VCC + 0.3 V
3.6 V
−0.3 V
SCLK, SDIO
All Other Pins
−0.3 V
VCC + 0.3 V
−0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. All signals referenced to GND unless noted otherwise
Table 3. ESD Capability
Description
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charged Device Model (Note 4)
Symbol
Typ
2000
750
Unit
V
ESD
ESD
HBM
CDM
V
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latch−up Current Maximum Rating: 200 mA per JEDEC standard: JESD78.
Table 4. RECOMMENDED OPERATING CONDITIONS
Description
Symbol
Min
4.75
−40
−40
Max
5.25
125
100
Unit
V
VCC Voltage Range
VCC
Operating Junction Temperature Range (Note 5)
Operating Ambient Temperature Range
T
J
°C
°C
T
A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. JEDEC JESD 51−7 with 0 LFM
Table 5. THERMAL CHARACTERISTICS
Description
Thermal Characteristic QFN Package
Symbol
Typ
Unit
°C/W
°C
R
68
JA
Maximum Storage Temperature Range
T
STG
−40 to +150
Moisture Sensitivity Level QFN Package
Soldering Temperature
MSL
1
°C
260
30
Junction−to−Ambient, Thermal Resistance (Note 6)
Junction−to−Case (Top), Thermal Resistance (Note 6)
Junction−to−Board Heat Spreader, Thermal Resistance (Note 6)
Junction−to−Case (Top), Measurement Reference (Note 6)
6. JEDEC JESD 51−7 with 0 LFM
q
°C/W
°C/W
°C/W
°C/W
JA
q
18
JC(TOP)
q
1.0
1.1
JB
Y
J−CT
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NCP81565
Table 6. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; 4.75 V < V < 5.25 V; C = 0.1 mF
VCC
A
CC
Parameter
BIAS SUPPLY
Test Conditions
Min
Typ
Max
Unit
VCC Voltage Range
Quiescent Current
4.75
5.25
V
PS0
27
25
24
20
mA
mA
mA
mA
mA
mA
V
PS1
PS2
PS3
PS4
79
64
Enable low
VCC Rising
VCC Falling
UVLO Threshold
4.5
4.1
V
VCC UVLO Hysteresis
100
100
mV
VRMP
VIN Supply Range
VRMP range prior to external voltage divider re-
sistor network with 1/12 ratio
4.5
21
V
UVLO Threshold
VRMP Rising
VRMP Falling
0.355
V
V
0.250
UVLO Hysteresis
mV
ENABLE INPUT
Upper Threshold
Activation Level
0.8
V
V
Lower Threshold
Deactivation Level
0.3
PHASE DETECTION
CSP Pin Threshold Voltage
Phase Detect Timer
IMVP9.1 DAC (PROTOCOL 0Eh)
System Voltage Accuracy
VCC−0.4
V
1.5
ms
0.25 V < DAC < 0.495 V (at 25°C only)
0.5 V < DAC < 0.745 V (at 25°C only)
0.75 V < DAC < 1.52 V (at 25°C only)
−10
−8
10
8
mV
mV
%
−0.5
0.5
DAC SLEW RATE
Soft Start Slew Rate
Slew Rate Slow
Slew Rate Fast
DRON
1/4 fast
1/4 fast
> 10
mV/ms
mV/ms
mV/ms
Resistor Selectable (Table 9)
Output High Voltage
Output Low Voltage
TSENSE
Sourcing 1 mA
Sinking 1 mA
3
V
V
0.1
TSENSE Bias Current
Alert#
115.5
120
556
595
124.5
mA
mV
mV
Assert Threshold
De−Assert Threshold
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
N* is the phase configuration number in PS0.
7. Tested at 25°C / 5 V VCC only.
8. Guaranteed by characterization, not production tested.
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NCP81565
Table 6. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; 4.75 V < V < 5.25 V; C = 0.1 mF
VCC
A
CC
Parameter
Test Conditions
Min
Typ
Max
Unit
TSENSE
VR_HOT
Assert Threshold
De−Assert Threshold
517
556
mV
mV
VR_RDY OUTPUT
Output Low Saturation Voltage
VR_RDY Rise Time
I
= −4 mA
0.1
110
20
0.3
150
150
V
VR_RDY
1 KW pull−up to 3.3 V, C
= 45 pF
ns
ns
TOT
VR_RDY Fall Time
SVID (SDIO and SCLK)
SVID Voltage Low Level (Note 7)
SVID Voltage High Level (Note 7)
SVID Pull Down Resistance
SDIO Output Low Voltage
SVID Clock to Data Delay (Note 8)
SVID Setup Time (Note 8)
SVID Hold Time (Note 8)
Pad and Pin Capacitance (Note 7)
ALERT#
VIL
0.45
V
V
VIH
0.65
4
5
W
VOL
TCO
0.3
12
V
ns
ns
ns
pF
7
14
VOL (Output Low)
0.3
V
OVP AND UVP
Absolute Over Voltage Threshold
10 mV DAC step
3.3
2.4
3.44
2.5
3.6
2.65
475
V
V
During Soft Start − CSREF Rising
5 mV DAC step
During Soft Start − CSREF Rising
Over Voltage Threshold Above DAC
Over Voltage Delay
VSP−VSN−VID Rising
350
400
50
mV
ns
VSP−VSN Rising to PWM Low
Under Voltage Threshold Below DAC− VSP−VSN−VID Falling
DROOP (VUVM)
−440
−400
−360
mV
Under Voltage Delay
5
ms
PWM OUTPUT
Output High Voltage
Output Mid Voltage
Output Low Voltage
DIFFERENTIAL AMPLIFIER
Input Bias Current
−3 dB Bandwidth
Sourcing 500 mA
Vcc−0.2
V
V
V
No Load, Power State 2
Sinking 500 mA
1.7
1.8
1.9
0.7
VSP = 1.3 V
200
500
nA
MHz
V/V
CL = 20 pF, RL = 10 kW
VSP − VSN = 0.5 V to 1.3 V
22.5
1
Closed Loop DC Gain
ERROR AMPLIFIER
Input Bias Current
DC Gain
Input = 1.3 V
−400
400
nA
dB
CL = 20 pF, RL = 10 kW
80
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
N* is the phase configuration number in PS0.
7. Tested at 25°C / 5 V VCC only.
8. Guaranteed by characterization, not production tested.
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NCP81565
Table 6. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; 4.75 V < V < 5.25 V; C = 0.1 mF
VCC
A
CC
Parameter
ERROR AMPLIFIER
Test Conditions
Min
Typ
Max
Unit
−3 dB Bandwidth
CL = 20 pF, RL = 10 kW
DVin = 100mV, G=−10V/V,
20
5
MHz
Slew Rate
V/ms
DVout = 1.5 V to 2.5 V, CL = 20 pf, RL = 10 kW
OVER−CURRENT PROTECTION (ILIM)
ILim Threshold Current
(Delayed OCP shutdown)
PS0
8.5
10
10/N*
15
11.5
16.5
mA
mA
mA
mA
ms
PS1, PS2, PS3
PS0
ILim Threshold Current
(Immediate OCP shutdown)
13.5
PS1, PS2, PS3
Immediate
Delayed
15/N*
1.3
Shutdown Delay
50
ms
IOUT OUTPUT
Current Gain
IOUT/ILIM
(RLIM = 20 kW, RIOUT = 5 kW,
Vout = 0.8 V, 1.25 V, 1.52 V)
9.5
10
10.5
A/A
PWM GENERATOR
PWM Minimum Pulse Width
0% Duty Cycle
40
1.3
ns
V
Comp Voltage for PWM Held Low
100% Duty Cycle
Comp Voltage for PWM Held High
VIN at 4.5 V
1.75
V
100% Duty Cycle
Comp Voltage for PWM Held High
VIN at 21 V
3.4
V
CURRENT SUMMING AMPLIFIER (CSAMP)
Offset Voltage
−500
−10
500
10
mV
mA
Input Bias Current
CSSUM = CSREF = 1.0 V
Open Loop Gain
80
10
dB
Open Loop Unity Gain Bandwidth
CURRENT BALANCE AMPLIFIER
C = 20 pF to GND, R = 10 kW to GND
MHz
L
L
Differential Mode Input Voltage Range CSNx = 1.2 V
−100
100
mV
PSYS
Full Scale Input Voltage
Disable Threshold
2.5
V
V
VCC−0.4
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
N* is the phase configuration number in PS0.
7. Tested at 25°C / 5 V VCC only.
8. Guaranteed by characterization, not production tested.
Start Up
Following the rise of VCC above the UVLO threshold,
externally programmed configuration data is collected, and
all PWM outputs are set to Mid−level to prepare the gate
drivers of the power stages for activation. When the
controller is enabled, DRON is asserted (high) to activate the
external gate drivers. A digital counter steps the DAC up
from zero to the target boot voltage based on the Soft Start
Slew Rate in the spec table. As the DAC ramps, the PWM
outputs of each rail will change from Mid−level to high
when the first PWM pulse for that rail is produced. When the
controller is disabled, the PWM signals return to Mid−level.
The VR_RDY signal is asserted when the controller is ready
to accept the first SVID command.
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NCP81565
DEVICE CONFIGURATION
ICCMAX
Phase and Rail Configuration
During start−up, the number of operational phases of the
multiphase rail is determined by the internal circuitry
monitoring the CSP inputs. If a reduced phase count is
required, the appropriate CSP pins should be externally
pulled to VCC with a resistor during startup.
Resistors to ground on the PWM3/ICCMAX,
PWM1A/ICCMAXA and PWM6/ICCMAX_AUXIN pins
programs these registers at the time the part is enabled.
10 mA is sourced from this pin to generate a voltage on the
program resistor. The value of the register is set by the
equation below. The resistor value should be no less than
10 kW.
Basic Configuration
The controller has four basic configuration features. On
power up a 10 mA current is sourced from these pins through
a resistor connected to this pin and the resulting voltage is
measured. The following features will be programmed:
R @ 10 mA @ 255
ICCMAX +
2.5 V
ICCMAX Additional Capability
There is an option to extend the current range of the main
rail by scaling the lsb size (See Table 7). See Table 11 for
details on how to enable this mode.
• SVID Address
• Slew Rate
• V
BOOT
• Output Voltage Step
Table 7. ICCMAX CAPABILITY SCALING
ICCMAX_ADD[4:0]
Switching Frequency
Power
Power [4:2]
010
Current [1:0]
Switching frequencies between 180 kHz and 1.17 MHz
are programmed at startup with pulldown resistors on Rosc
and RoscA pin. Switching frequency options are shown in
Table 12.
Scaling
4 W /bit
8 W / bit
ICC Scaling
1 A / bit
00
01
011
2 A / bit
Table
8
shows the rail configurations when
ICC*2_MAIN_RAIL mode is enabled and disabled.
Table 8. RAIL SETTINGS FOR ICC*2_MAIN_RAIL MODE
ICC*2_MAIN_RAIL
Disabled
1A
Enabled
2A
ICCMAX LSB Size
IOUT LSB Size
POUT LSB Size
1A
2A
4 W
8 W
Main Rail
HIGHPOWER_ICCMAX_ADD[1:0]
00
01
HIGHPOWER_ICCMAX_ADD[4:2]
Loadline Weighting
ICCMAX LSB Size
010
011
93.75%
187.5%
1A
1A
IOUT LSB Size
POUT LSB Size
4 W
00
A Rail
HIGHPOWER_ICCMAX_ADD[1:0]
HIGHPOWER_ICCMAX_ADD[4:2]
Loadline Weighting
010
93.75%
1A
ICCMAX LSB Size
IOUT LSB Size
1A
POUT LSB Size
4 W
00
VCCIN_AUX
HIGHPOWER_ICCMAX_ADD[1:0]
HIGHPOWER_ICCMAX_ADD[4:2]
010
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10
NCP81565
Ultrasonic Mode
Table 10. VBOOT AND OUTPUT VOLTAGE STEP
The switching frequency of a rail in DCM will decrease
at very light loads. Ultrasonic Mode forces the switching
frequency to stay above the audible range.
Resistor
V
BOOT
(V)
V
BOOT
(V)
Output
(kW)
Main rail
A rail
0 V
Voltage Step
10
0 V
Both rail
5 mV/step
CCM/DCM Operation
14
0 V
1.05 V
0 V
In PS0, all rails operate in Continuous Conduction Mode
(CCM) which uses the dual−edge control methodology.
However, if PS0 is configured as one−phase instead of
multi−phase, the control methodology changes to RPM
operation. RPM has great transient performance in
one−phase CCM operation. The RPM frequency average
DC value is targeted to be similar to the PS0 Dual Edge
frequency. However, the switching frequency of RPM
depends on input voltage, output voltage, load current,
inductor value, and output capacitor value. In PS1, all rails
operate in one−phase CCM RPM. In PS2 and PS3, all rails
operate in either CCM or Discontinuous Conduction Mode
(DCM). It depends on load current in order to prevent loss
of efficiency from negative inductor current.
18.7
24.3
30.9
38.3
47.5
59
1.05 V
1.05 V
0 V
1.05 V
0 V
B oth rail
10mV/step
0 V
1.8 V
0 V
1.8 V
1.8 V
0 V
1.8 V
0 V
71.5
86.6
105
127
154
187
221
280
Main rail
5 mV/step.
A rail
10 mV/step.
0 V
1.8 V
0 V
1.05 V
1.05 V
0 V
1.8 V
0 V
Main rail
10 mV/step.
A rail
5 mV/step.
PSYS
1.8 V
0 V
0 V
The PSYS pin is an analog input to the VR controller. It
is a system input power monitor that facilitates the
monitoring of the total platform system power. For more
information regarding PSYS please contact Intel, Inc.
1.05 V
1.05 V
1.8 V
AUX_IN
The AUX_IMON current monitor input is a means of
measuring the VCCIN_AUX platform VR output current
using the IMVP9.1 ADC.
Table 9. SVID ADDRESS AND SLEW RATE
Intel
Proprietary
Current
Protection
Feature
Main Rail
SVID
Address
A Rail
SVID
Address
Programming Pin
Resistor
(kW)
SR
(mV/ms)
This is a multifunction select pin used to set the operation
of multiple features and the combination of these features
enabled/disable. Items programmed on this pin are
ICC*2_MAIN_RAIL which allows the user to select if the
ICCMAX and IOUT reporting for the main rail is a 1 A or
2 A LSB step size. When off, the resolution is 1 A per LSB.
When on, the resolution is set to 2 A per LSB which allows
reporting of over 255 A on the main rail only.
The other options include dithering and acoustic noise
solution.
10
10
30
48
10
30
48
10
30
48
10
30
48
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
ON
ON
14
18.7
24.3
30.9
38.3
47.5
59
ON
OFF
OFF
OFF
ON
ON
71.5
86.6
105
127
ON
OFF
OFF
OFF
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11
NCP81565
Table 11. PIN OF ICC*2_MAIN_RAIL CONFIGURATION
Resistor (kW)
10
ICC*2 Main Rail
Acoustic Noise Solution
Dithering
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
18.7
30.9
OFF
ON
47.5
ON
71.5
OFF
OFF
ON
OFF
ON
105
ON
154
ON
OFF
ON
221
ON
ON
Table 12. SWITCHING FREQUENCY
R
/R
OSC OSCA
Switching Frequency (KHz)
Control by Pin
1 Phase ~ 6 Phase
Resistor (kW)
10
180
225
270
315
360
405
450
495
540
630
720
810
900
990
1080
1170
14
18.7
24.3
30.9
38.3
47.5
59
71.5
86.6
105
127
154
187
221
280
Input Voltage Feed−Forward (VRMP Pin)
Ramp generator circuits are provided for the dual−edge
modulator. The ramp generators implement input voltage
feed−forward control by varying the ramp slopes
proportional to the VRMP pin voltage. The VRMP pin also
has a UVLO function, which is active only after the
controller is enabled. The VRMP pin is high impedance
input when the controller is disabled. For multi−phase
operation, the dual−edge PWM ramp amplitude is changed
according to the following:
Figure 4. Ramp Feed Forward
An external voltage divider is required on this VRMP pin.
In order to scale the voltage seen on the VRMP pin, the
voltage divider on the pin needs to be setup to maintain a
VRMPPP + 0.1 @ VVRMP
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12
NCP81565
ratio of 1/12. Typical resistor values may include 1 MW Rup
/ 90.9 kW Rdown or 1.1 MW Rup / 100 kW Rdown. UVLO
on VRMP is inactive in PS4 power state and PS3 when a
VID to 0 V is received.
senses the inductor temperature, and compensates both the
DC gain and the filter time constant for the change in DCR
with temperature. The Phase 1 inductor is chosen for the
thermistor location so that the temperature of the inductor
providing current in the PS1 power mode.
Rup
Input Voltage
Feed Forward
Control
The DC gain equation for the DC total current signal is:
VRMP
VIN
R
CS1@Rth
RCS2
)
Rdown
R
CS1)Rth
V
CSCOMP * VCSREF
+
@ DCR @ IOUT
Rph
Set the DC gain by adjusting the value of the Rph resistors
in order to make the ratio of total current signal to output
current equal the desired loadline. The values of Rcs1 and
Rcs2 are set based on the effect of temperature on both the
thermistor and inductor, and may need to be adjusted to
eliminate output voltage temperature drift with the final
product enclosure and cooling.
Figure 5. Ramp Feed Forward Circuit
Differential Current Feedback Amplifiers
Each phase of the rail has a low offset, differential
amplifier to sense the current of that phase in order to
balance current. The CSREF and CSPx pins are high
impedance inputs, but it is recommended that any external
filter resistor RCSN does not exceed 10 kW to avoid offset
due to leakage current.
Rcs1
Rcs2
It is also recommended that the voltage sense element be
no less than 0.5 mW for best current balance.
Ccs2
Ccs1
SWN1
SWNX
The external filter RCSN and CCSN time constant should
match the inductor L/DCR time constant, but fine tuning of
this time constant is generally not required. Phase current
signals are summed with the COMP or ramp signals at their
respective PWM comparator inputs in order to balance
phase currents via a current mode control approach.
Rph1
Rphx
CSSUM
CSREF
cscomp
CSN1
CSNX
Rref1
Rrefx
Rilim
To remote sense
Cref
amplifier
buffer
LPHASE
CSN @ DCR
ilim
RCSN
DCR
RCSN
+
C
LPHASE
Current Limit Current
Comparator Mirror
SWx
Ciout
Riout
VOUT
CCSN
CSPx
Figure 7. Total Current Sense Amplifier
Figure 6. Per Phase Current Sense Network
The pole frequency of the CSCOMP filter should be set
equal to the zero of the output inductor. This causes the total
current signal to contain only the component of inductor
voltage caused by the DCR voltage, and therefore to be
proportional to inductor current. Connecting Ccs2 in
parallel with Ccs1 allows fine tuning of the pole frequency
using commonly available capacitor values. It is best to
perform fine tuning during transient testing.
Total Current Sense Amplifier
The multiphase rail uses a patented approach to sum the
phase currents into a single, temperature compensated, total
current signal. This signal is then used to generate the output
voltage droop, total current limit, and the output current
monitoring functions. The Rref(n) resistors average the
voltages at the output terminals of the inductors to create a
low impedance reference voltage at CSREF. The Rph
resistors sum currents from the switch nodes to the virtual
CSREF potential created at the CSSUM pin by the amplifier.
The total current signal is the difference between the
CSCOMP and CSREF voltages.
DCR25oC
2p @ LPHASE
FZ
+
1
Fp +
R
CS1@Rth
CS1)Rth
@ ǒC Ǔ
CS1 ) CCS2
2p @ ǒ
Ǔ
RCS2
)
R
The amplifier filters, and amplifies, the voltage across the
inductors in order to extract only the voltage across the
inductor series resistances (DCR). An NTC thermistor (Rth)
in the feedback network placed near the Phase 1 inductor
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier.
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13
NCP81565
The value of the CREF capacitor (in nF) on the CSREF pin
should be:
regulator output voltage. The VSP and VSN inputs should
be connected to the regulator’s output voltage sense points.
The remote sense amplifier takes the difference of the output
voltage with the DAC voltage and adds the droop voltage.
0.02 @ Rph
Cref +
Rref
VDIFFOUT
+
High Performance Voltage Error Amplifier
ǒV
Ǔ ) 1.3 V * V
ǒ
Ǔ ) V
ǒ
Ǔ
DROOP * VCSREF
VSP * VVSN
DAC
The Remote Sense Amplifier output feeds a Type III
compensation network formed by the Error Amplifier and
external tuning components. The non−inverting input of the
error amplifier is connected to the same reference voltage
used to bias the Remote Sense Amplifier output.
Programming the Current Limit
The current limit thresholds are programmed with a
resistor between the ILIM and CSCOMP pins. The
multiphase rails generates a replica of the CSREF pin
voltage at the ILIM pin, and compares ILIM pin current to
ICL and ICLM. The controller latches off if ILIM pin
C2
C3
R3
current exceeds ICL for t
, and latches off
OCPDLY
C1
R2
immediately if ILIM pin current exceeds ICLM. Set the
value of the current limit resistor RLIMIT according to the
desired current limit Iout LIMIT.
R1
DIFFOUT
FB
Vref
Figure 8. Error Amplifier
COMP
-
+
EA
R
CS1@Rth
RCS2)
R
CS1)Rth
@ DCR @ IOUT
Rph
LIM
Loadline Programming (VDROOP
)
RLIMIT
+
10 m
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases
proportional to load current. This characteristic can reduce
the output capacitance required to maintain output voltage
within limits during load transients faster than those to
which the regulation loop can respond.
Programming IOUT
The IOUT pin sources a current proportional to the ILIM
current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external
resistor to ground such that a load equal to ICCMAX
generates a 2.5 V signal on IOUT.
A load line is produced by adding a signal proportional to
output load current (V
) to the output voltage feedback
DROOP
signal – thereby satisfying the voltage regulator at an output
voltage reduced proportional to load current. The load line
is programmed by setting the gain of the Total Current Sense
Amplifier such that the total current signal is equal to the
desired output voltage droop.
2.5 V @ RLIM
RIOUT
+
R
CS1@Rth
RCS2)
R
CS1)Rth
Rph
10 @
@ DCR @ ICCMAX
R
CS1@Rth
Programming DAC Feed−Forward Filter
RCS2
)
The multiphase rail outputs a pulse of current from the
VSN pin upon each increment of the internal DAC
following a DVID UP command. A parallel RC network
inserted into the path from VSN to the output voltage return
sense point, VSS_SENSE, causes these current pulses to
temporarily decrease the voltage between VSP and VSN.
This causes the output voltage during DVID to be regulated
slightly higher, in order to compensate for the response of
the DROOP function to current flowing into the charging
R
CS1)Rth
VDROOP
+
@ DCR @ IOUT
Rph
For the main rail, loadline programming is dependent on its
programmed ICCMAX value.
Rcs
Loadline + DCR
Weighting
Rph
For ICC*2_MAIN_RAIL configuration enabled,
weighting = 187.50%.
For ICC*2_MAIN_RAIL configuration disabled,
weighting = 93.75%.
output capacitors. In the following equations, C
total output capacitance of the system.
is the
OUT
R
FF + Cout @ LL @ 453.6 @ 106
For the A rail, loadline weighting = 93.75%
LL @ Cout
Rail Remote Sense Amplifier
CFF +
RFF
A
high performance high input impedance true
differential amplifier is provided to accurately sense
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14
NCP81565
TSENSE
RCOMP 1
CFILTER
RNTC
RCOMP 2
Figure 10. TSENSE Network
PWM Comparators
Figure 9. DAC Feed Forward
TSENSE Network
The noninverting input of each comparator (one for each
phase) is connected to the summation of the error amplifier
output (COMP) and each phase current (IL×DCR×Phase
Balance Gain Factor). The inverting input is connected to
the triangle ramp voltage of that phase. The output of the
comparator generates the PWM output. During steady state
PS0 operation, the main rail PWM pulses are centered on the
valley of the triangle ramp waveforms and both edges of the
PWM signals are modulated. During a transient event, the
duty cycle can increase rapidly as the error amp signal
increases with respect to the ramps, to provide a highly
linear and proportional response to the step load.
A temperature sense input is provided for each rail. A
precision current is sourced from the output of the
TSENSE/A pins to generate a voltage on the temperature
sense networks. The voltages on the temperature sense
inputs are sampled by the internal A/D converter. A 100k
NTC similar to the Murata NCP15WF104E03RC should be
used. Rcomp1 in the following Figure is optional, and can
be used to slightly change the hysteresis. See the
specification table for the thermal sensing voltage
thresholds and source current.
Table 13. PHASE CONFIGURATION
Phase
Configuration
Programming Pin in CSPx
Unused Pin
6 + 2
All CSP pins are connected normally
No unused Pin
5 + 2
CSP1 to CSP5, CSP1A and CSP2A pins connected normally.
CSP6 connected to VCC through a 2k resistor.
Float PWM6.
4 + 2
3 + 2
CSP1 to CSP4, CSP1A and CSP2A pins connected normally.
CSP5 connected to VCC through a 2k resistor.
Float PWM6 and CSP6.
Use PWM5 for programming ROSCA only.
CSP1 to CSP3, CSP1A and CSP2A pins connected normally.
CSP4 connected to VCC through a 2k resistor.
Float PWM6, CSP5 and CSP6.
Use PWM5 for programming ROSCA only.
Use PWM4 for programming ROSC only.
2 + 2
2+1
CSP1, CSP2, CSP1A and CSP2A pins connected normally.
CSP3 connected to VCC through a 2k resistor.
Float PWM6, CSP4, CSP5 and CSP6.
Use PWM5 for programming ROSCA only.
Use PWM4 for programming ROSC only.
Use PWM3 for programming ICCMAX only.
CSP1, CSP2, CSP1A pins connected normally.
CSP3 and CSP2A connected to VCC through a 2k resistor.
Float PWM6, PWM2A, CSP4, CSP5 and
CSP6.
Use PWM5 for programming ROSCA only.
Use PWM4 for programming ROSC only.
Use PWM3 for programming ICCMAX only.
2+0
CSP1, CSP2, pins connected normally.
CSP3 and CSP1A connected to VCC through a 2k resistor.
Float PWM6, PWM1A, PWM2A, CSP4, CSP5,
CSP6 and CSP2A.
Use PWM5 for programming ROSCA only.
Use PWM4 for programming ROSC only.
Use PWM3 for programming ICCMAX only.
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15
NCP81565
FAULT PROTECTION
Over Current Protection (OCP)
below the DAC−DROOP voltage, the UVM comparator
A programmable total phase current limit is provided that
is decreased when not operating in PS0 mode. This limit is
programmed with a resistor between the CSCOMP and
ILIM pins. The current from the ILIM pin to this resistor is
compared to the ILIM Threshold Currents.
If the fault is not removed, the controller shuts down when
the timer expires. If the current into the pin exceeds ICLM,
the controller shuts down immediately. To recover from an
OCP fault, the EN pin or VCC voltage must be cycled low.
will trip – sending the VR_RDY signal low.
Output Over Voltage Protection
The multiphase phase output voltage is monitored for
OVP at the VSP pin. During normal operation, if an output
voltage exceeds the DAC voltage by VOVP, the VR_RDY
flag goes low, and the DAC voltage of the overvoltage rail
will be slowly ramped down to 0 V to avoid producing a
negative output voltage. At the same time, the PWM outputs
of the overvoltage rail are sent low. The PWM output will
pulse to mid−level during the DAC ramp down period if the
output decreases below the DAC + OVP threshold as DAC
decreases. When the DAC gets to zero, the PWMs will be
held low, and the VR will stay in this mode until the VCC
voltage or EN is toggled.
Input Under−voltage Lockouts (UVLO)
The VR monitors the 5 V VCC supply as well as the
VRMP pin voltage. Hysteresis is incorporated within these
monitors.
Output Under Voltage Monitor
The multiphase rail output voltage is monitored for under
voltage at the output of the differential amplifier. If the
multiphase−phase rail output falls more than VUVM2
Absolute OVP
During start up, the OVP threshold is set to the absolute
over voltage threshold. This allows the controller to start up
without false triggering OVP.
Figure 11. OVP Threshold Behavior
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16
NCP81565
Figure 12. OVP Behavior at Start−up
Figure 13. OVP During Normal Operation Mode
Serial VID Interface
For Intel proprietary interface communication details
please contact Intel, inc.
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17
NCP81565
PACKAGE DIMENSIONS
QFN52 6x6, 0.4P
CASE 485BE
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
L
D
A B
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
L1
LOCATION
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.10
C
EXPOSED Cu
MOLD CMPD
0.15
0.25
D
D2
E
6.00 BSC
4.60
4.80
TOP VIEW
0.10
C
6.00 BSC
E2
e
K
L
L1
L2
4.60
0.40 BSC
0.30 REF
0.25
0.00
0.15 REF
4.80
A
(A3)
DETAIL B
DETAIL B
0.10
C
C
ALTERNATE
0.45
0.15
CONSTRUCTION
0.08
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
D2
C
K
L2
DETAIL C
L2
14
DETAIL A
DETAIL C
27
8 PLACES
SOLDERING FOOTPRINT*
E2
6.40
4.80
52X
0.63
52X
L
1
52
40
52X b
e
0.07
C
C
A B
BOTTOM VIEW
0.05
NOTE 3
4.80
6.40
0.11
0.49
DETAIL D
PKG
8 PLACES
OUTLINE
DETAIL D
52X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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