NCS20164DR2G [ONSEMI]
8 MHz, Rail-to-Rail CMOS Operational Amplifier.;
| 型号： | NCS20164DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8 MHz, Rail-to-Rail CMOS Operational Amplifier. |
| 文件： | 总22页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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8 MHz, Rail-To-Rail, CMOS
Operational Amplifier
5
1
SC70−5
TSOP−5/SOT23−5
CASE 419A
CASE 483
NCS20161, NCS20162,
NCS20164, NCV20161,
NCV20162, NCV20164
8
1
The NCS20161, NCS20162, and NCS20164 are a family of single,
dual and quad operational amplifiers (op amps) that provide 8 MHz
gain−bandwidth product while consuming 500 ꢀ A of quiescent
current per channel. The NCS2016x has an input offset voltage of
0.3 mV and operates from 1.8 V to 5.5 V supply over a wide
temperature range (−40C to 125C). The rail−to−rail input and output
operation allows the use of the entire supply voltage range. Thus, this
series of op amps offers superior performance over many industry
standard parts. These devices are AEC−Q100 qualified when denoted
by the NCV prefix.
Micro8]/MSOP8
SOIC−8
CASE 751
CASE 846A
14
14
1
1
SOIC−14
CASE 751A
TSSOP−14
CASE 948G
With low current consumption and low supply voltage operation in
industry standard packages, the NCS20161 series is ideal for sensor
signal conditioning and low voltage current sensing applications in
automotive, consumer and industrial markets.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
Features
Gain−Bandwidth Product: 8 MHz
Low Supply Current per Channel: 500 ꢀ A typ (V = 5.5 V)
Low Input Offset Voltage: 0.3 mV
Wide Supply Range: 1.8 V to 5.5 V
Wide Temperature Range: −40C to +125C
Rail−to−Rail Input and Output
ORDERING INFORMATION
S
See detailed ordering and shipping information on page 3 of
this data sheet.
Unity Gain Stable
Available in Single, Dual and Quad Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
Automotive
Battery Powered / Portable
Sensor Signal Conditioning
Low Voltage Current Sensing
Filter Circuits
Unity Gain Buffer
This document contains information on some products that are still under development.
onsemi reserves the right to change or discontinue these products without notice.
Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
May, 2023 − Rev. 1
NCS20161/D
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
MARKING DIAGRAMS
Single Channel Configuration
NCS20161, NCV20161
5
XXMG
XXXAYWG
G
G
1
SC70−5
TSOP−5/SOT23−5
CASE 419A
CASE 483
Dual Channel Configuration
NCS20162, NCV20162
8
8
20162
ALYW
G
XXXX
AYWG
G
1
1
Micro8]/MSOP8
SOIC−8
CASE 751
CASE 846A
Quad Channel Configuration
NCS20164, NCV20164
14
14
XXXX
XXXX
ALYWG
G
20164G
AWLYWW
1
1
TSSOP−14
CASE 948G
SOIC−14
CASE 751A
XXXXX = Specific Device Code
= Assembly Location
WL, L = Wafer Lot
= Year
A
Y
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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2
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
Single Channel Configuration
NCS20161, NCV20161
5
4
1
2
3
5
4
1
2
3
IN+
VDD
VDD
OUT
OUT
VSS
+
VSS
−
IN−
IN+
IN−
SC70−5
SQ3 Pinout
SOT23−5 (TSOP−5)
SN2 Pinout
Quadruple Channel Configuration
NCS20164, NCV20164
Dual Channel Configuration
OUT 1
IN− 1
IN+ 1
VDD
1
2
3
4
5
6
7
14
OUT 4
NCS20162, NCV20162
13 IN− 4
−
−
1
2
3
4
8
7
6
5
OUT 1
VDD
+
+
12 IN+ 4
−
OUT 2
IN− 2
IN+ 2
IN− 1
IN+ 1
VSS
VSS
11
+
−
10 IN+ 3
IN+ 2
IN− 2
+
+
+
−
−
9
8
IN− 3
Micro8/MSOP8, SOIC−8
OUT 2
OUT 3
TSSOP−14, SOIC−14
Figure 1. Pin Connections
ORDERING INFORMATION
†
Device*
Configuration
Automotive
Marking
TBD
Package
SC70
Shipping
NCS20161SQ3T2G**
NCS20161SN2T1G**
NCV20161SQ3T2G**
NCV20161SN2T1G**
NCS20162DMR2G**
NCS20162DR2G**
NCV20162DMR2G**
NCV20162DR2G**
NCS20164DR2G
Single
No
Yes
No
3000 / Tape and Reel
3000 / Tape and Reel
3000 / Tape and Reel
3000 / Tape and Reel
4000 / Tape and Reel
2500 / Tape and Reel
4000 / Tape and Reel
2500 / Tape and Reel
2500 / Tape and Reel
2500 / Tape and Reel
2500 / Tape and Reel
2500 / Tape and Reel
TBD
SOT23−5/TSOP−5
SC70
TBD
TBD
SOT23−5/TSOP−5
Micro8/MSOP8
SOIC−8
Dual
TBD
20162
TBD
Yes
No
Micro8/MSOP8
SOIC−8
20162
20164G
TBD
Quad
SOIC−14
NCS20164DTBR2G**
NCV20164DR2G**
NCV20164DTBR2G**
TSSOP−14
SOIC−14
Yes
20164G
TBD
TSSOP−14
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
**In Development. Contact local sales office for more information.
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3
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
ABSOLUTE MAXIMUM RATINGS (Note 1)
Rating
Symbol
Limit
Unit
V
Supply Voltage (V – V
)
V
S
−0.3 to 6
DD
SS
Common Mode Input Voltage
Differential Input Voltage
Maximum Input Current
V
V
SS
−0.3 to V +0.3
V
I
DD
V
ID
V
DD
– V +0.2
V
SS
I
I
10
100
200
mA
mA
mW
C
_C
_C
V
Maximum Output Current (Note 2)
I
O
Continuous Total Power Dissipation (Note 2)
Maximum Junction Temperature
P
D
T
J
150
Storage Temperature Range
T
−65 to 150
STG
Mounting Temperature (Infrared or Convection – 20 sec)
T
260
mount
ESD Capability (Note 3)
Human Body Model
Charge Device Model
HBM
CDM
2500
1500
Latch−Up Current (Note 4)
I
LU
100
mA
Moisture Sensitivity Level (Note 5)
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS for Safe Operating Area.
2. Continuous short circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction
temperature of 150C. Output currents in excess of the maximum output current rating over the long term may adversely affect reliability.
Shorting output to either VDD or VSS will adversely affect reliability.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard Js−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004)
5. Moisture Sensitivity Level tested per IPC/JEDEC standard: J−STD−020A
OPERATING RANGES
Parameter
Operating Supply Voltage (V − V
Symbol
Min
1.8
−
Max
Unit
V
)
V
S
5.5
DD
SS
Differential Input Voltage
V
ID
V
S
V
Common Mode Input Voltage Range
Ambient Temperature
V
V
– 0.1
V + 0.1
DD
V
CM
SS
T
−40
125
C
A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
ELECTRICAL CHARACTERISTICS AT VS = 1.8 V to 5.5 V
T = 25C; R 10 kꢁ connected to mid−supply; V
= V
= mid−supply unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, T = −40C to 125C. (Note 6)
A
Parameter
INPUT CHARACTERISTICS
Input Offset Voltage
Symbol
Conditions
Min
Typ
Max
Unit
V
OS
V
V
V
= 5 V
= 5 V
= 5 V
−
−
0.3
−
2.1
2.6
−
mV
mV
ꢀ V/C
pA
S
S
S
Offset Voltage Drift
dV /dT
OS
−
1.5
5
Input Bias Current (Note 6)
Input Offset Current (Note 6)
Channel Separation
I
IB
−
−
I
−
5
−
pA
OS
DC
−
100
4
−
dB
Input Capacitance
C
−
−
pF
IN
Common Mode Rejection Ratio
CMRR
V
S
V
S
V
S
V
S
= 5.5 V, V
= 5.5 V, V
= 1.8 V, V
= 1.8 V, V
= V − 0.1 V to V − 1.4 V
80
57
−
103
79
−
dB
CM
CM
CM
CM
SS
DD
= –0.1 V to 5.6 V
−
= V − 0.1 V to V − 1.4 V
91
−
SS
DD
= –0.1 V to 1.9 V
−
71
−
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
A
V
= 1.8 V, V + 0.04 V < V < V – 0.04 V,
−
101
−
100
108
97
−
−
−
−
−
dB
VOL
S
SS
O
DD
R = 10 kꢁ
L
V
S
= 5.5 V, V + 0.05 V < V < V – 0.05 V,
SS O DD
R = 10 kꢁ
L
V
S
= 1.8 V, V + 0.06 V < V < V – 0.06 V,
SS O DD
R = 2 kꢁ
L
V
S
= 5.5 V, V + 0.15 V < V < V – 0.15 V,
−
113
SS
O
DD
R = 2 kꢁ
L
Short Circuit Current
I
Output sourcing current V = 5 V
−
−
−
40
50
3
mA
mV
SC
S
Output sinking current, V = 5 V
S
Output Voltage Swing from V
V
−
OH
20
60
V
= 5.5 V, R = 10 kꢁ
L
DD
DD
S
S
V
V
= 5.5 V, R = 2 kꢁ
−
−
L
Output Voltage Swing from V
V
−
SS
−
−
3
20
60
mV
V
V
= 5.5 V, R = 10 kꢁ
SS
OL
S
L
V
= 5.5 V, R = 2 kꢁ
−
S
L
AC CHARACTERISTICS
Unity Gain Bandwidth
Slew Rate at Unity Gain
Phase Margin
UGBW
SR
V
V
V
= 5 V, G = +1
= 5 V, G = +1
= 5 V, G = +1
−
−
−
−
−
−
−
−
8
3.5
52
11
0.5
1
−
−
−
−
−
−
−
−
MHz
V/ꢀ s
_
S
S
S
ꢂ
m
Gain Margin
A
m
dB
Settling Time to 0.1%
t
t
V
S
V
S
V
S
V
S
= 5 V, V = 2 V step, G = +1, C = 100 pF
IN L
s
S
Settling Time to 0.01%
Overload Recovery Time
Open Loop Output Impedance
NOISE CHARACTERISTICS
Total Harmonic Distortion plus Noise
= 5 V, V = 2 V step, G = +1, C = 100 pF
s
S
IN
L
t
= 5 V, V x gain > V
1
s
OR
IN
S
Z
OL
= 5 V, f = 10 MHz
240
ꢁ
THD+n
V
S
= 5.5 V, V
= 2.5 V, V = 1 V
, G = +1,
−
0.0008
−
%
CM
O
RMS
f = 1 kHz
Input Referred Voltage Noise
e
n
V
S
V
S
= 5 V, f = 1 kHz
= 5 V, f = 10 kHz
−
−
20
10
−
−
nV/Hz
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization.
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5
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
ELECTRICAL CHARACTERISTICS AT VS = 1.8 V to 5.5 V (continued)
T = 25C; R 10 kꢁ connected to mid−supply; V
= V
= mid−supply unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, T = −40C to 125C. (Note 6)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NOISE CHARACTERISTICS
Input Referred Current Noise
Input Voltage Noise, Peak−to−Peak
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Power Supply Quiescent Current
i
f = 1 kHz
−
−
20
5
−
−
fA/Hz
VPP
n
E
V
S
= 5 V, f = 0.1 Hz to 10 Hz
n
PSRR
V
S
= 1.8 V – 5.5 V, V
= V
−
−
8
80
V/V
A
CM
SS
I
Q
Per channel, no load
500
800
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization.
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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L L
25
20
15
10
20
18
16
14
12
V
= 5 V
S
V
= 5 V
S
105 Units
105 Units
10
8
6
4
2
0
5
0
−1.4
−1.0 −0.6
−0.2
0.2
0.6
1.0
1.4
−3
−2
−1
0
1
2
3
4
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET VOLTAGE DRIFT (ꢀ V/C)
Figure 2. Input Offset Voltage Distribution
Figure 3. Input Offset Voltage Drift Distribution
2000
1500
1000
500
2000
1500
1000
500
0
0
−500
−1000
−500
−1000
V
S
= 5.5 V
V = 1.8 V
S
−1500
−2000
−1500
−2000
5 typical units
5 typical units
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
COMMON MODE VOLTAGE (V)
−0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
−0.2 0
COMMON MODE VOLTAGE (V)
Figure 4. Input Offset Voltage vs. Common
Mode Voltage at 5.5 V Supply
Figure 5. Input Offset Voltage vs. Common
Mode Voltage at 1.8 V Supply
2000
2000
1500
1000
500
1500
1000
500
V
S
= 1.8 V
V
CM
= mid−supply
0
0
−500
−1000
−500
−1000
V
= 5.5 V
S
V
= mid−supply
CM
−1500
−2000
−1500
−2000
5 typical units
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 6. Input Offset Voltage vs. Temperature
at 5.5 V Supply
Figure 7. Input Offset Voltage vs. Temperature
at 1.8 V Supply
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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L
L
120
100
80
160
140
120
100
80
V
S
V
S
= 5.5 V
= 1.8 V
Phase
60
Gain
40
60
20
40
0
20
0
V
S
= 5 V
100
−20
10
10
0
1K
10K
100K
1M
10M
−50 −25
0
25
50
75
100
125 150
FREQUENCY (Hz)
TEMPERATURE (C)
Figure 8. Open Loop Gain vs. Frequency
Figure 9. Open Loop Gain vs. Temperature
30
20
10
600
500
400
300
200
100
I
I
I
IB+
IB−
OS
V
S
= 5.5 V
0
−10
−20
−30
A = 1
V
A = −1
V
A = 10
V
0
−40
−50
V
S
= 5.5 V
−100
100
1K
10K
100K
1M
10M
−50 −25
0
25
50
75
100
125 150
FREQUENCY (Hz)
TEMPERATURE (C)
Figure 10. Closed Loop Gain vs. Frequency
Figure 11. Input Current vs. Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.7
0.6
0.5
0.4
0.3
0.2
T = −40C
T = 25C
T = 85C
T = 125C
T = −40C
T = 25C
T = 85C
T = 125C
A
A
A
A
A
A
A
A
0.1
0
0.1
0
V
S
= 5.5 V
50
V
S
= 5.5 V
10
20
30
40
0
10
20
30
40
60
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 12. Output Voltage Swing High
Figure 13. Output Voltage Swing Low
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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L
L
120
100
80
120
100
80
60
40
20
0
V = −10 dBm
IN
V
IN
= 0 dBm
60
40
V
S
V
S
V
S
V
S
= 1.8 V, PSRR+
= 1.8 V, PSRR−
= 5.5 V, PSRR+
= 5.5 V, PSRR−
20
V
V
= 1.8 V
= 5.5 V
S
S
0
−20
−40
−20
10
100
1K
10K
100K
1M
10M
10
1K
100K
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. CMRR vs Frequency
Figure 15. PSRR vs. Frequency
0
6
5
4
−1
−2
−3
−4
−5
3
2
V
= 5.5 V
S
1
0
−6
−7
V
= 1.8 V to 5.5 V
S
V
= −0.1 V to 4.1 V
CM
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 16. CMRR vs Temperature
Figure 17. PSRR vs. Temperature
4
180
V
S
= 5 V
160
140
120
100
80
3
2
1
0
−1
−2
60
40
V
S
V
S
= 5.5 V
= 1.8 V
−3
−4
20
0
10
100
1K
10K
100K
1M
TIME (1 s/div)
FREQUENCY (Hz)
Figure 18. 0.1 Hz to 10 Hz Noise
Figure 19. Voltage Noise Density vs.
Frequency
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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L L
−90
−95
0
−10
−20
−30
−40
−50
−60
−70
V
= 5.5 V
S
V = 5.5 V
S
R = 2.2 kꢁ to mid−supply
L
R = 2.2 kꢁ to mid−supply
L
V
IN
= 0.5 V
RMS
V = 0.5 V
IN RMS
A = 1
V
A = −1
V
−100
−105
−110
−80
−90
−115
−120
−100
10
100
1K
10K
0.001
0.01
0.1
1
FREQUENCY (Hz)
AMPLITUDE (V
)
RMS
Figure 20. THD+n vs. Frequency
Figure 21. THD+n vs. Output Amplitude
540
530
520
510
510
500
490
V
S
= 5.5 V
480
470
500
490
460
450
480
470
−50 −25
0
25
50
75
100
125 150
1.5 2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
Figure 22. Quiescent Current Per Channel vs.
Temperature
Figure 23. Quiescent Current Per Channel vs.
Supply Voltage
0.08
0.06
0.04
0.02
0
3
2
1
Input
Output
Input
Output
−0.02
−0.04
−0.06
−0.08
0
−1
−2
−3
V = 5.5 V
S
V
S
= 5.5 V
−0.10
−0.12
A = 1
V
A = 1
V
TIME (0.2 ꢀ s/div)
TIME (1 ꢀ s/div)
Figure 24. Small Signal Step Response
Figure 25. Large Signal Step Response
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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L L
4
3
4
3
0.4
Input
Output
V
DD
0.3
0.2
0.1
0
2
2
1
1
Output
0
0
V
DD
V
SS
= 2.75 V
= −2.75 V
−1
−2
−1
−2
−0.1
−0.2
V
SS
−3
−4
−3
−4
−0.3
−0.4
TIME (100 ꢀ s/div)
TIME (1 ꢀ s/div)
Figure 26. Power Up
Figure 27. No Phase Reversal
60
40
20
0
160
140
120
100
80
Sourcing
Sinking
V
S
= 5 V
−20
−40
60
40
−60
−80
V
= 5.5 V
20
0
S
−50
−25
0
25
50
75
100
125
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
TEMPERATURE (C)
Figure 28. Short Circuit Current vs.
Temperature
Figure 29. Open Loop Gain vs. Output Voltage
1.5
1.0
1
0
1.5
1.0
0.5
0
5
4
Input
Output
Input
3
0.5
0
−1
−2
−3
Output
2
V
= 5.5 V
A = −1
C = 100 pF
S
V
= 5.5 V
A = −1
C = 100 pF
S
V
V
−0.5
1
−0.5
L
L
−1.0
−1.5
−4
−5
−1.0
−1.5
0
−1
TIME (500 ns/div)
TIME (500 ns/div)
Figure 30. Output Low−to−High Settling Time
Figure 31. Output High−to−Low Settling Time
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11
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L
L
100
90
80
70
60
50
40
30
300
250
200
150
100
20
10
0
50
0
V
S
= 5 V
10M
100M
1G
10G
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. EMIRR vs. Frequency
Figure 33. Open Loop Output Impedance vs.
Frequency
0
−20
−40
−60
−80
60
50
40
30
20
V
S
= 5 V
V = 5 V
S
−100
−120
10
0
10
100
1K
10K
100K
1M
10M
0
50
100
150
200
250
FREQUENCY (Hz)
CAPACITIVE LOAD (pF)
Figure 34. Channel Separation vs. Frequency
Figure 35. Phase Margin vs. Capacitive Load
www.onsemi.com
12
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS
(AT T = 25C, V
= MID−SUPPLY, C = 20 PF, R = 10 Kꢁ TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
A
CM
L
L
50
45
50
45
V
= 5.5 V
V = 5.5 V
S
A = −1
V
S
A = 1
V
40
35
30
25
20
15
10
40
35
30
25
20
15
10
5
Rising Edge
Falling Edge
Rising Edge
Falling Edge
5
0
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 36. Overshoot vs. Capacitive Load for
AV = 1
Figure 37. Overshoot vs. Capacitive Load for
AV = −1
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5.5 V
V = 5.5 V
S
A = −10
V
S
A = −10
V
0.5
0
−0.5
−1.0
−1.5
−2.0
−0.5
Input
Output
Input
Output
−2.5
−3.0
−1.0
−1.5
TIME (1 ꢀ s/div)
TIME (1 ꢀ s/div)
Figure 38. Negative Overvoltage Recovery
Figure 39. Positive Overvoltage Recovery
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13
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
APPLICATION INFORMATION
The NCS20161 family of operational amplifiers is
manufactured using onsemi’s CMOS process. Products in
this class are general purpose, unity−gain stable amplifiers
and include single, dual and quad configurations.
events (within the limits specified) trigger the protection
structure so the operational amplifier is not damaged.
In order to safe guard against excessive voltages across the
op amp’s inputs, external clamp diodes can be used as shown
in Figure 40. The four low−drop fast diodes (Schottky
preferred) are used in parallel with the internal structure to
divert the excessive energy to the supply rails where it can
be easily dissipated or absorbed by the supply capacitors.
The application designer should also take into account that
these external diodes add leakage currents and parasitic
capacitance that must be considered when evaluating the
end−to−end performance of the amplifier stage.
Rail−to−Rail Input with No Phase Reversal
The NCS2016x operational amplifiers are designed to
prevent phase reversal or any similar issues when the input
pins potential exceed the supply voltages by up to 100 mV.
The input stage of the NCS20161 family consists of two
differential CMOS input stages connected in parallel: the
first is constructed using paired PMOS devices and it
operates at low common mode input voltages (V ); the
CM
second stage is build using paired NMOS devices to operate
Limiting Input Currents
at high V . The transition between the two input stages
occurs at a common mode input voltage of approximately
In order to prevent damage/ improper operation of these
amplifiers, the application circuit must limit the current
flowing through the input pins. A possible solution is
presented in Figure 40 by means of the two added series
resistors. The minimum value for the input resistors should
be calculated using Ohm’s Law so they limit the input pin
current to less than the absolute maximum values specified.
The application designer should take into account that these
resistors also add parasitic inductance that must be
considered when evaluating performance.
CM
V
DD
−1.3V.
Limiting Input Voltages
In order to prevent damage and/or improper operation of
these amplifiers, the application circuit must never expose
the input pins to voltages or currents higher than the
Absolute Maximum Ratings.
The internal ESD structure includes special diodes to
protect the input stages while maintaining a low input bias
Combining the current limiting resistors with the voltage
limiting diodes creates a solid input protection structure, that
can be used to insure reliable operation of the amplifier even
in the hardest conditions.
current (I ). The input protection circuitry clamp the inputs
IB
when the signals applied exceed more than one diode drop
below VSS or one diode drop above VDD. Very fast ESD
V
DD
V
DD
V
DD
SS
IN+
+
IN+
IN+
+
+
−
IN−
IN−
−
−
IN−
V
V
SS
V
SS
Figure 40. Typical Protection of the Operational Amplifier Inputs
Rail−to−Rail Output
degraded phase margin
The maximum output voltage swing is dependent of the
particular output load. According to the specification, the
output can reach within 20 mV of either supply rail when
lowered bandwidth
gain peaking of the frequency response
overshoot and ringing of the step response
load resistance is 10 kꢁ. The V and V graphs shows the
OL
OH
While the NCS2016x series op amps are capable of driving
capacitive loads up to 100 pF, adding a small resistor in
load drive capabilities of the part under different conditions.
Output current is internally limited to the typical values
listed in the Electrical Characteristics table.
series to the output (R
in Figure 41) will increase the
ISO
phase margin. This leads to higher stability by making the
equivalent load more resistive at high frequencies.
Capacitive Loads
Driving capacitive loads can create stability problems for
voltage feedback op amps, as it is a known possible cause for:
www.onsemi.com
14
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
V
DD
The unity gain buffer is recommended here (Figure 42).
The ADC’s internal sampling capacitor requires a buffer
front−end to recharge it faster than the sampling time, and
IN+
+
R
this problem is even worse if more channels are sampled by
the same ADC using an internal multiplexer. In order to
achieve a settling time shorter than the multiplexed
sampling rate, an RC stage is recommended between the
ISO
IN−
−
C
L
buffer and the ADC input. The R
resistor’s value should
ISO
V
SS
be low enough to charge the capacitor quickly, but at the
same time large enough to isolate the capacitive load from
the amplifier output to preserve phase margin. When
transients are generated by the sensor’s output, first the two
amplifier inputs see a high differential voltage between
them, then the output settles and brings the inverting input
back to the correct voltage.
Let us take an example of a 0.1 V to 4 V sensor signal. To
successfully accommodate it, the differential input range of
the NCS2016x is close to the supply range and the output
will match the input. The differential input voltage is limited
only by the ESD protection structure and not by
back−to−back diodes between inputs.
Figure 41. Driving Capacitive Loads
Simulating the application with onsemi’s Spice model is
a good starting point for selecting the isolation resistor’s
value. Bench testing the frequency and step response can be
used to fine−tune the value according to the desired
characteristic.
Unity Gain Bandwidth
Interfacing a high impedance sensor’s output to
a relatively low−impedance ADC input usually requires an
intermediate stage to avoid unwanted interference of the two
devices, and this stage needs to have a high input impedance,
a low output impedance, and high output current.
V
DD
ADC
+
sensor
R
ISO
−
C
C
L
sampling
V
SS
Figure 42. Unity Gain Buffer Stage for Sampling with ADC
Power Supply Bypassing
crosstalk, increased current consumption, or add noise to the
supply rails.
For AC, the power supply pins (VDD and VSS for split
supply, VDD for single supply) should be bypassed locally
with a quality capacitor in the range of 100 nF as close as
possible to the amplifier supply pins. Ceramic capacitors are
recommended for their low ESR and good high frequency
response.
V
DD
V
DD
+
+
For DC, a bulk capacitor in the range of 1 F placed within
inches distance from the op amp can provide the additional
current needed to drive higher loads.
−
−
Unused Operational Amplifiers
V
SS
Occasionally not all the op amp channels offered in the
quad packages are needed for a specific application. They
can be connected as “buffering ground” as shown in
Figure 43, a solution that does not need any extra parts.
Connecting them differently (inputs split to rails, left
floating, etc.) can sometimes cause unwanted oscillation,
Figure 43. Unused Operational Amplifiers
www.onsemi.com
15
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PCB Surface Leakage
PCB Routing Recommendations
If it is critical to obtain the lowest input bias current, the
PCB’s surface leakage should be considered. Dry
environment surface current increases further when the
board is exposed to humidity, dust or chemical
contamination. For harsh environment conditions,
protecting the entire board surface (with all the exposed
metal pins and soldered areas) is advised. Conformal coating
or potting the board in resin proves effective in most cases.
An alternate solution for reduced leakage is the use of
guard rings around sensitive pins and pads. A proper guard
ring should have low impedance and be biased to the same
voltage as the sensitive pin so that no current flows in
between them.
In addition to amplifying the useful signal, op amps can
also pick the high frequency noise together with the signal
and amplify it accordingly, if the design allows it. In order
to reach the values specified in the Electrical Characteristics
tables and to avoid high frequency interference issues, it is
recommended that the PCB layout follows the basic
guidelines listed below:
A dedicated layer for the ground plane should be
used whenever possible and all supply decoupling
capacitors should connect to it by vias
Copper traces should be as short as possible
High current paths should not be shared by small
signal or low current traces
For an inverting amplifier, the non−inverting input is
usually connected to supply’s ground (or virtual ground at
half the rail voltage in single supply applications) so it can
represent a good ring solution. When routing the PCB traces,
create a closed perimeter around the inverting input pad (which
carries the signal) and connect it to the non−inverting input.
For a non−inverting amplifier, use a similarly shaped
(rectangle or circle) copper trace around the non−inverting
input pad (which carries the signal) and connect it to the
inverting input pin, which presents a much lower impedance
thanks to the feedback network.
If present, switching power supply blocks should be
kept away from the analog sensitive areas to avoid
potential conducted and radiated noise issues
When different circuit taxonomies share the same
board, it is recommended to keep separated the
power areas, the digital areas and the small signal
analog areas. Small−signal components in the signal
path should be placed as close as possible to the
amplifier input pins
Metal shielding the sensitive areas and the
“offender” blocks may be required in some cases
www.onsemi.com
16
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE M
www.onsemi.com
17
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X−
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
18
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
19
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
20
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
www.onsemi.com
21
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
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Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
onsemi Website: www.onsemi.com
www.onsemi.com
相关型号：
NCS20166SN2T1G
Precision Operational Amplifier, Low Offset, 10 MHz, Rail-to-Rail Input / Output
ONSEMI
NCS2021SN2T1
OP-AMP, 5000uV OFFSET-MAX, 0.06MHz BAND WIDTH, PDSO5, PLASTIC, SC-59, SOT-23, TSOP-5
ONSEMI
NCS2021SN3T1
OP-AMP, 5000uV OFFSET-MAX, 0.06MHz BAND WIDTH, PDSO5, PLASTIC, SC-59, SOT-23, TSOP-5
ONSEMI
NCS2021SQ2T1
OP-AMP, 5000uV OFFSET-MAX, 0.06MHz BAND WIDTH, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
ONSEMI
NCS2021SQ3T1
OP-AMP, 5000uV OFFSET-MAX, 0.06MHz BAND WIDTH, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
ONSEMI
NCS20231SN2T1G
Operational Amplifier, 36 V, 3 MHz, 0.95 mV Input Offset Voltage, Rail-to-Rail
ONSEMI
NCS20231SQ3T2G
Operational Amplifier, 36 V, 3 MHz, 0.95 mV Input Offset Voltage, Rail-to-Rail
ONSEMI
NCS20231XV53T2G
Operational Amplifier, 36 V, 3 MHz, 0.95 mV Input Offset Voltage, Rail-to-Rail
ONSEMI
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