NCV4276BDT50RKG [ONSEMI]
400 mA LowâDrop Voltage Regulator; 400毫安洛瓦????降稳压器
| 型号： | NCV4276BDT50RKG |
| 厂家： | 
ONSEMI |
| 描述： | 400 mA LowâDrop Voltage Regulator |
| 文件： | 总18页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV4276B
400 mA Low‐Drop Voltage
Regulator
The NCV4276B is a 400 mA output current integrated low dropout
regulator family designed for use in harsh automotive environments.
It includes wide operating temperature and input voltage ranges. The
device is offered with 3.3 V, 5.0 V, and adjustable voltage versions
available in 2% output voltage accuracy. It has a high peak input
voltage tolerance and reverse input voltage protection. It also
provides overcurrent protection, overtemperature protection and
inhibit for control of the state of the output voltage. The NCV4276B
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2
2
DPAK
D PAK
family is available in DPAK and D PAK surface mount packages.
CASE 175AA
CASE 936A
The output is stable over a wide output capacitance and ESR range.
The NCV4276B has improved startup behavior during input voltage
transients.
MARKING DIAGRAMS
Features
3.3 V, 5.0 V, and Adjustable Voltage Version (from 2.5 V to 20 V)
2% Output Voltage
400 mA Output Current
76BXXG
ALYWW
500 mV (max) Dropout Voltage (5.0 V Output)
Inhibit Input
1
Very Low Current Consumption
Fault Protection
DPAK
5-PIN
+45 V Peak Transient Voltage
−42 V Reverse Voltage
Short Circuit
Thermal Overload
NC
V4276B−XX
AWLYWWG
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
These are Pb-Free Devices
1
2
D PAK
5-PIN
*Tab is connected to Pin 3 on all packages.
= Assembly Location
A
WL, L = Wafer Lot
Y
= Year
WW
G
XX
= Work Week
= Pb-Free Device
= 33 (3.3 V)
= 50 (5.0 V)
= AJ (Adj. Voltage)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 16 of this data sheet.
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
February, 2013 − Rev. 5
NCV4276B/D
NCV4276B
I
Q
Error
Amplifier
Current Limit and
Saturation Sense
Bandgap
Reference
−
+
Thermal
Shutdown
INH
GND
NC
Figure 1. NCV4276B Block Diagram
I
Q
Error
Amplifier
Current Limit and
Saturation Sense
Bandgap
Reference
−
+
Thermal
Shutdown
INH
GND
VA
Figure 2. NCV4276B Adjustable Block Diagram
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NCV4276B
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Symbol
I
Description
1
2
3
4
Input; Battery Supply Input Voltage.
INH
Inhibit; Set low-to inhibit.
GND
NC/VA
Ground; Pin 3 internally connected to heatsink.
Not connected for fixed voltage version/Voltage Adjust Input for adjustable voltage version; use an external
voltage divider to set the output voltage
5
Q
Output: Bypass with a capacitor to GND. See Figures 3 to 7 and Regulator Stability Considerations section.
Table 2. MAXIMUM RATINGS*
Rating
Symbol
Min
−42
−
Max
45
Unit
V
Input Voltage
V
I
V
I
Input Peak Transient Voltage
Inhibit INH Voltage
45
V
V
−42
−0.3
−1.0
−
45
V
INH
Voltage Adjust Input VA
Output Voltage
V
10
V
VA
V
40
V
Q
Ground Current
I
100
40
mA
V
q
Input Voltage Operating Range
V
V
Q
+ 0.5 V or 4.5 V
(Note 1)
I
ESD Susceptibility
(Human Body Model)
(Machine Model)
(Charged Device Model)
−
−
−
4.0
250
1.25
−
−
−
kV
V
kV
Junction Temperature
Storage Temperature
T
−40
−50
150
150
C
C
J
T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal
dissipation must be observed closely.
1. Minimum V = 4.5 V or (V + 0.5 V), whichever is higher.
I
Q
Table 3. LEAD TEMPERATURE SOLDERING REFLOW (Note 2)
Lead Temperature Soldering
T
SLD
C
Reflow (SMD styles only), Leaded, 60−150 s above 183, 30 s max at peak
Reflow (SMD styles only), Lead Free, 60−150 s above 217, 40 s max at peak
Wave Solder (through hole styles only), 12 sec max
−
−
−
240
265
310
2. Per IPC/JEDEC J−STD−020C.
Table 4. THERMAL CHARACTERISTICS (Notes 3 and 4)
Characteristic
Test Conditions (Typical Value)
Unit
DPAK 5-PIN PACKAGE
Min Pad Board (Note 5)
1, Pad Board (Note 6)
Junction-to-Tab (psi-JLx, y
)
4.2
4.7
C/W
C/W
JLx
Junction-to-Ambient (R , q
)
)
100.9
46.8
q
JA JA
2
D PAK 5-PIN PACKAGE
0.4 sq. in. Spreader Board (Note 7)
1.2 sq. in. Spreader Board (Note 8)
Junction-to-Tab (psi-JLx, y
)
3.8
4.0
C/W
C/W
JLx
Junction-to-Ambient (R , q
74.8
41.6
q
JA JA
3. Minimum V = 4.5 V or (V + 0.5 V), whichever is higher.
I
Q
4. Per IPC/JEDEC J−STD−020C.
2
2
2
5. 1 oz. copper, 0.26 inch (168 mm ) copper area, 0.062 thick FR4.
2
6. 1 oz. copper, 1.14 inch (736 mm ) copper area, 0.062 thick FR4.
2
2
2
2
7. 1 oz. copper, 0.373 inch (241 mm ) copper area, 0.062 thick FR4.
8. 1 oz. copper, 1.222 inch (788 mm ) copper area, 0.062 thick FR4.
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NCV4276B
Table 5. ELECTRICAL CHARACTERISTICS (V = 13.5 V; −40C < T < 150C; unless otherwise noted.)
I
J
NCV4276B
Typ
Min
Max
Characteristic
OUTPUT
Symbol
Test Conditions
Unit
Output Voltage, 5.0 V Version
Output Voltage, 5.0 V Version
Output Voltage, 3.3 V Version
Output Voltage, 3.3 V Version
V
V
V
V
5.0 mA < I < 400 mA,
4.9
4.9
5.0
5.0
3.3
3.3
−
5.1
5.1
V
V
V
V
V
Q
Q
Q
Q
Q
6.0 V < V < 28 V
I
5.0 mA < I < 200 mA,
Q
6.0 V < V < 40 V
I
5.0 mA < I < 400 mA,
3.234
3.234
−2%
3.366
3.366
+2%
Q
4.5 V < V < 28 V
I
5.0 mA < I < 200 mA,
Q
4.5 V < V < 40 V
I
Output Voltage, Adjustable
Version
AV
5.0 mA < I < 400 mA
Q
Q
V +1 < V < 40 V
Q
I
I
V > 4.5 V
Output Current Limitation
I
V
V
= 90% V
(V = 2.5 V for ADJ Version)
QTYP
400
700
1100
10
mA
Q
Q
QTYP
Quiescent Current (Sleep Mode)
I
= 0 V
−
−
mA
q
INH
I = I − I
q
I
Q
Quiescent Current, I = I − I
I
I
I
I
I
= 1.0 mA
= 250 mA
= 400 mA
−
−
−
130
10
200
15
mA
mA
mA
q
I
Q
Q
Q
q
q
q
Q
Q
Q
Q
Quiescent Current, I = I − I
I
I
q
I
Quiescent Current, I = I − I
25
35
q
I
Dropout Voltage,
Adjustable Version
V
DR
= 250 mA, V = V − V
DR I
V > 4.5 V
Q
−
−
−
−
250
250
3.0
4.0
500
500
20
mV
mV
mV
mV
I
Dropout Voltage (5.0 V Version)
Load Regulation
V
DR
I
Q
I
Q
= 250 mA (Note 9)
DV
= 5.0 mA to 400 mA
Q,LO
Line Regulation
DV
DV = 12 V to 32 V,
15
Q
I
I
Q
= 5.0 mA
Power Supply Ripple Rejection
Temperature Output Voltage Drift
INHIBIT
PSRR
f = 100 Hz, V = 0.5 V
−
−
70
−
−
dB
r
r
PP
d
−
0.5
mV/K
VQ/dT
Inhibit Voltage, Output High
Inhibit Voltage, Output Low (Off)
Input Current
V
V
V
V
V
w V
QMIN
−
2.3
2.2
10
2.8
−
V
V
INH
INH
INH
Q
v 0.1 V
1.8
5.0
Q
I
= 5.0 V
20
mA
INH
THERMAL SHUTDOWN
Thermal Shutdown Temperature*
T
SD
I
Q
= 5.0 mA
150
−
210
C
*Guaranteed by design, not tested in production.
9. Measured when the output voltage V has dropped 100 mV from the nominal valued obtained at V = 13.5 V.
Q
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NCV4276B
Output
I
I
I
Q
I 1
5 Q
5.5 − 45 V
C
1.0 mF
C
C
Q
22 mF
I1
I2
Input
100 nF
NCV4276B
INH
NC
R
L
2
4
3
I
INH
GND
Figure 3. Applications Circuit; Fixed Voltage Version
V
Q
= [(R1 + R2) * V ] / R2
ref
Output
I
I
I
Q
I 1
5 Q
Input
C
I1
C
I2
C
Q
C *
b
1.0 mF
100 nF
22 mF
NCV4276B
R
R
1
INH
VA
R
L
2
4
3
I
INH
GND
2
C * − Required if usage of low ESR output capacitor C is demand, see Regulator Stability Considerations section
b
Q
Figure 4. Applications Circuit; Adjustable Voltage Version
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS
10
C
= 22 mF for all
Q
Unstable Region
Stable Region
Fixed Output Voltages
1
0.1
Maximum ESR
for C = 22 mF
Q
0.01
0
50
100
150 200
250
300
350 400
I , OUTPUT CURRENT (mA)
Q
Figure 5. Output Stability with Output Capacitor
ESR, 5.0 V and 3.3 V Regulator
10
C
= 10 mF for 3.3 V and
Q
Unstable Region
Stable Region
5 V Fixed Output Voltages
1
Maximum ESR
for C = 10 mF
Q
0.1
0.01
0
50
100
150 200
250
300
350 400
I , OUTPUT CURRENT (mA)
Q
Figure 6. Output Stability with Output Capacitor
ESR, 5.0 V and 3.3 V Regulator
100
10
C
Q
= 22 mF for these
Output Voltages
Unstable Region
12 V
6 V
1
2.5 V
Stable Region
0.1
0.01
Unstable Region
C capacitor not connected
b
0
50
100
150 200
250
300
350 400
I , OUTPUT CURRENT (mA)
Q
Figure 7. Output Stability with Output Capacitor
ESR, Adjustable Regulator
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − 4276B Version
5.2
5.1
5.0
3.45
V = 13.5 V
R = 1 kW
L
I
V = 13.5 V
R = 1 kW
L
I
3.40
3.35
3.30
3.25
4.9
4.8
3.20
3.15
−40
0
40
80
120
160
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (C)
J
T , JUNCTION TEMPERATURE (C)
J
Figure 8. Output Voltage vs.
Figure 9. Output Voltage vs.
Junction Temperature, 5.0 V Version
Junction Temperature, 3.3 V Version
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
40
30
20
R = 20 W
T = 25C
J
L
T = 25C
R = 20 W
L
J
10
0
2.0
1.0
0
0
10
20
30
40
50
0
10
20
30
40
50
V , INPUT VOLTAGE (V)
I
V , INPUT VOLTAGE (V)
I
Figure 10. Current Consumption vs.
Input Voltage, 5.0 V Version
Figure 11. Current Consumption vs. Input
Voltage, 3.3 V Version
6.0
5.0
4.0
3.0
2.0
6.0
5.0
4.0
3.0
2.0
T = 25C
R = 20 W
L
J
R = 20 W
T = 25C
J
L
1.0
0
1.0
0
0
1.0
2.0
3.0
4.0
5.0
6.0
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (V)
I
V , INPUT VOLTAGE (V)
I
Figure 12. Low Voltage Behavior, 5.0 V Version
Figure 13. Low Voltage Behavior, 3.3 V Version
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − 4276B Version
2.0
0
6.0
4.0
2.0
0
−2.0
−4.0
−6.0
−2.0
−4.0
−6.0
R = 6.8 kW
T = 25C
J
L
−8.0
−10
R = 6.8 kW
T = 25C
J
L
−8.0
−10
−50
−25
0
25
50
−50
−25
0
25
50
50
60
V , INPUT VOLTAGE (V)
V , INPUT VOLTAGE (V)
I
I
Figure 14. Input Current vs. Input Voltage,
5.0 V Version
Figure 15. Input Current vs. Input Voltage,
3.3 V Version
600
500
800
600
400
T = 25C
J
V
Q
= 0 V
T = 125C
J
400
300
200
T = 25C
J
200
0
100
0
0
100
200
300
400
0
10
20
30
40
I , OUTPUT CURRENT (mA)
Q
V , INPUT VOLTAGE (V)
I
Figure 16. Dropout Voltage vs.
Output Current
Figure 17. Maximum Output Current vs.
Input Voltage
60
50
40
30
20
1.6
1.4
1.2
1.0
V = 13.5 V
T = 25C
J
I
V = 13.5 V
T = 25C
I
J
0.8
0.6
0.4
10
0
0.2
0
0
100
200
300
400
500
600
0
10
20
30
40
50
I , OUTPUT CURRENT (mA)
Q
I , OUTPUT CURRENT (mA)
Q
Figure 18. Current Consumption vs.
Output Current (High Load)
Figure 19. Current Consumption vs.
Output Current (Low Load)
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
5.0
4.5
T = 25C
R = 20 W
L
J
V = 13.5 V
T = 25C
J
I
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.46
2.45
0.5
0
−40
0
40
80
120
160
0
10
20
30
40
50
T , JUNCTION TEMPERATURE (C)
J
V , INPUT VOLTAGE (V)
I
Figure 20. Output Voltage vs. Junction
Temperature, Adjustable Version
Figure 21. Current Consumption vs. Input
Voltage, Adjustable Version
4
3.5
3
2
0
T = 25C
R = 20 W
L
J
−2
−4
2.5
2
−6
−8
−10
−12
−14
1.5
1
T = 25C
R = 6.8 kW
L
J
0.5
0
−16
−18
−50
−25
0
25
50
0
2
4
6
8
10
V , INPUT VOLTAGE (V)
I
V , INPUT VOLTAGE (V)
I
Figure 22. Low Voltage Behavior,
Adjustable Version
Figure 23. High Voltage Behavior,
Adjustable Version
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
600
500
400
300
200
800
700
600
T = 125C
J
500
400
T = 25C
J
V
Q
= 0 V
T = 25C
J
300
200
100
0
100
0
0
50
100
150 200
250 300
350 400
0
10
20
30
40
50
I , OUTPUT CURRENT (mA)
Q
V , INPUT VOLTAGE (V)
I
Figure 24. Dropout Voltage vs. Output Current,
Regulator Set at 5.0 V, Adjustable Version
Figure 25. Maximum Output Current vs.
Input Voltage, Adjustable Version
60
50
40
30
20
1.6
1.4
1.2
1.0
0.8
0.6
0.4
T = 25C
V = 13.5 V
I
T = 25C
V = 13.5 V
I
J
J
10
0
0.2
0
0
100
200
300
400
500
600
0
10
20
30
40
50
60
I , OUTPUT CURRENT (mA)
Q
I , OUTPUT CURRENT (mA)
Q
Figure 26. Current Consumption vs.
Output Current (High Load), Adjustable Version
Figure 27. Current Consumption vs. Output
Current (Low Load), Adjustable Version
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NCV4276B
Circuit Description
Minimum ESR for C = 22 mF is native ESR of ceramic
Q
The NCV4276B is an integrated low dropout regulator
that provides a regulated voltage at 400 mA to the output.
It is enabled with an input to the inhibit pin. The regulator
voltage is provided by a PNP pass transistor controlled by
an error amplifier with a bandgap reference, which gives it
the lowest possible dropout voltage. The output current
capability is 400 mA, and the base drive quiescent current
is controlled to prevent oversaturation when the input
voltage is low or when the output is overloaded. The
regulator is protected by both current limit and thermal
shutdown. Thermal shutdown occurs above 150C to
protect the IC during overloads and extreme ambient
temperatures.
capacitor with which the fixed output voltage devices are
performing stable. Murata ceramic capacitors were used,
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210),
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206).
Calculating Bypass Capacitor
If usage of low ESR ceramic capacitors is demand in case
of Adjustable Regulator, connect the bypass capacitor C
b
between Voltage Adjust pin and Q pin according to
Applications circuit at Figure 4.
Parallel combination of bypass capacitor C with the
b
feedback resistor R contributes in the device transfer
1
function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention
to the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (V ) and drives the base of a
Q
PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature-stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. See Figure 4, Test Circuit, for
circuit element nomenclature illustration.
1
C
b
+
@ (F)
(eq. 1)
2 p f R
z
1
where
R = the upper feedback resistor
1
f = the frequency of the zero added into the device
z
Regulator Stability Considerations
transfer function by R and C external components.
1
b
The input capacitors (C and C ) are necessary to
I1
I2
Set the R resistor according to output voltage
1
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 W in
requirement. Chose the f with regard on the output
z
capacitance C , refer to the table below.
Q
series with C can stop potential oscillations caused by
I2
stray inductance and capacitance.
C
Q
(mF)
10
22
47
100
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25C to −40C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information.
f Range (kHz)
20 - 50
14 - 35
10 - 20
7 – 14
z
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors C from the
table above to define the frequency ranges of additional
zero required for stability.
Q
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
The value for the output capacitor C , shown in Figure 3,
Q
should work for most applications; see also Figures 5 to 7
for output stability at various load and Output Capacitor
ESR conditions. Stable region of ESR in Figures 5 to 7
shows ESR values at which the LDO output voltage does
not have any permanent oscillations at any dynamic
changes of output load current. Marginal ESR is the value
at which the output voltage waving is fully damped during
four periods after the load change and no oscillation is
further observable.
Inhibit Input
The inhibit pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 1.8 V, the output
of the regulator will be turned off. When the voltage on the
Inhibit pin is greater than 2.8 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage. The inhibit pin may be connected directly to the
input pin to give constant enable to the output regulator.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
Setting the Output Voltage (Adjustable Version)
The output voltage range of the adjustable version can be
set between 2.5 V and 20 V. This is accomplished with an
external resistor divider feeding back the voltage to the IC
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NCV4276B
I
Q
I
I
back to the error amplifier by the voltage adjust pin VA.
The internal reference voltage is set to a temperature stable
reference of 2.5 V.
SMART
REGULATOR
V
I
V
Q
The output voltage is calculated from the following
formula. Ignoring the bias current into the VA pin:
Control
Features
(eq. 2)
V
Q
+ [(R1 ) R2) * V ] ń R2
ref
Iq
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
Figure 28. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
The input voltage range for operation (pin 1) of the
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
adjustable version is between (V + 0.5 V) and 40 V.
Q
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
4.0 V is (4.5 V − V ).
Q
Calculating Power Dissipation
summed to determine the value of R
:
JA
q
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 28) is:
(eq. 5)
R
qJA
+ R
qJC
) R ) R
qCS qSA
where:
R
P
+ [V
* V )
]I
D(max)
I(max)
I
Q(min) Q(max)
is the junction-to-case thermal resistance,
is the case-to-heatsink thermal resistance,
is the heatsink-to-ambient thermal resistance.
JC
q
(eq. 3)
) V
R
I(max) q
CS
SA
q
q
R
where:
R
appears in the package section of the data sheet.
JC
q
V
V
I
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
application,
is the quiescent current the regulator
I(max)
Q(min)
Q(max)
Like R , it too is a function of package type. R
and
JA
CS
q
q
R
are functions of the package type, heatsink and the
SA
q
interface between them. These values appear in data sheets
of heatsink manufacturers.
I
q
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
consumes at I
.
Q(max)
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
JA
q
o
T
150 C *
A
Thermal Model
See pages 13 to 16 for detailed information about thermal
model parameters.
(eq. 4)
R
+
qJA
P
D
The value of R
can then be compared with those in the
JA
q
package section of the data sheet. Those packages with
less than the calculated value in Equation 4 will keep
R
JA
q
the die temperature below 150C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
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12
NCV4276B
Table 6. DPAK 5-LEAD THERMAL RC NETWORK MODELS
2
2
2
2
Drain Copper Area (1 oz thick)
(SPICE Deck Format)
168 mm
736 mm
168 mm
736 mm
Cauer Network
Foster Network
2
2
168 mm
1.00E−06
1.00E−05
6.00E−05
1.00E−04
4.36E−04
6.77E−02
1.51E−01
4.80E−01
3.740
736 mm
Units
Tau
Tau
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
C_C1
C_C2
C_C3
C_C4
C_C5
C_C6
C_C7
C_C8
C_C9
C_C10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.00E−06
1.00E−05
6.00E−05
1.00E−04
3.64E−04
1.92E−02
1.27E−01
1.018
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
1.36E−08
7.41E−07
1.04E−05
3.91E−05
1.80E−03
3.77E−01
3.79E+00
2.65E+01
8.71E+01
1.361E−08
7.411E−07
1.029E−05
3.737E−05
1.376E−03
2.851E−02
9.475E−01
1.173E+01
8.59E+01
2.955
10.322
0.438
2
2
168 mm
736 mm
R’s
R’s
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_R9
R_R10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
node1
node2
node3
node4
node5
node6
node7
node8
node9
GND
0.015
0.08
0.015
0.08
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
0.0123
0.0585
0.0304
0.3997
3.115
0.0123
0.0585
0.0287
0.3772
2.68
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
0.4
0.4
0.2
0.2
2.97519
8.2971
25.9805
46.5192
17.7808
0.1
2.6171
1.6778
7.4246
14.9320
19.2560
0.1758
3.571
1.38
12.851
35.471
46.741
5.92
7.39
28.94
NOTE: Bold face items represent the package without the external thermal system.
R
1
R
2
R
3
R
n
Junction
C
1
C
2
C
3
C
n
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 29. Grounded Capacitor Thermal Network (“Cauer” Ladder)
R
1
R
2
R
3
R
n
Junction
C
1
C
2
C
3
C
n
Each rung is exactly characterized by its RC-product
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 30. Non-Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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13
NCV4276B
Table 7. D2PAK 5-LEAD THERMAL RC NETWORK MODELS
2
2
2
2
Drain Copper Area (1 oz thick)
(SPICE Deck Format)
241 mm
788 mm
241 mm
788 mm
Cauer Network
Foster Network
2
2
241 mm
1.00E−06
1.00E−05
6.00E−05
1.00E−04
2.82E−04
5.58E−03
4.25E−01
9.22E−01
1.73
653 mm
Units
Tau
Tau
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
C_C1
C_C2
C_C3
C_C4
C_C5
C_C6
C_C7
C_C8
C_C9
C_C10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.00E−06
1.00E−05
6.00E−05
1.00E−04
2.87E−04
5.95E−03
4.61E−01
2.05
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
1.361E−08
7.411E−07
1.005E−05
3.460E−05
7.868E−04
7.431E−03
2.786E+00
2.014E+01
1.134E+02
1.361E−08
7.411E−07
1.007E−05
3.480E−05
8.107E−04
7.830E−03
2.012E+00
2.601E+01
1.218E+02
4.88
7.12
1.31
2
2
241 mm
653 mm
R’s
R’s
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_R9
R_R10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
node1
node2
node3
node4
node5
node6
node7
node8
node9
GND
0.015
0.08
0.0150
0.0800
0.4000
0.2000
1.8839
1.2272
5.3383
18.9591
13.3369
0.1191
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
0.0123
0.0585
0.0257
0.3413
1.77
0.0123
0.0585
0.0260
0.3438
1.81
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
0.4
0.2
1.85638
1.23672
9.81541
33.1868
27.0263
1.13944
1.54
1.52
4.13
3.46
6.27
5.03
60.80
29.30
NOTE: Bold face items represent the package without the external thermal system.
The Cauer networks generally have physical
significance and may be divided between nodes to separate
thermal behavior due to one portion of the network from
another. The Foster networks, though when sorted by time
constant (as above) bear a rough correlation with the Cauer
networks, are really only convenient mathematical models.
Cauer networks can be easily implemented using circuit
simulating tools, whereas Foster networks may be more
easily implemented using mathematical tools (for instance,
in a spreadsheet program), according to the following
formula:
n
−tńtau
i
ǒ
R 1−e
i
Ǔ
(eq. 6)
R(t) +
S
i + 1
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14
NCV4276B
110
100
90
110
100
90
80
80
70
70
1 oz
1 oz
60
60
2 oz
2 oz
50
50
40
40
30
30
150 200 250 300 350 400 450 500 550 600 650 700 750
150 200 250 300 350 400 450 500 550 600 650 700 750
2
2
COPPER AREA (mm )
COPPER AREA (mm )
Figure 31. qJA vs. Copper Spreader Area,
Figure 32. qJA vs. Copper Spreader Area,
DPAK 5-Lead
D2PAK 5-Lead
100
2
Cu Area 167 mm
2
Cu Area 736 mm
10
1.0
0.1
sqrt(t)
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
TIME (sec)
Figure 33. Single-Pulse Heating Curves, DPAK 5-Lead
100
10
2
Cu Area 167 mm
2
Cu Area 736 mm
1.0
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
TIME (sec)
Figure 34. Single-Pulse Heating Curves, D2PAK 5-Lead
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15
NCV4276B
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
1.0
0.1
Non−normalized Response
0.01
0.0000001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE WIDTH (sec)
Figure 35. Duty Cycle for 1, Spreader Boards, DPAK 5-Lead
100
50% Duty Cycle
20%
10
1.0
10%
5%
2%
1%
0.1
Non−normalized Response
0.01
0.0000001 0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE WIDTH (sec)
Figure 36. Duty Cycle for 1, Spreader Boards, D2PAK 5-Lead
Table 8. ORDERING INFORMATION
†
Device
Output Voltage Accuracy
Output Voltage
Package
Shipping
NCV4276BDT33RKG
DPAK, 5-Pin
(Pb-Free)
2,500 / Tape & Reel
800 / Tape & Reel
2,500 / Tape & Reel
800 / Tape & Reel
2,500 / Tape & Reel
800 / Tape & Reel
3.3 V
2
NCV4276BDS33R4G
NCV4276BDT50RKG
NCV4276BDS50R4G
NCV4276BDTADJRKG
NCV4276BDSADJR4G
D PAK, 5-Pin
(Pb-Free)
DPAK, 5-Pin
(Pb-Free)
2%
5.0 V
2
D PAK, 5-Pin
(Pb-Free)
DPAK, 5-Pin
(Pb-Free)
Adjustable
2
D PAK, 5-Pin
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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16
NCV4276B
PACKAGE DIMENSIONS
DPAK 5, CENTER LEAD CROP
DT SUFFIX
CASE 175AA
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
−T−
PLANE
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.51
0.46
0.61
MAX
6.22
6.73
2.38
0.71
0.58
0.81
E
V
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
R1
Z
A
K
S
4.56 BSC
1 2 3 4
5
0.87
0.46
2.60
1.01
0.58
2.89
U
K
L
1.14 BSC
R
0.170 0.190
4.32
4.70
0.63
0.51
0.89
3.93
4.83
5.33
1.01
−−−
1.27
4.32
F
J
R1 0.185 0.210
S
U
V
Z
0.025 0.040
0.020 −−−
0.035 0.050
0.155 0.170
L
H
D 5 PL
M
G
0.13 (0.005)
T
SOLDERING FOOTPRINT*
6.4
0.252
2.2
0.086
0.34
0.013
5.8
0.228
5.36
0.217
10.6
0.417
0.8
0.031
mm
inches
ǒ
Ǔ
SCALE 4:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
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17
NCV4276B
PACKAGE DIMENSIONS
D2PAK 5
CASE 936A−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A
AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED 0.025
(0.635) MAXIMUM.
−T−
TERMINAL 6
OPTIONAL
CHAMFER
A
E
U
S
K
V
B
H
1
2
3
4 5
INCHES
MILLIMETERS
M
L
DIM
A
B
C
D
E
MIN
MAX
0.403
0.368
0.180
0.036
0.055
MIN
9.804
9.042
4.318
0.660
1.143
MAX
10.236
9.347
4.572
0.914
1.397
0.386
0.356
0.170
0.026
0.045
D
M
P
N
0.010 (0.254)
T
G
R
G
H
K
L
M
N
P
0.067 BSC
1.702 BSC
14.707
1.270 REF
0.539
0.579 13.691
0.050 REF
0.000
0.088
0.018
0.058
0.010
0.102
0.026
0.078
0.000
2.235
0.457
1.473
0.254
2.591
0.660
1.981
C
R
S
U
V
5_ REF
5_ REF
0.116 REF
0.200 MIN
0.250 MIN
2.946 REF
5.080 MIN
6.350 MIN
SOLDERING FOOTPRINT
8.38
0.33
1.702
0.067
10.66
0.42
1.016
0.04
3.05
0.12
16.02
0.63
mm
inches
ǒ
Ǔ
SCALE 3:1
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