NCV4279BD2R2G [ONSEMI]
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NCV4279B
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Monitor FLAG
http://onsemi.com
MARKING DIAGRAMS
The NCV4279B is a 5.0 V precision micropower voltage regulator.
The output current capability is 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature
drawing only 90 mA with a 100 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
8
SO−8
4279B
ALYW
D SUFFIX
CASE 751
8
1
Microprocessor control logic includes an active RESET (with
DELAY), and a FLAG monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending RESET
signal. The use of the FLAG monitor allows the microprocessor to
finish any signal processing before the RESET shuts the
microprocessor down.
1
14
SO−14
D SUFFIX
CASE 751A
NCV4279B
AWLYWW
14
1
1
20
The active RESET circuit operates correctly at an output voltage as
low as 1.0 V. The RESET function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
NCV4279B
AWLYYWW
20
SO−20L
DW SUFFIX
CASE 751D
1
The reset threshold voltage can be decreased by the connection of
1
external resistor divider to R
lead.
ADJ
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments. The
device has also been optimized for EMC conditions.
WW, W = Work Week
PIN CONNECTIONS
1
8
SO−8
V
IN
V
OUT
Features
• 5.0 V ± 2.0% Output
• Low 90 mA Quiescent Current
• Active RESET
• Adjustable Reset
• 150 mA Output Current Capability
• Fault Protection
MON
FLAG
RESET
GND
R
ADJ
DELAY
1
14
SO−14
R
MON
ADJ
DELAY
GND
GND
V
IN
GND
GND
GND
GND
− +60 V Peak Transient Voltage
− −15 V Reverse Voltage
NC
V
OUT
RESET
FLAG
− Short Circuit
− Thermal Overload
• Early Warning through FLAG/MON Leads
• Internally Fused Leads in SO−14 and SO−20L Packages
1
20
SO−20L
R
MON
ADJ
DELAY
NC
GND
GND
GND
GND
V
IN
NC
GND
GND
GND
GND
NC
• NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
NC
NC
V
OUT
RESET
FLAG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
August, 2003 − Rev. 1
NCV4279B/D
NCV4279B
V
BAT
V
IN
V
R
V
DD
OUT
10 µF
10 µF
ADJ
NCV4279B
R
R
RST
FLG
10 k
10 k
Delay
MON
C
DELAY
RESET
I/O
FLAG
I/O
GND
Figure 1. Application Diagram
MAXIMUM RATINGS*{
Rating
Value
Unit
V
V
IN
(DC)
−15 to 45
60
Peak Transient Voltage (46 V Load Dump @ V = 14 V)
V
IN
Operating Voltage
45
V
V
OUT
(DC)
16
V
Voltage Range (RESET, FLAG)
Input Voltage Range (MON)
−0.3 to 10
−0.3 to 10
2.0
V
V
ESD Susceptibility (Human Body Model)
kV
°C
°C
°C/W
Junction Temperature, T
−40 to +150
−55 to 150
J
Storage Temperature, T
S
Package Thermal Resistance, SO−8:
Junction−to−Case, R
45
θ
JC
165
Junction−to−Ambient, R
θ
JA
Package Thermal Resistance, SO−14 (Fused) Minimum Pad Data:
Junction−to−Case, R
°C/W
°C/W
°C
15
110
33
θ
JC
Junction−to−Ambient, R
θ
JA
Junction−to−Pin, R
(Note 3)
θ
JP
Package Thermal Resistance, SO−20L (Fused) Minimum Pad Data:
Junction−to−Case, R
12
82
26
θ
JC
Junction−to−Ambient, R
θ
JA
Junction−to−Pin, R
(Note 4)
θ
JP
Lead Temperature Soldering:
Reflow: (SMD styles only) (Notes 1, 2)
240 peak
1. 60 second maximum above 183°C.
2. −5°C/+0°C allowable conditions.
3. Measured to pin 9.
4. Measured to pin 12.
*The maximum package power dissipation must be observed.
†During the voltage range which exceeds the maximum tested voltage of V , operation is assured, but not specified. Wider limits may apply.
IN
Thermal dissipation must be observed closely.
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2
NCV4279B
ELECTRICAL CHARACTERISTICS (I
Characteristic
= 1.0 mA, −40°C ≤ T ≤ 125°C; 6.0 V < V < 26 V; unless otherwise specified.)
OUT
J
IN
Test Conditions
Min
Typ
Max
Unit
Output Stage
Output Voltage
9.0 V < V < 16 V, 100 mA ≤ I
≤ 150 mA
≤ 150 mA
4.90
4.85
5.0
5.0
5.10
5.15
V
V
IN
OUT
OUT
6.0 V < V < 26 V, 100 mA ≤ I
IN
Dropout Voltage (V − V
)
I
I
= 150 mA
= 100 mA
−
−
400
100
600
150
mV
mV
IN
OUT
OUT
OUT
Load Regulation
Line Regulation
V
= 14 V, 5.0 mA ≤ I
≤ 150 mA
-30
−
5.0
15
30
60
mV
mV
IN
OUT
[V
(typ) + 1.0] < V < 26 V, I
OUT
= 1.0 mA
IN
OUT
Quiescent Current, (I )
Active Mode
I
= 100 mA, V = 12 V, Delay = 3.0 V, MON = 3.0 V
= 75 mA, V = 14 V, Delay = 3.0 V, MON = 3.0 V
−
−
−
90
4.0
12
125
6.0
19
mA
mA
mA
Q
OUT
IN
I
OUT IN
I
≤ 150 mA, V = 14 V, Delay = 3.0 V, MON = 3.0 V
OUT
IN
Current Limit
−
151
40
300
190
180
−
−
−
mA
mA
°C
Short Circuit Output Current
Thermal Shutdown
V
= 0 V
OUT
(Guaranteed by Design)
150
Reset Function (RESET)
RESET Threshold
HIGH (V
)
V
OUT
V
OUT
Increasing
Decreasing
4.55
4.50
4.70
4.60
0.98 × V
0.97 × V
V
V
RH
)
OUT
OUT
LOW (V
RL
Output Voltage
Low (V
)
1.0 V ≤ V
≤ V , R
= 10 k
−
1.4
−
0.1
1.8
−
0.4
2.2
0.1
3.5
−
V
V
RLO
OUT
RL
RESET
Delay Switching Threshold (V
Reset Delay Low Voltage
Delay Charge Current
)
DT
−
V
OUT
< RESET Threshold Low(min)
V
DELAY = 1.0 V, V
DELAY = 1.0 V, V
> V
1.5
5.0
1.23
2.5
−
mA
mA
V
OUT
OUT
RH
Delay Discharge Current
= 1.5 V
−
Reset Adjust Switching Voltage
(V
1.31
1.39
)
R(ADJ)
FLAG/Monitor
Monitor Threshold
Hysteresis
Increasing and Decreasing
1.10
20
1.20
50
1.31
100
0.5
V
mV
mA
V
−
Input Current
MON = 2.0 V
MON = 0 V, I
−0.5
−
0.1
0.1
Output Saturation Voltage
= 1.0 mA
0.4
FLAG
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3
NCV4279B
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
SO−14
SO−20L
Pin Symbol
Function
3
4
5
−
6
7
8
1
2
1
1
R
Reset Adjust. If not needed connect to ground.
Timing capacitor for RESET function.
Ground. All GND leads must be connected to Ground
No connection.
ADJ
2
2
DELAY
GND
3−5, 10−12
4−7, 14−17
.
6
7
3, 8, 9, 13, 18
NC
10
11
12
19
20
RESET
FLAG
Active reset (accurate to V
≥ 1.0 V)
OUT
8
Open collector output from early warning comparator.
±2.0%, 150 mA output.
9
V
OUT
13
14
V
Input Voltage.
IN
MON
Monitor. Input for early warning comparator. If not needed connect to V
OUT.
TYPICAL PERFORMANCE CHARACTERISTICS
5.01
5.00
4.99
4.98
1.2
V
= 12 V
V
V
I
= 5.0 V
= 14 V
= 5.0 mA
IN
OUT
IN
1.0
0.8
0.6
0.4
0.2
0
+125°C
OUT
+25°C
−40°C
−40 −25 −10
5
20 35 50 65 80 95 110 125
0
5
10
I
15
(mA)
20
25
Temperature (°C)
OUT
Figure 2. Output Voltage vs. Temperature
Figure 3. Quiescent Current vs. Output Current
14
12
10
8
7
6
5
4
3
2
1
0
V
= 12 V
IN
T = 25°C
I
= 100 mA
OUT
+125°C
+25°C
6
−40°C
I
I
= 50 mA
= 10 mA
OUT
4
2
OUT
0
0
15 30 45 60 75 90 105 120 135 140
(mA)
6
8
10 12 14 16 18 20 22 24 26
(V)
I
V
IN
OUT
Figure 4. Quiescent Current vs. Output Current
Figure 5. Quiescent Current vs. Input Voltage
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4
NCV4279B
TYPICAL PERFORMANCE CHARACTERISTICS
120
100
80
60
49
20
0
450
T = 25°C
400
I
= 100 mA
350
300
250
200
150
100
50
OUT
+125°C
+25°C
−40°C
0
6
8
10 12 14 16 18 20 22 24 26
(V)
0
25
50
75
(mA)
100
125
150
V
IN
I
OUT
Figure 6. Quiescent Current vs. Input Voltage
Figure 7. Dropout Voltage vs. Output Current
1000
100
10
1000
C
= 10 mF
Unstable Region
Vout
Unstable Region
C
= 0.1 mF
Vout
100
10
1
1
Stable Region
Stable Region
= 10 mF
0.1
C
Vout
0.01
0
10 20 30 40 50 60 70 80 90 100110120130140150
OUTPUT CURRENT (mA)
0
10
20 30 40
50 60 70 80 90 100 110
OUTPUT CURRENT (mA)
Figure 8. Output Capacitor ESR
Figure 9. Output Stability with Output
Capacitor Change
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5
NCV4279B
V
OUT
V
IN
Current Source
(Circuit Bias)
I
BIAS
Current Limit
Sense
+
+
−
R
ADJ
I
BIAS
+
V
BG
−
Error Amplifier
V
BG
RESET
+
1.8 V
−
Thermal
Protection
3.0 µA
Bandgap
Delay
MON
Reference
I
V
BG
BIAS
GND
V
BG
I
BIAS
FLAG
+
−
Figure 10. Block Diagram
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6
NCV4279B
CIRCUIT DESCRIPTION
DELAY Function
REGULATOR CONTROL FUNCTIONS
The NCV4279B contains the microprocessor compatible
control function RESET (Figure 11).
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The DELAY lead provides source current (typically
2.5 mA) to the external DELAY capacitor during the
following proceedings:
V
IN
1. During Power Up (once the regulation threshold
has been verified).
RESET
V
OUT
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
Threshold
DELAY
RESET
DELAY
Threshold
(V
)
DT
T
T
d
d
Figure 11. Reset and Delay Circuit Wave Forms
FLAG/Monitor Function
RESET Function
An on−chip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 13). The typical
threshold is 1.20 V on the MON Pin.
A RESET signal (low voltage) is generated as the IC
powers up until V is within 6.0% of the regulated output
OUT
voltage, or when V
drops out of regulation,and is lower
OUT
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for V
as 1.0 V.
as low
OUT
Adjustable Reset Function
The reset threshold can be made lower by connecting an
external resistor divider to the R lead from the V
lead, as displayed in Figure 12. This lead is grounded to
select the default value of 4.6 V.
V
BAT
V
OUT
V
V
CC
IN
ADJ
OUT
µP
NCV4279B
C
OUT
I/O
MON
FLAG
R
RESET
ADJ
RESET
GND
to µP and
System
Power
Delay
V
OUT
R
ADJ
C
OUT
Figure 13. FLAG/Monitor Function
R
RST
NCV4279B
RESET
Delay
to µP and
RESET
Port
C
DELAY
Figure 12. Adjustable RESET
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7
NCV4279B
APPLICATION NOTES
FLAG MONITOR
The value for the output capacitor C
shown in Figure 15
OUT
Figure 14 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 13. As the output voltage
should work for most applications, however it is not
necessarily the optimized solution.
falls (V
), the Monitor threshold is crossed. This causes
OUT
V
the voltage on the FLAG output to go low sending a warning
signal to the microprocessor that a RESET signal may occur
IN
V
OUT
C
0.1 mF
*
IN
C
10 mF
**
NCV4279B
OUT
in a short period of time. T
microprocessor has to complete the function it is currently
working on and get ready for the RESET shutdown signal.
is the time the
R
WARNING
RST
RESET
V
OUT
*C required if regulator is located far from the power supply filter.
IN
MON
**C
required for stability. Capacitor must operate at minimum
temperature expected.
OUT
FLAG Monitor
Ref. Voltage
Figure 15. Test and Application Circuit Showing
Output Compensation
RESET
FLAG
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 16) is:
P
+ [V
* V
]I
OUT(min) OUT(max)
(1)
D(max)
IN(max)
) V
I
IN(max) Q
T
WARNING
where:
Figure 14. FLAG Monitor Circuit Waveform
V
V
I
is the maximum input voltage,
is the minimum output voltage,
IN(max)
OUT(min)
SETTING THE DELAY TIME
is the maximum output current for the
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
OUT(max)
application, and
I
I
is the quiescent current the regulator consumes at
Q
.
OUT(max)
[
C
+
]
(V * Reset Delay Low Voltage)
DELAY dt
t
Once the value of P
permissible value of R
is known, the maximum
DELAY
D(max)
Delay Charge Current
can be calculated:
qJA
Example:
Using C
T
150°C *
A
= 33 nF.
R
+
DELAY
(2)
qJA
P
D
Assume reset Delay Low Voltage = 0.
Use the typical value for V = 1.8 V.
The value of R
can then be compared with those in the
qJA
dt
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
Use the typical value for Delay Charge Current = 2.5 mA.
R
qJA
[
]
33 nF(1.8 * 0)
the die temperature below 150°C.
t
+
+ 23.8 ms
DELAY
2.5 mA
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
I
I
IN
OUT
SMART
REGULATOR
V
IN
V
OUT
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
Control
Features
}
I
Q
Figure 16. Single Output Regulator with Key
Performance Parameters Labeled
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8
NCV4279B
HEAT SINKS
where:
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
R
qJC
R
qCS
R
qSA
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
R
appears in the package section of the data sheet. Like
qJC
R
, it too is a function of package type. R
and R
are
qJA
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
determine the value of R
:
qJA
R
+ R
) R
) R
qSA
(3)
qJA
qJC
qCS
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9
NCV4279B
ORDERING INFORMATION
Device
Output Voltage
Package
Shipping
98 Units/Rail
NCV4279BD1
SO−8
SO−14
SO−20L
NCV4279BD1R2
NCV4279BD2
2500 Tape & Reel
55 Units/Rail
5.0 V
NCV4279BD2R2
NCV4279BDW
1000 Tape & Reel
37 Units/Rail
NCV4279BDWR2
1000 Tape & Reel
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10
NCV4279B
PACKAGE DIMENSIONS
SO−8
D SUFFIX
CASE 751−07
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
M
J
H
D
K
M
N
S
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
SO−14
D SUFFIX
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
0.337
0.150
0.054
0.014
0.016
−T−
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
A
0.25 (0.010)
T
B
K
M
P
R
_
_
_
_
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
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11
NCV4279B
PACKAGE DIMENSIONS
SO−20L
DW SUFFIX
CASE 751D−05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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