NCV7101SN1T1G [ONSEMI]
1.8 Volt Rail-to-Rail Operational Amplifier;
| 型号： | NCV7101SN1T1G |
| 厂家： | 
ONSEMI |
| 描述： | 1.8 Volt Rail-to-Rail Operational Amplifier |
| 文件： | 总16页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCS7101, NCV7101
1.8 Volt Rail-to-Rail
Operational Amplifier
The NCS7101 operational amplifier provides rail−to−rail operation
on both the input and output. The output can swing within 50 mV of
each rail. This rail−to−rail operation enables the user to make full use
of the entire supply voltage range available. It is designed to work at
very low supply voltages (1.8 V and ground), yet can operate with a
supply of up to 10 V and ground. The NCS7101 is available in the
space saving SOT−23−5 package with two industry standard pinouts.
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LOW VOLTAGE
RAIL−TO−RAIL
OPERATIONAL AMPLIFIER
Features
• Low Voltage, Single Supply Operation (1.8 V and Ground to 10 V
and Ground)
CASE 483
SOT−23−5
SN SUFFIX
5
• 1.0 pA Input Bias Current
1
• Unity Gain Bandwidth of 1.0 MHz at 5.0 V,
MARKING DIAGRAM
0.9 MHz at 1.8 V
x
= C for SN1
D for SN2
= Assembly Location
= Year
• Output Voltage Swings Within 50 mV of Both Rails @ 1.8 V
5
1
• No Phase Reversal on the Output for Over−Driven Input Signals
• Input Offset Trimmed to 1.0 mV
AAx AYWG
A
Y
G
W = Work Week
• Low Supply Current (I = 1.0 mA)
D
G
= Pb−Free Package
• Works Down to Two Discharged NiCd Battery Cells
• ESD Protected Inputs Up to 2.0 kV
(Note: Microdot may be in either location)
• These Devices are Pb−Free and are RoHS Compliant
• AEC−Q100 Qualified and PPAP Capable
PIN CONNECTIONS
1
2
3
5
V
V
EE
OUT
• *NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
V
CC
+ −
Non−Inverting
Inverting
Input
4
Input
Typical Applications
• Dual NiCd/NiMH Cell Powered Systems
• Portable Communication Devices
• Low Voltage Active Filters
• Power Supply Monitor and Control
• Interface to DSP
Style 1 Pin Out (SN1T1)
1
2
3
5
4
V
V
CC
OUT
V
EE
+ −
Non−Inverting
Inverting
Input
Input
Style 2 Pin Out (SN2T1)
Rail to Rail Input
Rail to Rail Output
ORDERING INFORMATION
†
Device
Package
Shipping
1.8 V
to
10 V
NCS7101SN1T1G
NCV7101SN1T1G*
+
-
SOT−23−5 3000 Tape & Reel
(Pb−Free) (7 inch Reel)
NCS7101SN2T1G
NCV7101SN2T1G*
This device contains 68 active transistors.
Figure 1. Typical Application
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011 − Rev. 4
NCS7101/D
NCS7101, NCV7101
MAXIMUM RATINGS
Rating
Symbol
Value
10
Unit
V
Supply Voltage (V to V
)
V
S
CC
EE
Input Differential Voltage Range (Note 1)
Input Common Mode Voltage Range (Note 1)
Output Short Circuit Duration (Note 2)
Junction Temperature
V
V
V
V
− 300 mV to 10 V
− 300 mV to 10 V
Indefinite
150
V
IDR
ICR
SC
EE
V
EE
t
sec
°C
T
J
Power Dissipation and Thermal Characteristics − SOT−23−5 Package
Thermal Resistance, Junction−to−Air
R
P
220
364
°C/W
mW
q
JA
Power Dissipation @ T = 70°C
A
D
Storage Temperature Range
T
−65 to +150
°C
°C
stg
Operating Ambient Temperature Range
NCS7101
NCV7101
T
−40 to +85
−40 to +125
A
ESD Protection at any Pin Human Body Model (Note 3)
V
ESD
2000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both inputs should not exceed the range of V − 300 mV to V + 10 V.
EE
EE
2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded.
T = T + (P R
)
q
JA
J
A
D
3. ESD data available upon request.
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2
NCS7101, NCV7101
DC ELECTRICAL CHARACTERISTICS
(V = 2.5 V, V = −2.5 V, V
= V = 0, R to GND, T = 25°C, unless otherwise noted.)
CC
EE
CM
O L A
Characteristics
Symbol
Min
Typ
Max
Unit
Input Offset Voltage
V
IO
mV
V
V
V
= 0.9 V, V = −0.9 V
CC
EE
T = 25°C
−7.0
−9.0
0.6
−
7.0
9.0
A
T = T
to T
High
A
Low
= 2.5 V, V = −2.5 V
CC
EE
T = 25°C
−7.0
−9.0
0.6
−
7.0
9.0
A
T = T
to T
High
A
Low
= 5.0 V, V = −5.0 V
CC
EE
T = 25°C
−7.0
−9.0
0.6
−
7.0
9.0
A
T = T
to T
High
A
Low
Input Offset Voltage Temperature Coefficient (R = 50)
DV /DT
−
8.0
−
mV/°C
S
IO
T = −40°C to 125°C
A
Input Bias Current (V = 1.8 V to 10 V)
|I |
−
1.0
−
pA
V
CC
IB
Common Mode Input Voltage Range
Large Signal Voltage Gain
V
ICR
V
EE
−
V
CC
A
VOL
kV/V
V
CC
= 5.0 V, V = −5.0 V
EE
R = 10 kW
R = 2.0 kW
L
16
16
50
30
−
−
L
Output Voltage Swing, High (V = "0.2 V)
V
OH
V
ID
V
V
V
= 0.9 V, V = −0.9 V (T = 25°C)
L
CC
R = 10 k
EE A
0.85
0.80
0.88
0.82
−
−
R = 2.0 k
L
T = T
to T
High
A
Low
R = 10 k
0.85
0.79
−
−
−
−
L
R = 2.0 k
L
= 2.5 V, V = −2.5 V (T = 25°C)
CC
EE
A
R = 600
2.10
2.35
2.21
2.44
−
−
L
R = 2.0 k
L
T = T
to T
High
A
Low
R = 600
2.00
2.40
−
−
−
−
L
R = 2.0 k
L
= 5.0 V, V = −5.0 V (T = 25°C)
CC
EE
A
R = 600
4.40
4.80
4.60
4.88
−
−
L
R = 2.0 k
L
T = T
to T
High
A
Low
R = 600
R = 2.0 k
L
4.40
4.80
−
−
−
−
L
Output Voltage Swing, Low (V = "0.2 V)
V
OL
V
ID
V
V
V
= 0.9 V, V = −0.9 V (T = 25°C)
L
CC
R = 10 k
EE A
−
−
−0.88
−0.82
−0.85
−0.80
R = 2.0 k
L
T = T
to T
High
A
Low
R = 10 k
−
−
−
−
−0.85
−0.78
L
R = 2.0 k
L
= 2.5 V, V = −2.5 V (T = 25°C)
CC
EE
A
R = 600
−
−
−2.22
−2.38
−2.10
−2.35
L
R = 2.0 k
L
T = T
to T
High
A
Low
R = 600
−
−
−
−
−2.00
−2.30
L
R = 2.0 k
L
= 5.0 V, V = −5.0 V (T = 25°C)
CC
EE
A
R = 600
−
−
−4.66
−4.88
−4.40
−4.80
L
R = 2.0 k
L
T = T
to T
High
A
Low
R = 600
R = 2.0 k
L
−
−
−
−
−4.35
−4.80
L
Common Mode Rejection Ratio
CMRR
dB
V
in
V
in
= 0 to 10 V
= 0 to 5.0 V
65
60
−
−
−
−
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3
NCS7101, NCV7101
DC ELECTRICAL CHARACTERISTICS (continued)
(V = 2.5 V, V = −2.5 V, V
= V = 0, R to GND, T = 25°C, unless otherwise noted.)
CC
EE
CM
O L A
Characteristics
Symbol
Min
Typ
Max
Unit
Power Supply Rejection Ratio
/V = 10 V/Ground, DV = 2.5 V
PSRR
65
−
−
dB
V
CC EE
S
Output Short Circuit Current (V Diff = "1.0 V)
I
mA
in
SC
V
V
V
= +0.9 V, V = −0.9 V
Source
Sink
CC
EE
−
−
3.0
−3.0
−
−
= +2.5 V, V = −2.5 V
CC
EE
Source
Sink
20
−60
25
−25
60
−20
= 5.0 V, V = −5.0 V
CC
EE
Source
Sink
50
−140
72
−72
140
−50
Power Supply Current (V = 0 V)
I
D
mA
O
V
V
V
= +0.9 V, V = −0.9 V
CC
EE
T = 25°C
−
−
−
0.97
−
−
1.20
1.30
1.60
A
T = −40°C to 85°C
A
T = −40°C to 125°C
A
= +2.5 V, V = −2.5 V
CC
EE
T = 25°C
−
−
−
1.05
−
−
1.30
1.40
1.70
A
T = −40°C to 85°C
A
T = −40°C to 125°C
A
= 5.0 V, V = −5.0 V
CC
EE
T = 25°C
−
−
−
1.13
−
−
1.40
1.50
1.80
A
T = −40°C to 85°C
A
T = −40°C to 125°C
A
AC ELECTRICAL CHARACTERISTICS
(V = 2.5 V, V = −2.5 V, V
= V = 0, R to GND, T = 25°C, unless otherwise noted.)
CC
EE
CM
O L A
Characteristics
Slew Rate (V = −2.0 to 2.0 V, R = 2.0 kW, A = 1.0)
Symbol
SR
Min
0.7
0.5
−
Typ
1.2
1.0
6.5
60
Max
3.0
3.0
−
Unit
V/ms
MHz
dB
O
L
V
Gain Bandwidth Product (V = 10 V)
GBW
Am
CC
Gain Margin (R = 10 k, C = 5.0 pF)
L
L
Phase Margin (R = 10 k, C = 5.0 pF)
φm
−
−
Deg
kHz
%
L
L
Power Bandwidth (V = 4.0 Vpp, R = 2.0 kW, THD v 1.0%)
BW
P
−
130
−
O
L
Total Harmonic Distortion (V = 4.0 Vpp, R = 2.0 kW, A = 1.0)
THD
O
L
V
f = 1.0 kHz
f = 10 kHz
−
−
0.02
0.2
−
−
Differential Input Resistance (V
= 0 V)
R
in
C
in
e
n
−
−
−
u1.0
2.0
−
−
−
tera W
pF
CM
Differential Input Capacitance (V
= 0 V)
CM
Equivalent Input Noise Voltage (Freq = 1.0 kHz)
140
nV/√Hz
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4
NCS7101, NCV7101
0
0
−400
V
CC
−0.4
V
CC
V
S
= 2.5 V
V
=
2.5 V
S
High State Output
Sourcing Current
−0.8 R = to GND
L
−800
R = to GND
T = 25°C
A
L
High State Output
Sourcing Current
T = 25°C
A
−1.2
−1200
1200
800
Low State Output
Sinking Current
1.2
0.8
Low State Output
Sinking Current
400
0
V
EE
0.4
0
V
EE
0
2.0
4.0
6.0
8.0
10
12
100
1.0 k
10 k
100 k
1.0 M
R , LOAD RESISTANCE (W)
L
I , LOAD CURRENT (mA)
L
Figure 2. Output Saturation Voltage versus
Load Resistance
Figure 3. Output Saturation Voltage versus
Load Current
1000
100
10
100
80
V = 5.0 V
S
R = 100 k
L
0
GAIN
T = 25°C
A
−20
60
−60
PHASE
1.0
0.1
0
40
−100
V = 2.5 V
S
R = ∞
L
20
0
C = 0
−140
−180
L
A = 1.0
V
0
25
50
75
100
125
1.0
10
100
1.0 k
10 k 100 k 1.0 M 10 M
T , AMBIENT TEMPERATURE (°C)
A
f, FREQUENCY (Hz)
Figure 4. Input Bias Current versus
Temperature
Figure 5. Gain and Phase versus Frequency
V
V
=
2.5 V
S
= 4.0 V
O
PP
R = 10 k
L
C = 10 pF
L
A = 1.0
V
T = 25°C
A
V
V
=
2.5 V
S
= 4.0 V
O
PP
R = 10 k
L
C = 10 pF
L
A = 1.0
V
T = 25°C
A
t, time (500 ns/Div)
t, time (1.0 ms/Div)
Figure 6. Transient Response
Figure 7. Slew Rate
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5
NCS7101, NCV7101
100
14
12
R = 10 k
L
90
80
70
60
50
40
30
20
10
A = 1.0
V
V
S
=
2.5 V
T = 25°C
A
R = ∞
V
=
5.0 V
L
S
10
T = 25°C
A
A = 1.0
V
8.0
6.0
V
V
=
=
2.5 V
0.9 V
S
4.0
2.0
0
S
0
−10
10
100
1.0 k
10 k
100 k
1.0 M
10 M
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 9. Common Mode Rejection versus
Frequency
Figure 8. Output Voltage versus Frequency
100
90
80
70
60
50
40
30
20
10
140
120
100
80
Output Pulsed Test
at 3% Duty Cycle
V
=
2.5 V
S
PSR+
R = ∞
L
T = 25°C
A
−40°C
A = 1.0
V
25°C
PSR−
60
85°C
40
20
0
0
−10
0
1.0
2.0
3.0
4.0
5.0
10
100
1.0 k
10 k
100 k
1.0 M 10 M
V , SUPPLY VOLTAGE (V)
S
f, FREQUENCY (Hz)
Figure 11. Output Short Circuit Sinking
Current versus Supply Voltage
Figure 10. Power Supply Rejection versus
Frequency
140
120
100
80
1.4
1.2
Output Pulsed Test
at 3% Duty Cycle
85°C
−40°C
25°C
1.0
0.8
25°C
−40°C
60
0.6
0.4
85°C
40
R = ∞
L
20
0
A = 1.0
0.2
0
V
V
in
= 0 V
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
3.0
4.0
5.0
V , SUPPLY VOLTAGE (V)
S
V , SUPPLY VOLTAGE (V)
S
Figure 12. Output Short Circuit Sourcing
Current versus Supply Voltage
Figure 13. Supply Current versus Supply
Voltage with No Load
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NCS7101, NCV7101
10
1.0
0.1
10
A = 1000
V
A = 1000
V
1.0
0.1
A = 100
V
A = 100
V
A = 10
V
A = 10
V
V
=
2.5 V
V
=
5.0 V
= 8.0 V
S
S
V
out
= 4.0 V
V
out
PP
PP
0.01
0.01
R = 2 k
R = 2 k
L
L
A = 1.0
V
T = 25°C
A
T = 25°C
A
A = 1.0
V
0.001
0.001
10
100
1.0 k
10 k
100 k
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 14. Total Harmonic Distortion versus
Frequency with 5.0 V Supply
Figure 15. Total Harmonic Distortion versus
Frequency with 10 V Supply
10
1.0
0.1
10
V
=
2.5 V
S
V
out
= 4.0 V
PP
R = 10 k
T = 25°C
A
L
1.0
0.1
A = 1000
V
A = 1000
V
A = 100
V
A = 100
V
A = 10
V
V
=
5.0 V
A = 10
V
S
0.01
0.01
V
out
= 8.0 V
PP
R = 10 k
L
T = 25°C
A = 1.0
A = 1.0
V
A
V
0.001
0.001
10
100
1.0 k
10 k
100 k
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 16. Total Harmonic Distortion versus
Frequency with 5.0 V Supply
Figure 17. Total Harmonic Distortion versus
Frequency with 10 V Supply
1.6
3.0
2.0
V
S
=
2.5 V
+Slew Rate, V
=
=
2.5 V
2.5 V
S
R = 10 k
L
C = 5.3 pF
L
1.2
0.8
−Slew Rate, V
S
R = 10 k
C = 10 pF
L
L
A = 1.0
V
T = 25°C
A
1.0
0
0.4
0
+Slew Rate, V
−Slew Rate, V
=
=
0.9 V
0.9 V
S
S
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 18. Slew Rate versus Temperature (Avg.)
Figure 19. Gain Bandwidth Product versus
Temperature
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NCS7101, NCV7101
50
40
30
20
10
0
20
80
70
60
50
40
30
20
80
70
Phase Margin
R = 10 k
L
−20
A = 100
V
T = 25°C
A
−60
60
50
40
30
20
V
=
2.5 V
−100
−140
−180
−220
S
R = 10 k
C = 10 pF
L
L
−10
Gain Margin
V
V
=
=
0.9 V
2.5 V
S
S
−20
−30
10
0
125
−260
−300
10
0
10 k
100 k
1.0 M
10 M
100 M
−50 −25
0
25
50
75
100
f, FREQUENCY (Hz)
T , AMBIENT TEMPERATURE (°C)
A
Figure 20. Voltage Gain and Phase versus
Frequency
Figure 21. Gain and Phase Margin versus
Temperature
70
100
80
60
40
20
0
100
70
V
=
2.5 V
S
60
50
40
30
20
Phase Margin
Gain Margin
80
60
40
20
60
50
40
30
R = 10 k
L
Phase Margin
A = 100
V
T = 25°C
A
V
= 2.5 V
R = 10 k
C = 5.0 pF
T = 25°C
S
0
20
L
Gain Margin
10
10
0
−20
−40
L
−20
−40
10
0
A
10
100
1.0 k
10 k
100 k 1.0M
1.0
100
1000
R , DIFFERENTIAL SOURCE RESISTANCE (W)
t
C , CAPACITIVE LOAD (pF)
L
Figure 22. Gain and Phase Margin versus
Differential Source Resistance
Figure 23. Gain and Phase Margin versus
Output Load Capacitance
12
80
70
60
50
40
30
20
Phase Margin
10
8.0
6.0
4.0
A = 100
V
R = 10 k
L
C = 0
L
T = 25°C
A
R = 10 k
L
A = 100
V
T = 25°C
A
Gain Margin
2.0
0
Split Supplies
10
0
0
2.0
V
4.0
6.0
8.0
10
0
1.0
2.0
3.0
4.0
5.0
V , SUPPLY VOLTAGE (V)
S
− V , SUPPLY VOLTAGE (V)
CC
EE
Figure 24. Output Voltage Swing versus
Supply Voltage
Figure 25. Gain and Phase Margin versus
Supply Voltage
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NCS7101, NCV7101
120
110
100
90
20
V
=
2.5 V
S
15
10
R = ∞
C = 0
L
L
A = 1.0
V
T = 25°C
A
5
0
R = 10 k
C = 0
L
L
−5
80
T = 25°C
A
−10
70
60
−15
−20
0
1.0
2.0
3.0
4.0
5.0
−3.0
−2.0
−1.0
, COMMON VOLTAGE RANGE (V)
CM
0
1.0
2.0
3.0
V , SUPPLY VOLTAGE (V)
V
S
Figure 26. Open Loop Voltage Gain versus
Supply Voltage (Split Supplies)
Figure 27. Input Offset Voltage versus Common
Mode Input Voltage Range, VS = + 2.5 V
20
15
10
5
6.0
4.0
2.0
V
=
0.9 V
S
R = ∞
C = 0
L
L
A = 1.0
V
T = 25°C
A
DV = 5.0 mV
IO
R = ∞
L
C = 0
L
0
0
A = 1.0
T = 25°C
A
V
−5
−10
−2.0
−4.0
−6.0
−15
−20
−1.0 −0.8 −0.6 −0.4 −0.2
0
0.2 0.4 0.6 0.8 1.0
0.5 1.0
2.0
3.0
4.0
5.0
V
CM
, COMMON MODE INPUT VOLTAGE (V)
V , SUPPLY VOLTAGE (V)
S
Figure 28. Input Offset Voltage versus Common
Figure 29. Common−Mode Input Voltage Range
Mode Input Voltage Range, VS = + 0.9 V
versus Power Supply Voltage
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9
NCS7101, NCV7101
APPLICATION INFORMATION AND OPERATING DESCRIPTION
C
GENERAL INFORMATION
fb
The NCS7101 is a rail−to−rail input, rail−to−rail output
operational amplifier that features guaranteed 1.8 volt
operation. This feature is achieved with the use of a modified
analog CMOS process that allows the implementation of
depletion MOSFET devices. The amplifier has a 1.0 MHz
gain bandwidth product, 1.2 V/ms slew rate and is
operational over a power supply range less than 1.8 V to as
high as 10 V.
R
fb
R
in
-
+
Input
Output
C
in
C
= Input and printed circuit board capacitance
in
Figure 30. Input Capacitance Pole Cancellation
Inputs
The input topology of this device series is unconventional
when compared to most low voltage operational amplifiers.
It consists of an N−channel depletion mode differential
transistor pair that drives a folded cascode stage and current
mirror. This configuration extends the input common mode
Output
The output stage consists of complementary P and N
channel devices connected to provide rail−to−rail output
drive. With a 2.0 k load, the output can swing within 100 mV
of either rail. It is also capable of supplying over 95 mA
when powered from 10 V and 3.0 mA when powered from
1.8 V.
voltage range to encompass the V and V power supply
EE
CC
rails, even when powered from a combined total of less than
1.8 volts. Figures 27 and 28 show the input common mode
voltage range versus power supply voltage.
The differential input stage is laser trimmed in order to
minimize offset voltage. The N−channel depletion mode
MOSFET input stage exhibits an extremely low input bias
current of less than 40 pA. The input bias current versus
temperature is shown in Figure 4. Either one or both inputs
When connected as a unity gain follower, the NCS7101
can directly drive capacitive loads in excess of 390 pF at
room temperature without oscillating but with significantly
reduced phase margin. The unity gain follower
configuration exhibits the highest bandwidth and is most
prone to oscillations when driving a high value capacitive
load. The capacitive load in combination with the
amplifier’s output impedance, creates a phase lag that can
result in an under−damped pulse response or a continuous
oscillation. Figure 32 shows the effect of driving a large
capacitive load in a voltage follower type of setup. When
driving capacitive loads exceeding 390 pF, it is
recommended to place a low value isolation resistor
between the output of the op amp and the load, as shown in
Figure 31. The series resistor isolates the capacitive load
from the output and enhances the phase margin. Refer to
Figure 33. Larger values of R will result in a cleaner output
waveform but excessively large values will degrade the
large signal rise and fall time and reduce the output’s
amplitude. Depending upon the capacitor characteristics,
the isolation resistor value will typically be between 50 to
500 ohms. The output drive capability for resistive and
capacitive loads is shown in Figures 2, 3, and 23.
can be biased as low as V minus 300 mV to as high as 10 V
EE
without causing damage to the device. If the input common
mode voltage range is exceeded, the output will not display
a phase reversal but it may latch in the appropriate high or
low state. The device can then be reset by removing and
reapplying power. If the maximum input positive or
negative voltage ratings are to be exceeded, a series resistor
must be used to limit the input current to less than 2.0 mA.
The ultra low input bias current of the NCS7101 allows
the use of extremely high value source and feedback resistor
without reducing the amplifier’s gain accuracy. These high
value resistors, in conjunction with the device input and
printed circuit board parasitic capacitances C , will add an
in
additional pole to the single pole amplifier shown in
Figure 30. If low enough in frequency, this additional pole
can reduce the phase margin and significantly increase the
output settling time. The effects of C , can be canceled by
in
placing a zero into the feedback loop. This is accomplished
R
+
Input
Output
with the addition of capacitor C . An approximate value for
fb
-
C
C
fb
can be calculated by:
L
R
C
in
fb
in
C
+
fb
R
Isolation resistor R = 50 to 500
Figure 31. Capacitance Load Isolation
Note that the lowest phase margin is observed at cold
temperature and low supply voltage.
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10
NCS7101, NCV7101
Figure 32. Small Signal Transient Response with Large Capacitive Load
Figure 33. Small Signal Transient Response with Large
Capacitive Load and Isolation Resistor.
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11
NCS7101, NCV7101
R
T
470 k
V
CC
Output Voltage
0
V
CC
0.67 V
C
CC
CC
Timing Capacitor
Voltage
T
1.0 nF
0.33 V
-
f
O
= 1.5 kHz
+
The non−inverting input threshold levels are set so that
the capacitor voltage oscillates between 1/3 and 2/3 of
R
470 k
1a
V
CC
. This requires the resistors R , R and R to be of
1a 1b 2
equal value. The following formula can be used to ap-
proximate the output frequency.
0.9 V
R
470 k
2
R
1b
470 k
1
f
+
O
1.39 RTCT
Figure 34. Square Wave Oscillator
D
1
1N4148
V
10 k
CC
cww
cw
Output Voltage
0
CC
CC
1.0 M
D
2
0.67 V
0.33 V
Timing Capacitor
Voltage
1N4148
10 k
Clock−wise, Low Duty Cycle
V
CC
C
T
V
CC
1.0 nF
Output Voltage
-
+
0
CC
CC
f
O
Timing Capacitor
Voltage
0.67 V
0.33 V
R
1a
470 k
Counter−Clock−wise, High Duty Cycle
V
CC
R
470 k
2
The timing capacitor C will charge through diode D and discharge
T
2
R
through diode D , allowing a variable duty cycle. The pulse width of the
1b
1
470 k
signal can be programmed by adjusting the value of the trimpot. The ca-
pacitor voltage will oscillate between 1/3 and 2/3 of V , since all the
CC
resistors at the non−inverting input are of equal value.
Figure 35. Variable Duty Cycle Pulse Generator
R
1
1.0 M
2.5 V
R
3
1.0 k
+
-
≈
10,000 mF
C
in
10 mF
−2.5 V
R
R
1
3
C
+
C
in
eff.
R
2
1.0 M
Figure 36. Positive Capacitance Multiplier
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12
NCS7101, NCV7101
A
f
C
f
400 pF
R
f
100 k
f
L
f
H
0.9 V
1
R
10 k
2
f +
[ 200 Hz
[ 4.0 kHz
L
2 p R C
1 1
-
V
O
1
+
f
+
V
in
H
2 p R C
f f
C
1
R
10 k
1
80 nF
−0.9 V
R
f
R
A + 1 )
+ 11
f
2
Figure 37. Voice Band Filter
V
supply
V
CC
V
in
V
+
-
in
I
+
sink
R
sense
R
sense
Figure 38. High Compliance Current Sink
I
s
V
L
5.0 V
1.0 W
R
1.0 k
3
R
sense
R
R
1.0 k
4
1
R
L
I
V
O
s
1.0 k
R
+
5
V
O
1.00 A
0.50 A
67.93 mV
78.67 mV
-
2.4 k
For best performance, use low
tolerance resistors.
R
2
3.3 k
Figure 39. High Side Current Sense
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13
NCS7101, NCV7101
k R
2
V
CC
k R
1
+
-
V
R
S
1
V
O
i
L
+
, Note that i is independent of R
L
L
R
1
V
S
R
2
i
L
R
L
Figure 40. Current Source
R
1
V
CC
i
S
-
+
V
O
V
O
= −i
R
1
S
Figure 41. Current to Voltage Converter
V
CC
i = 0
R
L
-
+
V
R
1
V
R
S
R1
1
V
O
i
+ i
+
+
R1
L
V
S
i
L
i
R
R1
1
Figure 42. Voltage to Current Converter
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14
NCS7101, NCV7101
R
2
V
CC
R
R
R
ƪR ) 1ƫ* V
4
2
2
1
2 ƪR ) R ƫ R
1
V
+ V
O
1
3
4
R
1
-
+
V
V
1
V
O
If R = R , and R = R , the equation simplifies to:
1
3
2
4
2
R
3
R
R
2
1
V
+ (V * V )
2 1
O
R
4
Figure 43. Differential Amplifier
R
4
R
1
V
CC
V
2
V
1
V
2
R
2
-
+
V
V
R
V
R
3
3
1
1
2
2
R
2 ƪ
R ƫ
V
O
V
+ * R
)
)
3
O
To minimize input offset current take:
R = R // R // R // R
R
5
5
1
2
3
4
Figure 44. Summing Amplifier
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15
NCS7101, NCV7101
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCS7101/D
相关型号：
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