NCV7310D [ONSEMI]
LINE TRANSCEIVER, PDSO8, SO-8;
| 型号： | NCV7310D |
| 厂家： | 
ONSEMI |
| 描述： | LINE TRANSCEIVER, PDSO8, SO-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7310
Single Wire LIN Transceiver
with Regulator Control
NCV7310 provides the physical interface for LIN (Local
Interconnect Network). The device works in cooperation with a
microprocessor providing serial data to a single wire network, and
receiving data over the same network. System design requires a
master/slave operation. The device is backward compatible with
ISO9141 while meeting the newer LIN objectives, including slew rate
control. Applications can be found in the industrial market as well as
the automotive market. This device includes an inhibit (INH) function
used to control an external voltage regulator.
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SO–8
D SUFFIX
CASE 751
Features
• Single–Wire Transceiver Compatible with the LIN Protocol
• Also Compatible with ISO 9141
• 20 kbit/s Operation
• Low Current Sleep Mode
PIN CONNECTION AND
MARKING DIAGRAM
• Short Circuit Protection
• Thermal Shutdown
• ESD to 4.0 kV All Pins
• Loss of Ground Does Not Affect Bus Activity
• Unpowered Node Does Not Affect Bus Activity
8
1
RxD
EN
INH
V
S
V
CC
Bus
GND
TxD
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
INH
EN
V
S
WW, W = Work Week
V
CC
V
2
S
ORDERING INFORMATION
State
Device
Package
Shipping
Control
NCV7310D
95 Units/Rail
SO–8
SO–8
RxD
BUS
GND
NCV7310DR2
2500 Tape & Reel
Drive
Current
Limit
TxD
Wave Shaper
Thermal
Shutdown
Figure 1. Block Diagram
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
November, 2001 – Rev. 5
NCV7310/D
NCV7310
V Power Up
S
Stand–By
EN = LOW
INH = HIGH
RxD = LOW(1), HIGH(3)
V
CC
= ON
Wake Up
t > t[wake]
EN goes high
Normal Mode
EN = HIGH
INH = HIGH
V
CC
= ON
EN goes high
= ON
V
CC
EN goes low
Sleep Mode
EN = LOW
INH = FLOATING
V
CC
= OFF(2)
1. After wake–up via bus.
2. ON when INH not used to control external voltage regulator.
3. After V power up.
S
Figure 2. State Diagram
MAXIMUM RATINGS*
Symbol
Rating
Value
–0.3 to 6.0
–0.3 to 40
–20 to 28
40
Unit
V
V
V
Logic Power Supply Voltage
Battery Supply Voltage
Bus Input Voltage
CC
S
V
Bus
Vdc
V
Bus
Bus Input Voltage (t < 1.0 ms)
Logic Input Voltage
INHIBIT
EN, TxD, RxD
INH
–0.3 to V + 0.3
V
CC
–0.3 to V + 0.3
V
S
ESD
ESD Discharge Susceptibility (Human Body Model)
Operating Junction Temperature
4.0
kV
°C
°C
T
J
–40 to 150
–55 to 150
Tstg
Storage Temperature Range
Package Thermal Resistance
Junction–to–Case
Junction–to–Ambient
R
R
45
165
°C/W
°C/W
θ
θ
JC
JA
*The maximum package power dissipation must be observed.
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2
NCV7310
ELECTRICAL CHARACTERISTICS (4.5 V ≤ V ≤ 5.5 V, 6.0 V ≤ V ≤ 20 V, R = 1.0 kΩ, EN = V ,
CC
CC
S
T
–40°C ≤ T ≤ 125°C; unless otherwise specified. Note 1. See Figures 4 and 5.)
J
Characteristic
Test Conditions
Min
Typ
2.0
Max
4.0
4.0
2.0
8.0
50
Unit
mA
mA
mA
mA
µA
V
I
Quiescent Current Recessive State
Quiescent Current Dominant State
TxD = V , Note 2.
–
CC
CC
I
TxD = 0 V, Note 2.
–
2.0
CC
I
S
Quiescent Current Recessive State
Quiescent Current Dominant State
TxD = V
–
1.0
CC
I
S
TxD = 0 V
–
6.0
Quiescent Current Sleep Mode
RxD High Level Output Voltage
RxD Low Level Output Voltage
V
S
≤ 12 V. Note 3.
–
0.8 × V
0
35
I
= –400 µA
= 400 µA
–
V
CC
RxD
RxD
CC
I
–
0.2 × V
V
CC
Receiver Threshold Voltage,
recessive to dominant edge
–
–
0.4 × V
0.46 × V
–
V
S
S
Receiver Threshold Voltage,
dominant to recessive edge
–
0.54 × V
0.08 × V
0.6 × V
V
S
S
Receiver Hysteresis
–
–
–
–
–
V
V
S
TxD High Level Threshold Voltage
0.5 × V
0.7 × V
CC
CC
+0.4 V
TxD Low Level Threshold Voltage
–
–
0.3 × V
0.5 × V
–0.4 V
–
–
CC
CC
TxD Hysteresis
–
800
–
–80
–
mV
µA
V
TxD Pull Up Current
TxD = 0 V
TxD = V
–150
0.8 × V
0
–100
Bus Recessive Output Voltage
Bus Dominant Output Voltage
Bus Short Circuit Current
Bus Leakage Current
V
S
CC
S
TxD = 0 V
–
0.2 × V
V
S
Bus = 13.5 V
40
70
110
mA
µA
V
CC
V
CC
= 0 V, V = 0 V, Bus = –12 V
= 0 V, V = 0 V, Bus = 20 V
–750
–
–350
0
–
5.0
S
S
Bus Pull Up Resistance
–
–
–
20
0.4 × V
–
30
–
47
kΩ
V
Bus Wake–up Threshold Voltage
EN High Level Threshold Voltage
0.7 × V
S
S
0.5 × V
0.7 × V
V
CC
CC
+0.4 V
EN Low Level Threshold Voltage
–
0.3 × V
0.5 × V
–
V
CC
CC
–0.4 V
EN Pull Down Resistance
–
15
–
30
60
kΩ
INH High Level Drop Voltage,
I
= –0.15 mA
0.05
0.5
V
INH
∆INH = V – INH
S
INH Leakage Current
Sleep Mode, INH = 0 V
–5.0
0
5.0
µA
1. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
2. Sum of current into V and EN pins.
CC
3. Sum of current into Bus and V pins. V = V
≤ 12 V, I = I + I
.
S
S
BUS
Q
S
BUS
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3
NCV7310
SWITCHING CHARACTERISTICS (4.5 V ≤ V ≤ 5.5 V, 6.0 V ≤ V ≤ 20 V, R = 1.0 kΩ, EN = V ,
CC
CC
S
T
–40°C ≤ T ≤ 125°C; unless otherwise specified. Note 4. See Figures 4 and 5.)
J
Characteristic
Test Conditions
80% to 20%, C = 3.3 nF,
Min
Typ
Max
Unit
Bus Falling Edge Slew Rate
–3.0
–2.0
–1.0
V/µs
Bus
V
CC
= 5.0 V, V = 13.5 V
s
Bus Rising Edge Slew Rate
20% to 80%, C
= 3.3 nF,
1.0
2.0
1.5
5.0
3.0
10
V/µs
µs
Bus
V
CC
= 5.0 V, V = 13.5 V
s
Propagation Delay, TxD Low to RxD
C
C
= 3.3 nF, C
V = 13.5 V
S
= 20 pF, V = 5.0 V,
CC
Bus
RxD
Low, t
d(L)TR
(Recessive to Dominant)
Propagation Delay, TxD High to RxD
= 3.3 nF, C
V = 13.5 V
S
= 20 pF, V = 5.0 V,
2.0
5.0
10
µs
Bus
RxD
CC
High, t
d(H)TR
(Dominant to Recessive)
Propagation Delay, TxD Low to Bus
C
C
C
C
= 3.3 nF, V = 5.0 V
–
–
–
–
1.0
1.0
1.0
1.0
4.0
4.0
4.0
4.0
µs
µs
µs
µs
Bus
Bus
Bus
Bus
CC
Low, t
d(L)T
Propagation Delay, TxD High to Bus
High, t
= 3.3 nF, V = 5.0 V
CC
d(H)T
Propagation Delay, Bus Dominant
(Low) to RxD Low, t
= 3.3 nF, C
= 3.3 nF, C
= 20 pF, V = 5.0 V
CC
RxD
RxD
d(L)R
Propagation Delay, Bus Recessive
(High) to RxD High, t
= 20 pF, V = 5.0 V
CC
d(H)R
Receiver Delay Symmetry
Transmitter Delay Symmetry
Wake–up Delay Time
–
–
–
–2.0
–2.0
30
–
–
2.0
2.0
110
µs
µs
µs
70
4. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
PIN FUNCTION DESCRIPTION
PACKAGE PIN #
8 Lead SOIC
PIN SYMBOL
FUNCTION
1
2
RxD
Receive data output. Transmit data also loops back on this pin.
EN
Enable input. Internal 30 kΩ pull down resistor. Transceiver
in normal mode when high.
3
4
5
6
V
5.0 V supply input.
CC
TxD
GND
Bus
Transmit data input. Internal pull up current source (100µA).
Ground.
Bus Input/Output. Internal pull up resistor (30 kΩ) through a
diode (protection when V is low).
S
7
8
V
Battery supply input.
S
INH
Inhibit Output. For use with external regulator. Goes high
with wakeup signal on Bus.
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4
NCV7310
V
BATT
LIN bus
Ground
NCV7310
RxD INH
EN
V
S
V
CC
Bus
TxD GND
1.0 k
Voltage
Regulator
Master Node
V
BATT
LIN bus
Ground
NCV7310
RxD INH
EN
V
S
V
CC
Bus
TxD GND
Voltage
Regulator
with ENABLE
Slave Node
Figure 3. Application Diagram
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5
NCV7310
RxD
V
CC
TxD EN
INH
V
S
BUS
NCV7310
1
4
8
RxD INH
R
T
EN
V
S
C
RXD
V
CC
BUS
C
5
BUS
TxD GND
47 nF
47 nF
Figure 4. Test Circuit
V
V
CC
TxD
GND
t
t
d(H)T
d(L)T
V
S
V
V
DR
RD
BUS
GND
t
t
d(H)R
d(L)R
V
CC
0.7 V
CC
RxD
0.3 V
CC
GND
t
t
t
d(H)TR
d(L)TR
Figure 5. Switching Characteristics Timing Diagram
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6
NCV7310
PACKAGE DIMENSIONS
SO–8
D SUFFIX
CASE 751–07
ISSUE V
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
G
MILLIMETERS
INCHES
DIM MIN
MAX
5.00
4.00
1.75
0.51
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
0.189
0.150
0.053
0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25
0.25
1.27
8
0.004
0.010
0.010
0.050
8
0.007
0.016
0
M
J
H
D
K
M
N
S
_
_
_
_
0.25
5.80
0.50
6.20
0.010
0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
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7
NCV7310
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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NCV7310/D
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