NCV7446MW0R2G [ONSEMI]
Dual CAN FD Transceiver, High Speed, Low Power;
| 型号： | NCV7446MW0R2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual CAN FD Transceiver, High Speed, Low Power 电信 光电二极管 电信集成电路 |
| 文件： | 总14页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual CAN FD Transceiver,
High Speed, Low Power
NCV7446
Description
NCV7446 is a dual CAN FD physical layer transceiver. It allows
interfacing of two independent CAN physical buses and two
independent CAN protocol controllers. The transceivers provide
differential transmit capability to the bus and differential receive
capability to the CAN controllers.
It is consisted of two fully independent NCV7344 transceivers. The
NCV7446 guarantees additional timing parameters to ensure robust
communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7446 an excellent choice for all types of HS−CAN networks, in
nodes that require a low−power mode with wake−up capability via the
CAN bus.
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MARKING
DIAGRAM
NV74
46−0
ALYW
G
1
DFNW14
CASE 507AC
Features
NV7446−0 = Specific Device Code
A
L
Y
W
G
= Assembly Site
= Wafer Lot
= Year of Production, Last Number
= Work Week Number
= Pb−Free Package
• Compliant with the ISO 11898−2:2016
• CAN FD Timing Specified up to 5 Mbps
• Very Low Current Standby Mode with Wake−up via the Bus
• Low Electromagnetic Emission (EME) and High Electromagnetic
Immunity
• No Disturbance of the Bus Lines with an Un−powered Node
PIN CONNECTIONS
• Transmit Data (TxD) Dominant Timeout Function
• Under All Supply Conditions the Chip Behaves Predictably
• Very High ESD Robustness of Bus Pins
• Thermal Protection
• Bus Pins Short Circuit Proof to Supply Voltage and Ground
• Bus Pins Protected Against Transients in an Automotive
Environment
TxD1
1
2
3
4
5
6
7
14
13
12
11
10
9
STB1
GND1
VCC1
RxD1
TxD2
CANH1
CANL1
STB2
CANH2
CANL2
RxD2
GND2
VCC2
Quality
8
• Wettable Flank Package for Enhanced Optical Inspection
• AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 12 of this data sheet.
Compliant
Typical Applications
• Automotive
• Industrial Networks
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
December, 2019 − Rev. 2
NCV7446/D
NCV7446
BLOCK DIAGRAM
VCC1
3
VCC1
NCV7446
13
Thermal
CANH1
CANL1
shutdown
1
TxD1
STB1
Timer
VCC1
Mode &
12
Driver control
14
Wake −up
control
4
2
Wake −up
RxD1
COMP
Filter
GND1
COMP
Channel1
11
STB2
TxD2
5
6
CANH2
CANL2
10
9
GND2
VCC2
Channel2
7
8
RxD2
Figure 1. NCV7446 Block Diagram
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2
NCV7446
TYPICAL APPLICATION DIAGRAM
VBAT
IN
OUT
5V −reg
VCC
VCC1
VCC2
3
7
13
STB1
TxD1
RxD1
14
1
CANH1
CAN
BUS
4
CANL1
CANH2
Micro−
12
10
.
controller
STB2
TxD2
RxD2
11
5
CAN
BUS
8
CANL2
9
2
6
GND1 GND2
GND
Figure 2. NCV7446 Application Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin Number
Pin Name
TxD1
Description
1
2
Transmit data input for channel 1; low input Ù dominant driver; internal pull−up current
Ground for channel 1
GND1
3
V
CC1
Supply voltage for channel 1
4
RxD1
TxD2
GND2
Receive data output for channel 1; dominant transmitter Ù low output
Transmit data input for channel 2; low input Ù dominant driver; internal pull−up current
Ground for channel 2
5
6
7
V
CC2
Supply voltage for channel 2
8
RxD2
CANL2
Receive data output for channel 2; dominant transmitter Ù low output
Low−level CAN bus line channel 2 (low in dominant mode)
High−level CAN bus line channel 2 (high in dominant mode)
Standby mode control input for channel 2; internal pull−up current
Low−level CAN bus line channel 1 (low in dominant mode)
High−level CAN bus line channel 1 (high in dominant mode)
Standby mode control input for channel 1; internal pull−up current
Recommended to connect to GND or left floating in application
9
10
11
12
13
14
EP
CANH2
STB2
CANL1
CANH1
STB1
Exposed Pad
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NCV7446
FUNCTIONAL DESCRIPTION
Standby Mode
Operating Modes
NCV7446 provides two modes of operation per
transceiver as illustrated in Table 2. These modes are
selectable through pins STB1 and STB2 independently for
each transceiver.
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are biased to ground and supply current is reduced to a
minimum. When a wake−up request is detected by the
low−power differential receiver, the signal is first filtered
and then verified as a valid wake signal after a time period of
twake_filt, the corresponding RxDx pin is driven low by the
transceiver (following the bus) to inform the controller of
the wake−up request.
Table 2. OPERATING MODES
Pins
Mode
Pins RxDx
STBx
Low when bus
dominant
High when bus
recessive
Low
Normal
Follows the bus
when wake−up
detected
High when no
wake−up re-
Wake−up
High
Standby
quest detected
When a valid wake−up pattern (phase in order
dominant − recessive − dominant) is detected during the
standby mode the RxDx pins follows the bus. Minimum
length of each phase is t
Pattern must be received within t
Normal Mode
– see Figure 3.
wake_filt
In the normal mode, the selected transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxDx and
RxDx. The slopes on the bus lines outputs are optimized to
give low EME.
to be recognized
wake_to
as valid wake−up otherwise internal logic is reset.
twake_filt
twake_filt
twake_filt
CANHx
CANLx
< twake_to
tdwakerd tdwakedr
RxDx
Figure 3. NCV7446 Wake−up behavior
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NCV7446
Overtemperature Detection
This TxD dominant timeout time t
defines
dom(TxD)
the minimum possible bit rate to 17 kbps.
A thermal protection circuit protects the IC from damage
by switching off the affected transmitter if the junction
temperature exceeds a value of approximately 170°C.
Because the transmitter dissipates most of the power, the
power dissipation and temperature of the IC is reduced. All
other IC functions continue to operate. The transmitter
off−state resets when the temperature decreases below
the shutdown threshold and pins TxDx goes high.
The thermal protection circuit is particularly needed when
a bus line short circuits.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Undervoltage on V
or V
pins prevents the chip
CC2
CC1
sending data on the bus when there is not enough V supply
voltage.
CC
After supply is recovered, corresponding TxD pin must be
first released to high to allow sending dominant bits again.
Recovery time from undervoltage detection is equal to
td(stb−nm) time.
The pins CANHx and CANLx are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxDx and STBx are pulled high internally
should the input become disconnected. Pins TxDx, STBx
and RxDx will be floating, preventing reverse supply should
the adjacent VCCx supply be removed.
TxDx Dominant Timeout Function
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pins TxDx are forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pins
TxDx. If the duration of the low−level on pins TxDx exceeds
the internal timer value t
, the transmitter is
dom(TxD)
disabled, driving the bus into a recessive state. The timer is
reset by a positive edge on pins TxDx.
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NCV7446
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GNDx (pin 2 or pin 6).
Positive currents flow into the IC. Sinking current means the
current is flowing into the pin; sourcing current means the
current is flowing out of the pin.
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
−0.3
−42
−42
−42
Max
+6
Unit
V
V
SUP
Supply voltage V
V
CC1, CC2
V
CANH
DC voltage at pins CANHx
DC voltage at pins CANLx
0 < V
0 < V
< 5.25 V; no time limit
< 5.25 V; no time limit
+42
+42
+42
V
CCX
V
V
CANL
CANH−CANL
CCX
V
DC voltage between any two pins
(including CANHx and CANLx)
V
V
DC Voltage at pins TxDx, STBx
DC Voltage at pin RxDx
−0.3
−0.3
−8
+6
V
V
IN
V
OUT
V
+ 0.3
CCx
V
Electrostatic discharge voltage at all pins,
Component HBM
(Note 1)
(Note 2)
+8
kV
esdHBM
V
Electrostatic discharge voltage at all pins,
Component CDM
−750
+750
V
esdCDM
V
Electrostatic discharge voltage at pins CANHx
and CANLx, System HBM (Note 4)
Without bus filter (Note 3)
With bus filter (Note 3)
test pulses 1
−7
−11
+7
kV
kV
V
esdIEC
+11
V
Voltage transients, pins CANHx, CANLx.
According to ISO7637−3, Class C (Note 4)
−100
schaff
test pulses 2a
+75
V
test pulses 3a
−150
V
test pulses 3b
+100
150
V
Latch−up
Static latch−up at all pins
(Note 5)
mA
°C
°C
−
T
stg
Storage temperature
−55
−40
+150
+170
T
Maximum junction temperature
Moisture Sensitivity Level
J
MSL
1
T
SLD
Lead temperature Soldering − Reflow (Note 11)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011.
3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330 W resistor referenced to GNDx.
4. Results were verified by external test house.
5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
6. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 4. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
101
53
Unit
K/W
K/W
K/W
K/W
R
Thermal Resistance Junction−to−Air, JEDEC 1S0P PCB
Thermal Resistance Junction−to−Air, JEDEC 2S2P PCB
Thermal Resistance Junction−to−Air
Free air; (Note 8)
Free air; (Note 9)
Free air; (Note 10)
Free air; (Note 11)
q
q
q
q
JA_1
JA_2
JA_3
JA_4
R
R
R
76
Thermal Resistance Junction−to−Air
46
7. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
8. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
9. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
10.Test board according to EIA/JEDEC Standard JESD51−3 and JESD51−5 , signal layer with 10% trace coverage and with thermal via array
under the exposed pad connected to the second copper layer.
11. Test board according to EIA/JEDEC Standard JESD51−5 and JESD51−7, signal layers with 10% trace coverage and thermal via array under
the exposed pad connected to the first inner copper layer.
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NCV7446
Table 5. ELECTRICAL CHARACTERISTICS
V
V
= 4.75 V to 5.25 V; T = −40°C to +150°C; R = 60 W, C = 100 pF, C not used, C
= 15 pF, unless specified otherwise.
CC1, CC2
J
LT
LT
1
RxD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY (PINS V
)
CCX
V
Power supply voltage
(Note 12)
4.75
20
5.0
45
5.0
−
5.25
55
V
CCx
CCx
I
Supply current on single channel
Dominant; V
= Low
= Low
mA
mA
mA
TxDx
Recessive; V
1.9
2.0
10
TxDx
Normal mode, Dominant;
= 0 V; one of bus wires
105
V
TxDx
shorted; −3 V ≤ (V
,
CANHx
V
CANLx
) ≤ +18 V
I
Supply current in standby mode on
single channel
T ≤ 100°C, (Note 13)
J
−
10
15
mA
CCSx
V
Standby undervoltage detection V
pins
3.5
2.0
4.0
2.3
4.3
2.6
V
V
UVD(VCC)(stby)
CCx
V
Switch−off undervoltage detection V
pins
CCx
UVD(VCC)(swoff)
TRANSMITTER DATA INPUT (Pins TxDx)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Output recessive
Output dominant
2.0
−
−
−
−
V
IH
V
+0.8
+5.0
−70
10
V
IL
I
IH
V
TxDx
V
TxDx
= V
CCx
−5.0
−300
−
0
mA
mA
pF
I
IL
= 0 V
−150
5
C
(Note 13)
i
TRANSMITTER MODE SELECT (Pins STBx)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Standby mode
Normal mode
2.0
−
−
−
0
−
5
−
V
IH
V
+0.8
+1.0
−1.0
10
V
IL
I
IH
V
STBx
V
STBx
= V
CCx
−1.0
−15
−
mA
mA
pF
I
IL
= 0 V
C
(Note 13)
i
RECEIVER DATA OUTPUT (Pins RxDx)
I
High−level output current
Normal mode
−8.0
−3.0
−1.0
mA
mA
OH
V
= V
– 0.4 V
RxDx
CCx
I
Low−level output current
V
RxDx
= 0.4 V
1.0
6.0
12
OL
BUS LINES (Pins CANHx and CANLx)
I
Recessive output current at pins
CANHx and CANLx
−27 V < V
, V <
CANLx
−5.0
−5.0
2.0
−
0
+5.0
+5.0
3.0
mA
mA
V
o(rec)
CANHx
+32 V; Normal mode
I
LI
Input leakage current
0 W < R(V
to GNDx) <
CCx
1 MW; V
= V
= 5 V
CANLx
CANHx
V
Recessive output voltage at pins CANHx
Recessive output voltage at pins CANLx
Recessive output voltage at pin CANHx
Recessive output voltage at pin CANLx
Normal mode, V
= High;
2.5
2.5
−
o(rec)(CANH)
TxDx
R
and C not used
LT
LT
V
Normal mode, V
= High;
2.0
3.0
V
o(rec)(CANL)
TxDx
R
and C not used
LT
LT
V
Standby mode; R and C
not used
−0.1
−0.1
−0.2
2.75
0.5
+0.1
+0.1
+0.2
4.5
V
o(off)(CANH)
LT
LT
LT
LT
V
Standby mode; R and C
not used
−
V
o(off)(CANL)
LT
V
Differential bus output voltage
Standby mode; R and C
not used
−
V
o(off)(CANL)
LT
(VCANHx * VCANLx)
V
Dominant output voltage at pins CANHx
V
= 0 V; t < tdom(TxD);
3.5
1.5
V
o(dom)(CANH)
TxDx
50 W < R < 65 W
LT
= 0 V; t < tdom(TxD);
TxDx
V
Dominant output voltage at pins CANLx
V
2.25
V
o(dom)(CANL)
50 W < R < 65 W
LT
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NCV7446
Table 5. ELECTRICAL CHARACTERISTICS
V
V
= 4.75 V to 5.25 V; T = −40°C to +150°C; R = 60 W, C = 100 pF, C not used, C
= 15 pF, unless specified otherwise.
CC1, CC2
J
LT
LT
1
RxD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BUS LINES (Pins CANHx and CANLx)
V
Differential bus output voltage
V
= 0 V; dominant;
LT
1.5
−50
1.5
0.9
2.25
0
3.0
+50
5.0
1.1
V
mV
V
o(dom)(diff)
TxDx
(V − V
)
45 W < R < 65 W
CANHx
CANLx
V
Differential bus output voltage
(V − V
V
= High; recessive; no
o(rec)(diff)
TxDx
)
CANLx
load
CANHx
V
Differential bus output voltage during
arbitration (V − V
R
2.24kW (Note 13)
LT =
−
o(dom)(diff)_arb
)
CANLx
CANHx
V
Dominant output voltage driver symmetry
(VCANHx + VCANLx)
RLT = 60W; C1 = 4.7 nF; C
not used; TxDx = square
wave up to 1 MHz
1.0
VCCx
o(dom)(sym)
LT
I
Short circuit output current at pins CANHx
Short circuit output current at pins CANLx
−3 V < V
−3 V < V
< +18 V
< +36 V
−100
−1.5
−3.0
−
−
−
1.5
100
0.5
mA
mA
V
o(sc)(CANH)
CANHx
CANLx
I
o(sc)(CANL)
V
Differential input voltage range recessive
state
Normal mode;
i(rec)(diff)_NM
−12 V ≤ V
,
CANHx
V
CANLx
≤ +12 V; no load
V
Standby mode;
−12 V ≤ V
CANLx
−3.0
0.9
0.4
8.0
8.0
V
V
V
i(rec)(diff)_LP
,
CANHx
V
≤ +12 V; no load
V
Differential input voltage range dominant
state
Normal mode;
−
i(dom)(diff)_NM
−12 V ≤ V
CANLx
,
CANHx
V
≤ +12 V; no load
V
Standby mode;
−12 V ≤ V
1.05
i(dom)(diff)_LP
,
CANHx
≤ +12 V; no load
V
CANLx
V
Differential receiver threshold voltage in
normal mode
−12 V ≤ V
−12 V ≤ V
≤ +12 V;
≤ +12 V
0.5
0.4
0.4
15
−
−
0.9
1.0
1.05
37
V
V
i(diff)(th)_NORM
CANLx
CANHx
V
Differential receiver threshold voltage in
normal mode, extended range
−30 V < V
−30 V < V
< +35 V;
< +35 V
i(diff)(th)_NORM_H
CANLx
CANHx
V
Differential receiver threshold voltage in
standby mode
−12 V ≤ V
−12 V ≤ V
≤ +12 V;
≤ +12 V
−
V
i(diff)(th)_STDBY
CANLx
CANHx
R
Common−mode input resistance at pin
CANHx
−2 V ≤ V
−2 V ≤ V
≤ +7 V;
≤ +7 V
26
26
0
kW
kW
%
i(cm)(CANH)
CANLx
CANHx
R
Common−mode input resistance at pin
CANLx
−2 V ≤ V
−2 V ≤ V
≤ +7 V;
≤ +7 V
15
37
i(cm)(CANL)
CANLx
CANHx
R
Matching between pin CANHx and pin
CANLx common mode input resistance
V
= V = +5 V
CANLx
−1
25
+1
i(cm)(m)
CANHx
R
Differential input resistance
−2 V ≤ V
−2 V ≤ V
≤ +7 V;
≤ +7 V
50
75
kW
i(diff)
CANLx
CANHx
C
Input capacitance at pins CANHx
Input capacitance at pins CANLx
Differential input capacitance
V
TxDx
V
TxDx
V
TxDx
= High; (Note 13)
= High; (Note 13)
= High; (Note 13)
−
−
−
4.5
4.5
20
20
10
pF
pF
pF
i(CANH)
C
i(CANL)
C
3.75
i(diff)
THERMAL SHUTDOWN
Shutdown junction temperature per channel
TIMING CHARACTERISTICS (see Figure 4 and Figure 6)
T
J(sd)
Junction temperature rising
160
180
200
°C
t
t
Delay TxDx to bus active
Delay TxDx to bus inactive
Delay bus active to RxDx
Delay bus inactive to RxDx
−
−
75
85
−
−
ns
ns
ns
ns
ns
d(TxD−BUSon)
d(TxD−BUSoff)
d(BUSon−RxD)
d(BUSoff−RxD)
t
t
−
24
−
−
32
−
t
Propagation delay TxDx to RxDx
dominant to recessive transition
50
100
210
pd_dr
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NCV7446
Table 5. ELECTRICAL CHARACTERISTICS
V
V
= 4.75 V to 5.25 V; T = −40°C to +150°C; R = 60 W, C = 100 pF, C not used, C
= 15 pF, unless specified otherwise.
CC1, CC2
J
LT
LT
1
RxD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TIMING CHARACTERISTICS (see Figure 4 and Figure 6)
t
Propagation delay TxDx to RxDx
recessive to dominant transition
50
120
210
ns
pd_rd
t
Delay standby mode to normal mode
5.0
0.5
0.5
11
−
20
5.0
6.0
ms
ms
ms
d(stb−nm)
t
Dominant time for wake−up via bus
wake_filt
t
Delay to flag wake event
(recessive to dominant transitions)
Valid bus wake−up event
Valid bus wake−up event
Standby mode
2.6
dwakerd
t
Delay to flag wake event
(dominant to recessive transitions)
0.5
2.6
6.0
ms
dwakedr
t
Bus time for wake−up timeout
TxDx dominant time for timeout
Bit time on RxDx pin
1.0
1.0
−
−
−
−
10
10
ms
ms
ns
wake_to
t
V
TxDx
= 0 V; Normal mode
dom(TxD)
t
t
t
t
= 500 ns
= 200 ns
= 500 ns
400
120
435
550
220
530
Bit(RxD)
Bit(TxD)
Bit(TxD)
Bit(TxD)
ns
t
Bit time on bus (CANHx – CANLx pin)
ns
Bit(Vi(diff))
−
t
= 200 ns
155
210
ns
Bit(TxD)
−
−
−
Dt
Rec
Receiver timing symmetry
Rec = Bit(RxD) − Bit(Vi(diff))
t
t
= 500 ns
= 200 ns
−65
−45
+40
+15
ns
ns
Bit(TxD)
Dt
t
t
;
Bit(TxD)
12.In the range of 4.5 V to 4.75 V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.
13.Values based on design and characterization, not tested in production.
MEASUREMENT SETUPS AND DEFINITIONS
0.7 × V
IO
1
TxDx
0.3 × V
0.3 × V
IO
IO
tpd_rd
tbit(TxD)
td(TxD−BUSon)
5 × t
bit(TxD)
td(BUSon−RxD)
900 mV
Vi(diff)= VCANHx −VCANLx
500 mV
tbit(Vi(diff))
td(BUSoff−RxD)
td(TxD−BUSoff)
tpd_dr
0.7 × V
IO
RxDx
0.3 × V
IO
1
TxDx Edge length below 10 ns
tbit(RxD)
Figure 4. Transceiver Timing Diagram
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9
NCV7446
+5 V
100 nF
VCC1
VCC2
3
5
CANH1
1 nF
13
TxD1
TxD2
1
5
Transient
Generator
RxD1
1 nF
4
12
NCV7446
CANL1
CANH2
1 nF
15 pF
15 pF
10
RxD2
Transient
Generator
8
1 nF
9
6
CANL2
14
11
2
STB1 STB2 GND1 GND2
Figure 5. Test Circuit for Automotive Transients
+5 V
100 nF
VCC1
VCC2
3
5
CANH1
13
TxD1
TxD2
RLT /2
4.7 nF
1
5
CLT
100 pF
C1
RxD1
RLT /2
4
12
10
NCV7446
CANL1
2x 30 W
CANH2
15 pF
15 pF
RLT /2
4.7 nF
CLT
RxD2
8
100 pF
C1
RLT /2
9
6
CANL2
2x 30 W
14
11
2
STB1 STB2 GND1 GND2
Figure 6. Test Circuit for Timing Characteristics
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10
NCV7446
Table 6. ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE
ISO 11898−2:2016 Specification
NCV7446 Datasheet
Symbol
Parameter
Notation
Dominant output characteristics
Single ended voltage on CAN_H
V
V
o(dom)(CANH)
CAN_H
Single ended voltage on CAN_L
V
CAN_L
V
o(dom)(CANL)
Differential voltage on normal bus load
Differential voltage on effective resistance during arbitration
Differential voltage on extended bus load range (optional)
Driver symmetry
V
Diff
V
Diff
V
Diff
V
o(dom)(diff)
V
o(dom)(diff)_arb
V
o(dom)(diff)
Driver symmetry
V
V
SYM
o(dom)(sym)
I
o(SC)(CANH)
Driver output current
Absolute current on CAN_H
I
CAN_H
Absolute current on CAN_L
I
I
o(SC)(CANL)
CAN_L
Receiver output characteristics, bus biasing active
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
V
V
o(rec)(CANH)
CAN_H
V
V
o(rec)(CANL)
CAN_L
V
Diff
V
o(rec)(diff)
Receiver output characteristics, bus biasing inactive
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
V
V
o(off)(CANH)
CAN_H
V
V
o(off)(CANL)
CAN_L
V
Diff
V
o(off)(dif)
Optional transmit dominant timeout
Transmit dominant timeout, long
t
t
t
dom(TxD)
dom
Transmit dominant timeout, short
NA
dom
Static receiver input characteristics, bus biasing active
Recessive state differential input voltage range
Dominant state differential input voltage range
Static receiver input characteristics, bus biasing inactive
Recessive state differential input voltage range
Dominant state differential input voltage range
Receiver input resistance
V
V
V
i(rec)(diff)_NM
Diff
V
Diff
i(dom)(diff)_NM
V
V
V
Diff
i(rec)(diff)_LP
V
Diff
i(dom)(diff)_LP
Differential internal resistance
R
R
Diff
i(diff)
R
i(cm)(CANH)
Single ended internal resistance
R
CAN_H
R
R
CAN_L
i(cm)(CANL)
Receiver input resistance matching
Matching a of internal resistance
Implementation loop delay requirement
Loop delay
m
R
i(cm)(m)
R
t
t
Loop
pd_rd
pd_dr
t
Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s
Received recessive bit width @ 2 Mbit/s
Receiver timing symmetry @ 2 Mbit/s
t
t
Bit(Vi(diff))
Bit(Bus)
t
t
Bit(RxD)
Bit(RXD)
Dt
Rec
D
tRec
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11
NCV7446
Table 6. ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE
ISO 11898−2:2016 Specification
NCV7446 Datasheet
Symbol
Parameter
Notation
Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s
Transmitted recessive bit width @ 5 Mbit/s
Transmitted recessive bit width @ 5 Mbit/s
Received recessive bit width @ 5 Mbit/s
t
t
Bit(Vi(diff))
Bit(Bus)
t
t
Bit(RxD)
Bit(RXD)
Dt
Rec
Dt
Rec
Maximum ratings of V
, V and V
CAN_L Diff
CAN_H
Maximum rating V
V
Diff
V
CANH−CANL
Diff
General maximum rating V
and V
V
V
CANH
CAN_H
CAN_L
CAN_H
V
CAN_L
V
CANL
Optional: Extended maximum rating V
and V
V
NA
CAN_H
CAN_L
CAN_H
V
CAN_L
Maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
I
I
LI
CAN_H
CAN_L
I
Bus biasing control timings
CAN activity filter time, long
t
t
t
wake_filt
Filter
CAN activity filter time, short
NA
Filter
Wake−up timeout, short
t
t
NA
Wake
Wake
Wake−up timeout, long
t
wake_to
Timeout for bus inactivity (Required for selective wake−up implementation only)
Bus Bias reaction time (Required for selective wake−up implementation only)
t
NA
Silence
t
NA
Bias
ORDERING INFORMATION
†
Device
Description
Package
Shipping
NCV7446MW0R2G
Dual CAN FD Transceiver, High Speed, Low Power
DFNW14
(Pb−Free)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW14 4.5x3, 0.65P
CASE 507AC
ISSUE D
1
DATE 03 JUL 2018
SCALE 2:1
NOTES:
L3
L3
A B
D
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMESNION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURES TO AID IN FILLET FOR-
MATION ON THE LEADS DURING MOUNTING.
L
L
DETAIL A
PIN ONE
REFERENCE
ALTERNATE
CONSTRUCTION
E
EXPOSED
COPPER
MILLIMETERS
TOP VIEW
DIM MIN
NOM
0.85
−−−
MAX
0.90
0.05
A
A1
A3
A4
b
D
D2
E
E2
e
K
L
L3
0.80
−−−
A
DETAIL B
0.10
C
C
0.20 REF
−−−
0.30
4.50
4.20
PLATING
A1
A4
0.10
0.25
4.40
4.13
2.90
1.53
−−−
0.35
4.60
4.27
3.10
1.67
C
C
DETAIL B
A4
0.08
SEATING
PLANE
A3
NOTE 4
C
3.00
1.60
SIDE VIEW
0.65 BSC
0.30 REF
0.40
DETAIL A
0.35
0.00
0.45
0.10
D2
L3
0.05
PLATED
SURFACES
14X
L
1
7
SECTION C−C
GENERIC
MARKING DIAGRAM*
E2
XXXXX
XXXXX
AYWWG
G
8
14
K
14X b
0.10
0.05
e
M
M
C A B
NOTE 3
C
BOTTOM VIEW
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
RECOMMENDED
SOLDERING FOOTPRINT*
WW
G
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
14X
4.35
4.23
0.75
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present. Some products may
not follow the Generic Marking.
14
8
7
3.60 1.75
PACKAGE
OUTLINE
1
0.65
PITCH
14X
0.33
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14979G
DFNW14 4.5x3, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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