NCV7684DQR2G_技术文档

NCV7684

12 Channels 60 mA LED

Linear Current Driver I²C

Controllable for Automotive

Applications

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The NCV7684 consists of twelve linear programmable constant

current sources. The part is designed for use in the regulation and

control of LED for automotive applications. The NCV7684 allows

128 different current levels adjustable with pulse width modulation

2

(PWM) programmable via I C serial interface. The device can be used

SSOP24 NB EP

CASE 940AP

2

with micro−controller applications using the I C bus or in stand−alone

applications where a choice could be done in between 2 different

configuration settings. The IC also provides 3.3 V voltage reference to

the application for loads up to 1 mA.

MARKING DIAGRAM

LED brightness level is easily programmed using an external

resistor. Each channel has an internal circuitry to detect open−load

conditions with an optional auto−recovery mode. If one driver is in

open−load condition, all other channels could be turned off according

to the programmable bit setting.

XXXXXXXXXG

AWLYYWW

The device is available in small body size SSOP24−EP package.

XXXX = Specific Device Code

Features

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

• 12 programmable Current Sources Up to 60 mA

2

• Common PWM Gain Control via I C

• On−chip 125, 250, or 500 Hz PWM

• Open LED String Diagnostic

(Note: Microdot may be in either location)

• Low Dropout Operation for Pre−Regulator Applications

• Single Resistor for Current Set Point

• Voltage Reference 3.3 V / 1 mA

ORDERING INFORMATION

Device

Package

Shipping†

2

• 8 bits I C Interface with CRC8 Error Detection

• OTP Bank for Stand−Alone Operation (2 Configurations)

• Detection and Protection Against Open Load and Under−Voltage

• Over Temperature Detection and Protection

• Low Emission with Spread Spectrum Oscillator

• AEC Q100 Qualified

NCV7684DQR2G SSOP24−EP

(Pb−Free)

2500 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

• SSOP24−EP Packaging

• This is a Pb−Free Device

Applications

• Dashboard Applications

• Rear Combination Lamps (RCL)

• Daytime Running Lights (DRL)

• Fog Lights

• Center High Mounted Stop Lamps (CHMSL) Arrays

• Turn Signal and other Externally Modulated Applications

1

Publication Order Number:

September, 2017 − Rev. 0

NCV7684/D

NCV7684

OUT1

OUT12

VS

ctrl

SET

I

SET

Voltage

Reference

VCC

VDD

I

SET

2

I C

CSN

SCL

SDA

Registers

Diagnostic control

DIAG

DIAGEN

PWM Registers

CONF

OTP

NCV7684

GND

Figure 1. Block Diagram

V

OUT1

OUT2

OUT3

DD

SCL

SDA

CSN

DIAG

GND

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

DIAGEN

VS

V

CC

CONF

ISET

GND

Figure 2. Pinout Diagram

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2

NCV7684

V

SUPPLY

MRA4003T3G

LDO

or

V

STRING

C1

100 nF

DC/DC

C

OUT12

(optional)

1 nF

OUT1

(optional)

1 nF

e.g. sensor

C2

1 nF

R1

VS

OUT1

OUT12

2.2 k

V

CC

I

SET

3.3 V / 5 V

LDO

V

SUPPLY

C

R5 R6

VDD

V

DD

R4

100 nF

10 k

R2

10 k

CSN

SCL

SDA

DIAG

2

{

I C

DIAGEN

C

DIAG

R3

(optional)

CONF

2.2 k

Microcontroller

NCV7684

GND

1 nF

Figure 3. Application Diagram with Micro−controller (I²C Mode)

V

SUPPLY

MRA4003T3G

LDO

V

STRING

or

C1

100 nF

DC/DC

C

OUT12

OUT1

(optional)

1 nF

(optional)

1 nF

R1

2.2 k

e.g. sensor

VS

OUT1

OUT12

V

CC

I

SET

C2

1 nF

V

SUPPLY

V

DD

R4

10 k

R2

10 k

CSN

SCL

SDA

DIAG

DIAGEN

C

DIAG

R3

2.2 k

(optional)

CONF

NCV7684

GND

1 nF

Figure 4. Application Diagram without Micro−controller (Stand Alone Mode)

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3

NCV7684

Pin Function Description

Table 1. PIN FUNCTION DESCRIPTION

Pin #

1

Label

Description

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

GND

Channel 1 Current Output to LED

Channel 2 Current Output to LED

Channel 3 Current Output to LED

Channel 4 Current Output to LED

Channel 5 Current Output to LED

Channel 6 Current Output to LED

Channel 7 Current Output to LED

Channel 8 Current Output to LED

Channel 9 Current Output to LED

Channel 10 Current Output to LED

Channel 11 Current Output to LED

Channel 12 Current Output to LED

Ground

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

ISET

Current Setting

CONF

Stand Alone Mode Selection Bank

3.3 V Voltage Reference Output (Needs External Decoupling Capacitor)

Supply Voltage Input

V

CC

VS

DIAGEN

GND

Diagnostic Voltage Sensing Node for V

Ground

Via Resistor Divider

STRING

DIAG

Open−drain diagnostic input/output.

Reporting Open Circuit and thermal shutdown.

Normal Operation = HIGH

21

22

CSN

SDA

SCL

End of Line Chip Select

2

I C Serial Data

2

23

I C Serial Clock

24

V

DD

Digital Supply Voltage Input

epad

True Ground

Do NOT Connect to PCB Traces other than GND

Maximum Ratings

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Unit

Symbol

V

MAX

_VS

Power supply voltage:

Continuous supply voltage

−0.3

28

40

V

Transient Voltage (t < 500 ms, “load dump”)

V

MAX

_INx

Input pin voltage (DIAGEN, DIAG, CONF, CSN)

−0.3

40

V

MAX

_OUTx

Continuous Output Pin voltage

Transient Voltage (t < 500 ms, “load dump”)

−0.3

28

40

V

_V

Stabilized output voltage (V

CC

)

−0.3

−

3.6

5.5

3.6

750

150

V

MAX

CC

V

MAX

Digital input supply voltage (V

)

DD

V

_IO

DC voltage at pins (V , SCL, SDA)

V

MAX

DD

V

MAX

_ISET

_GND

DC voltage at pin ISET

V

I

Maximum Ground Current

mA

°C

MAX

T

Junction Temperature, T

−40

JMAX

J

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are

considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation.

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4

NCV7684

ESD Protection and Packaging

Table 3. EDS PROTECTION (Note 1)

Parameter

Value

Unit

kV

V

ESD Voltage, HBM (Human Body Model); (100 μF, 1500 Ω)

2

4

All Pins

Output Pins OUTx to GND

ESD According to CDM (Charge Device Model)

500

750

All Pins

Corner Pins

ESD According to MM (Machine Model)

All Pins

150

MSL3

37

V

Moisture Sensitivity (SSOP24−EP)

Package Thermal Resistance Junction to Ambient (SSOP24−EP)

°C/W

1. This device series incorporates ESD protection and is tested by the following methods:

ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model

MM according to AEC−Q100

Table 4. ELECTRICAL CHARACTERISTICS

(5 V < VS < 18 V, 3.15 V < V < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)

DD

J

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

GENERAL

Supply Voltage

VS_EXT

Functional extended range

(limited temperature)

5

−

28

V

VS_OP

VSUV

Parametric operation

5

3.8

−

18

4.4

−

V

Supply Under−Voltage

VS rising

4.1

200

Supply Under−Voltage Hysteresis

Supply Current (Vs)

VSUV

−

mV

HYS

I

S

All OUTx OFF except channel in

open load, VS = 12 V

(error mode)

V

DD

= 0 V

I

_V = 0 mA

OUT CC

mA

−

1.2

2.2

1.5

2.5

_V = 1 mA

OUT CC

I

Active Mode,

V unloaded,

CC

−

7

10

mA

S

(active)

VS = 16 V, R1 = 2 kΩ

2

Digital Supply Current

I

I C mode, V = 5 V, VS = 16 V

1.5

2.0

2.9

mA

V

DD

V

DD

Under Voltage Detection

V

UV_R

V

DD

rising

falling

DD

V

UV_F

V

DD

2

V

DD

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5

NCV7684

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(5 V < VS < 18 V, 3.15 V < V < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)

DD

J

Characteristic

CURRENT SOURCE OUTPUTS

Output Current

Symbol

Conditions

Min

Typ

Max

Unit

I

OUTx = 1 V, T = 150°C

50

−7

−6

−5

−

55

0

60

7

mA

%

OUTHOT

J

I

OUTx = 0.5 V, T = −40°C

J

OUTCOLD

Current Matching from Channel to Channel

I

T = −40°C (Note 1)

J

MATCHCOLD

I

T = 25°C (Note 1)

0

6

%

MATCH

J

I

T = 150°C (Note 1)

0

5

%

MATCHHOT

J

Current Slew Rate

ISRx

10% to 90%

30

50

−

mA/μs

Open Circuit Detection Threshold

OLDT

I

x > 20 mA

OUT

30

70

% of

output

current

Open Load Recovery in Auto−recovery Mode

OLR

−

5

10

15

mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Matching formulas:

2IOUTx(min)

IOUTx(min) ) IOUTx(max)

2IOUTx(max)

IOUTx(min) ) IOUTx(max)

ƪ

_* 1ƫ_{100 and}ƪ

_* 1ƫ

100

(eq. 1)

Table 5. ELECTRICAL CHARACTERISTICS

(5 V < VS < 18 V, 3.15 V < V < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)

DD

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

VOLTAGE REFERENCE

V_V

Output Voltage Tolerance

Output Current

I_V ≤ 1 mA

3.20

−

3.30

−

3.45

−1

V

CC

I

_V

−

mA

nF

OUT CC

C

_

Load Capacitor

ESR < 200 mΩ

0.9

1.0

2.5

LOAD VCC

INPUTS: CSN, CONF

V

L

Input Low Level

Input High Level

−

0.7

−

1.0

1.25

250

200

−

V

IN

H

1.66

400

280

Input Hysteresis

100

120

mV

kΩ

IN_HYST

R

Input Pull−down Resistor

0 V < V < 0.8 V

IN_PD

IN

INPUTS: SCL, SDA

V

L

Input Low Level

Input High Level

Input Hysteresis

Output Current

−

0.3 × V

V

IN

DD

H

−

0.7 × V

−

DD

−

0.05 × V

V

IN_HYST

DD

I

_SDA

V (SDA) = 0.4 V

3

mA

OUT

DIAGEN PIN

V TH

DIAGEN

VS Diagnostic Enable

Threshold

−

1.9

2.0

2.1

V

R

Input Pull−down Resistor

0 V < V

< 0.9 V

120

200

280

kΩ

DIAGEN_PD

DIAG

DIAG PIN

V

OUT

L

Output Low Level

Diagnostic Activated,

−

0.2

0.4

V

I

= 1 mA

DIAG

DiagRes

tp_DIAG

Diagnostic Reset Voltage

−

1.65

1.80

10

1.95

20

V

Filter Time to Set the DIAG

Fail Pin in Failure Mode

I

= 1 mA

−

μs

DIAG

DIAG_leak

DIAG Output Leakage

V

DIAG

= 5 V

−

10

μA

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6

NCV7684

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(5 V < VS < 18 V, 3.15 V < V < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)

DD

J

Symbol

ISET INPUT PIN

VISET

Parameter

Test Conditions

Min

Typ

Max

Unit

Global Current Setting

IOUT ISET Factor

−

0.94

−

1.00

100

−

1.06

−

V

−

K

tsetupISET

Setup−up Time to 90% of the

VS > 5 V

−

50

μs

ISET Regulated Value

INTERNAL PWM CONTROL UNIT (OUT1− OUT12)

2

PWM1

PWM2

PWM3

PWM1 Frequency, I C Mode

Configuration Via I C

220

110

440

250

125

500

280

140

560

Hz

2

PWM2 Frequency, I C Mode

Configuration Via I C

2

PWM3 Frequency, I C Mode

Configuration Via I C

Table 6. THERMAL WARNING AND THERMAL SHUTDOWN PROTECTION

Characteristic

Symbol

Min

Typ

Max

Unit

T

Thermal Warning Threshold (Junction

Temperature)

−

TSD − 30

−

°C

JWAR_ON

TSD

Thermal Shutdown Threshold (Junction

Temperature)

160

10

−

180

15

°C

T Increasing

J

T

Thermal Shutdown Hysteresis

JSD_HYS

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7

NCV7684

General

The NCV7684 is a twelve channel LED driver. Each

Example:

output can drive currents up to 60 mA/channel and are

programmable via an external resistor. The target

applications for the device are in automotive rear lighting

systems and dashboard applications. The device can be used

R1 = 2 kΩ

using eq. 2 → I

= 500 μA

OUTx

SET

and using eq. 3 → I

= 50 mA

To avoid potential disturbances when all drivers are

activated at the same time, a typical activation delay of

400 ns between groups of 2 consecutive outputs is

implemented (see Figure 5).

2

with micro−controller applications using the I C bus or in

stand−alone applications. In both cases it is mandatory to

supply the LED channels by an external ballast transistor, or

by an LDO or a DC/DC. In order to have very low

electromagnetic emission, this device has an embedded

spread spectrum oscillator.

Output Current Programming (I_SET/OUTx)

The maximum current can be defined with the Iset input

pin. The equations below can be used to calculate this

maximum output current:

Iset + 1 VńR1

(eq. 2)

IOUTx + K Iset

(eq. 3)

PWM period counter

PWM signal

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

driver 1

driver 2

driver 3

driver 4

driver 5

driver 6

driver 7

driver 8

driver 9

driver 10

driver 11

driver 12

Figure 5.

Power Supply and Voltage Reference (VS, V_CC, V_DD

)

bus. When CSN will be connected to ground or below 0.7 V,

the device will be in a mode where zapping is not possible.

Zapping is only possible with VS above 13 V.

VS is the analog power supply input of the device. VS

supply is monitored with respect to the crossing of VSUV

level (typ. 4.1 V). When VS rises above VSUV, the device

starts the power−up state. When VS is above the VS_OP

minimum level (typ. 5 V), the device can work properly.

Configuration (CONF)

When the CONF input voltage will be below 0.7 V the

configuration 1 will be selected (One Time Programmable

OTP 1 register called SAM_CONF_1) and when the CONF

input voltage will be above 1.66 V the configuration 2 will

be selected (OTP 2 register called SAM_CONF_2). There

is ability to change the configuration in error mode (either

V

CC

is a voltage reference providing 3.3 V derived from

the VS main supply. It is able to deliver up to 1 mA and is

primarily intended to supply 3.3 V loads.

V

DD

is the digital power supply input of the device.

2

Ground Connections (GND: Pin 13 and Pin 19)

The device ground connection is split to two pins called

GND. Both pins have to be connected on the application

PCB.

with CONF in SAM or through I C in I2C mode).

I²C Bus (SCL, SDA)

2

The I C bus consists of two wires, Serial Data (SDA) and

Serial Clock (SCL), carrying information between the

devices connected on the bus. Each device connected to the

bus is recognized by a unique address and operates as either

a transmitter or receiver, depending on the function of the

device. The NCV7684 can both receive and transmit data

Chip Select (CSN)

The device can programmable using the I C bus in End Of

Line cases. When the CSN pin has a voltage above 1.66 V,

the device will be set in zapping control mode via the I C

2

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8

NCV7684

Diagnostic Feedback (DIAG)

with CRC8 error detection algorithm. The NCV7684 is a

slave device.

The DIAG is an open drain output pin who can alert a

microcontroller as soon as one of the outputs is in error mode

(DIAG Low = open load or thermal shut−down or Iset

shorted). Forcing the DIAG pin below 1.8 V will force a

fault condition if the DIAGEN input pin is above a typical

value of 2 V. If the DIAGEN input pin is below the typical

value of 2 V then forcing the DIAG input pin will not have

any effect.

SDA is a bi−directional line connected to a positive supply

voltage via an external pull−up resistor. When the bus is free

both lines are HIGH. The output stages of the devices

connected to the bus must have an open drain to perform the

2

wired−AND function. Data on the I C bus can be transferred

up to 400 kb/s.

Diagnostic Enabling (DIAGEN)

Parallel Outputs (OUTx)

The device is capable to detect for each independent

channel an open load condition. Versus the number of LEDs

The maximum rating per output is 60 mA. In order to

increase system level LED string current, parallel

combinations of any number of outputs is allowed.

Combining all 12 outputs will allow for a maximum system

level string current design of 720 mA.

and the V

voltage supply, a wrong open load

STRING

condition can be detected if the fault detection is activated

when there is not enough voltage across the LEDs. This

threshold can be programmable thanks to an external divider

connected to the DIAGEN pin. When the divided voltage is

below a typical value of 2 V, the LED diagnostic is disabled.

When the divided voltage is above the typical value of 2 V,

the LED diagnostic is enabled.

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9

NCV7684

2

DIGITAL PART AND I C REGISTERS

2

The I C bus consists of two wires, serial data (SDA) and

serial clock (SCL), carrying information between the

devices connected on the bus. Each device connected to the

bus is recognized by a unique address. The NCV7684 can

both receive and transmit data with CRC8 error detection

algorithm. The NCV7684 is a slave device only. Generation

2

of the signals on the I C bus is always the responsibility of

the master device.

They are multiple kinds of message structure possible

versus ID code received.

Table 7. IDENTIFIER ADDRESSING (ID) MESSAGE

Name

ID

00

01

02

03

08

09

0A

20

21

28

Access type

Name of Register Addressed

ID_I2C_CONF

ID_PWM

W

R

I2C_CONF

PWM_GAIN, PWM_GAIN_EN

ID_WRITEALL

ID_PWM_CONF

ID_STATUS

I2C_CONF, PWM_GAIN, PWM_GAIN_EN

PWM_CONF

I2C_STATUS

ID_FAULT

R

FAULT_STATUS

ID_READALL

ID_SET_OTP

ID_LOCK_OTP

ID_READ_OTP

R

I2C_CH_STATUS, I2C_STATUS, FAULT_STATUS

SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET

ID_VERS_1, ID_VERS_2, SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET

W

R

There are 3 kinds of registers, Hard Coding, OTP and

volatile registers.

Volatile Registers:

I2C_CONF

I2C_STATUS

Hard Coding Registers:

ID_VERS_1

ID_VERS_2

I2C_CH_STATUS

FAULT_STATUS

PWM_GAIN

PWM_GAIN_EN

PWM_CONF

OTP Registers:

ADD_SAM_SET

SAM_CONF_1

SAM_CONF_2

Format of the I2C frames

S

NCV7684 address

0

A

NCV7684 address

A

ID

A

Data

A

CRC

A*

P

‘0’ = Write

N bytes +

acknowledge

From master to NCV7684

S = Start condition

P = Stop condition

A = Acknowledge

From NCV7684 to master

A* = Not acknowledge

Figure 6. Format of I²C Write Access Frames

NCV7684

address

NCV7684

address

NCV7684

address

S

0

A

ID

A

CRC A* Sr

1

A

Data

A

CRC A* P

‘0’ = Write

‘1’ = Read

N bytes +

acknowledge

S = Start condition

From master to NCV7684

Sr = Repeated start condition

P = Stop condition

From NCV7684 to master

A = Acknowledge

A* = Not acknowledge

Figure 7. Format of I²C Read Access Frames

Remark: CRC byte is not transmitted when CRC

protection is turned off (ERREN = 0)

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10

NCV7684

Figure 8. Format of I²C Frames

Figure 9. Format of I²C OTP Frames

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11

NCV7684

There is a safety mechanism implemented by repeating

the address. Since the I C address is 7 bits long, first bit of

the second address byte starts with a “0” in the repeated byte

(see tables below).

2

Table 8.

st

1

Byte

7

6

5

4

3

2

1

0

2

I C Device Address

R/W Bit

nd

2

Byte

4

0

2

I C Device Address

HARD CODING REGISTERS

Table 9. HARD CODING REGISTERS

Bit

D7

D6

D5

D4

D3

D2

D1

D0

ID_VERS_1

Bit name

ID1[7:0]

ID2[7:0]

Access type

Reset value

ID_VERS_2

Bit name

R

0

R

1

R

0

R

0

R

0

R

0

R

1

R

1

Access type

Reset value

R

0

R

0

R

0

R

0

R

0

R

0

R

1

R

0

1. ID1[7:0] = 43h (ON Semi Device Identifier)

ID2[7:0] = 02h (The Actual Version)

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12

NCV7684

OTP REGISTERS

Table 10. ADD_SAM_SET

Bit

D7

AUTOR

R/W

0

D6

DETONLY

R/W

D5

ERREN

R/W

0

D4

D3

D2

ADD[4:0]

R/W

D1

D0

Bit name

Access type

Reset value

R/W

0

R/W

0

R/W

0

R/W

0

1

0

ADD[4:0] are the programmable BUS address registers

(in I2C mode ADD[6:5] = 11).

DETONLY: When DETONLY = 1, open load diagnostic

is performed. When a fault is detected, the DIAG pin is set

without taking any action on the current regulation. When

fault is recovered, DIAG is reset. If the DIAG pin is

triggered externally, no action is taken.

When AUTOR = DETONLY = 0, no diagnostic performed

When AUTOR = DETONLY = 1, no change

(same as previously setting).

AUTOR: When AUTOR = 1 (and DIAGEN is high), open

load diagnosis is performed. When a fault is detected, the

DIAG pin is set and LED driver imposes a low current on the

faulty branch alone, switching off the others. When fault is

recovered, LED driver returns to normal operation after

resetting the DIAG pin. If the DIAG pin is triggered

externally, LED driver outputs are switched off and the low

power mode is entered.

ERREN: When ERREN = 1, CRC error detection

2

algorithm is activated for I C communication.

Table 11. SAM_CONF

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SAM_CONF_1

Bit name

−

R

0

−

R

0

−

R

0

−

R

0

SAM1conf[11:0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Access type

Reset value

SAM_CONF_2

Bit name

1

−

R

0

−

R

0

−

R

0

−

R

0

SAM2conf[11:0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Access type

Reset value

1

1. SAM1conf[x] = 0 means channel is OFF and SAM1conf[x] = 1 means channel is ON

SAM2conf[x] = 0 means channel is OFF and SAM2conf[x] = 1 means channel is ON

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13

NCV7684

VOLATILE REGISTERS

Table 12. I2C_CONF

Bit

D15

D14

D13

D12

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Bit name

I2CFLAG

I2CautoR

I2CdOnly

PWMEN

I2Cconf[11:0]

Access type

Reset value

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

I2CFLAG: the I2CFLAG should be reset whenever

standalone mode is entered. When I2CFLAG = 1 and when

without taking any action on the current regulation. When

fault is recovered, DIAG is reset. If the DIAG pin is

triggered externally, no action is taken.

V

is high, the I2C mode is activated, in all other

DD

conditions the device is in Stand Alone Mode.

When I2CautoR = I2CdOnly = 0, no diagnostic

performed.

When I2CautoR = I2CdOnly = 1, no change (same as

previously setting).

PWMEN: When PWMEN = 1, PWM is activated, when

PWMEN = 0 the content of the complete register

PWM_GAIN_EN is not reset and PWM is disabled.

I2Cconf[x] = 0 means channel is OFF and I2Cconf[x] =

1 means channel is ON.

I2CautoR: When I2CautoR = 1 (and DIAGEN is high),

open load diagnosis is performed. When a fault is detected,

the DIAG pin is set and LED driver imposes a low current

on the faulty branch alone, switching off the others. When

fault is recovered, LED driver returns to normal operation

after resetting the DIAG pin. If the DIAG pin is triggered

externally, LED driver outputs are switched off and the low

power mode is entered.

I2CdOnly: When I2CdOnly = 1, open load diagnostic is

performed. When a fault is detected, the DIAG pin is set

Table 13. I2C STATUS

Bit

D7

D6

I2Cerr

R

D5

UV

R

D4

D3

TW

R

D2

TSD

R

D1

D0

OL

R

Bit name

Access type

Reset value

SC_Iset

diagRange

DIAGERR

R

0

R

0

R

0

SC_Iset: SC_Iset = 1 means there is short−circuit on the

external resistor on Iset pin and drivers are switched OFF

and DIAG pin is set. SC_Iset = 0 no short−circuit.

I2Cerr: I2Cerr = 1 means an error has been detected

during the I2C communication, I2Cerr = 0 means no error

during I2C communication has been detected.

UV: the device is in under voltage condition (VS is below

VSUV threshold, all channels OFF).

diagRange: when diagRange = 1 the divided voltage is

above the typical value of 2 V (LED diagnostic is enabled),

diagRange = 0 means the divided voltage is below the

typical value of 2 V (LED diagnostic is disabled).

TW: when TW=1 the device is in the thermal warning

range (typ. 140°C), this flag is just a warning no action is

foreseen on the output drivers. TW = 0 means the device is

below the thermal warning range.

TSD: when TSD = 1 the device is in the Thermal shutdown

range, TSD = 0 means the device is below the thermal

shutdown range.

DIAGERR: DIAGERR = 1 means an error is detected by

DIAG pin forced externally.

OL: OL = 1 means at least one channel is in Open Load

condition, OL = 0 no Open Load.

Table 14.

SC_I

Set when a short−circuit on the external resistor on Iset pin, latched if permanent after 10 μs.

Reset in case of short−circuit disappear permanently for at least 10 μs

SET

I2C

Set if an error has been detected during the I2C communication.

Reset on register reading

ERR

UV

Set when device is in under voltage condition (VS is low, all channels OFF)

diagRange

Set when divided voltage is above the V

TH threshold.

DIAGEN

Reset when the divided voltage is below the V

TH threshold

DIAGEN

TW

Set when junction temperature is above the T

threshold.

JWAR_ON

Reset on register reading and if temperature is below the (T

− T

) threshold

JWAR_ON

JSD_HYS

TSD

Set when junction temperature is above the TSD threshold.

Reset on register reading and if temperature is below the TSD − T

) threshold

JSD_HYS

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14

NCV7684

Table 14. (continued)

DIAGERR

Set by DIAG pin forced low externally, latched if permanent after 10 μs.

Reset in case DIAG pin is not forced permanently for at least 10 μs

OL

Set in Open Load condition and DIAGEN is high, latched if permanent after 10 μs.

Reset if Open Load disappear permanently for at least 10 μs.

Fault information is maintained on falling DIAGEN threshold exceeded

Table 15. I2C_CH_STATUS

Bit

D15

D14

D13

D12

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Bit name

I2CFLAG

I2CautoR

I2CdOnly

PWMEN

I2C_CH_STATUS[11:0]

Access type

Reset value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

I2CFLAG: same as I2C_CONF register.

I2CautoR: same as I2C_CONF register.

I2CdOnly: same as I2C_CONF register.

PWMEN: same as I2C_CONF register.

Remark: When NCV7684 is configured in I2C mode and

output channel OUTx is configured to operate in PWM

mode, I2C_CH_STATUS[x] shall contain value ‘1’.

I2C_CH_STATUS[11:0]: same as I2C_CONF[11:0] bits

in I2C mode or same as SAM_CONF_1[11:0],

SAM_CONF_2[11:0] bits in Standalone mode.

Table 16. FAULT_STATUS

Bit

D15

−

D14

−

D13

−

D12

−

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Bit name

Access type

Reset value

FAULT[11:0]

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

FAULT[11:0]: when FAULT[x] = 1 the OUTx channel is

in fault mode (Open Load latched when the duration is

longer than 10 μs), when FAULT[x] = 0 the OUTx channel

is working properly. The register is reset on each read

operation.

Table 17. PWM_GAIN

Bit

D7

PWMF1

W

D6

D5

D4

D3

D2

D1

D0

Bit Name

Access type

Reset Value

PWMGAIN[6:0]

W

0

W

0

W

0

W

0

W

0

W

0

W

0

PWMGAIN[6:0]: logarithmic (or linear) dimming via

embedded PWM generator (128 steps). Following formula

PWMF1: when PWMF1 = 1, PWM dimming is done at a

typical frequency of 250 Hz, when PWMF1 = 0 means

PWM dimming is done at a typical frequency of 125 Hz

(when PWMF2 = 0).

applies when logarithmic dimming is selected:

(N − i)

Duty_Cycle_Percent = 100 × α

where α = 0.9471,

N = 127 and i = PWMGAIN[6:0] rounded with an accuracy

of 400 ns.

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15

NCV7684

Table 18. PWM_GAIN_EN

Bit

D15

−

D14

−

D13

−

D12

−

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Bit name

Access type

Reset value

PWMGAINen[11:0]

−

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

PWMGAINen[11 :0] : when PWMGAINen[x] = 1, PWM

dimming is enabled for OUTx channel, when

PWMGAINen[x] = 0 means PWM dimming is disabled for

OUTx channel.

Table 19. PWM_CONF

Bit

D7

−

D6

−

D5

−

D4

−

D3

−

D2

−

D1

D0

PWMF2

W

Bit name

Access type

Reset value

PWMLIN

W

0

W

0

W

0

W

0

W

0

W

0

W

0

PWMLIN bit shall select between logarithmic (PWMLIN

= 0) and linear (PWMLIN = 1) translation of PWMGAIN

bits to duty cycle of internal PWM signal.

PWMF2: when PWMF2 = 1, PWM dimming is done at a

typical frequency of 500 Hz, when PWMF2 = 0, PWMF1

setting applies.

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16

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SSOP24 NB EP

CASE 940AP

ISSUE O

SCALE 1:1

DATE 05 MAR 2015

2X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

0.20 C A-B

NOTE 4

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE

LOCATED ON THE LOWER RADIUS OF THE

FOOT. DIMENSION b APPLIES TO THE FLAT

SECTION OF THE LEAD BETWEEN 0.10 TO 0.25

FROM THE LEAD TIP.

NOTE 6

D

L1

A

24

13

2X

H

L2

0.20 C

GAUGE

PLANE

4. DIMENSION D DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH, PROTRUSIONS OR GATE BURRS SHALL

NOT EXCEED 0.15 PER SIDE. DIMENSION D IS

DETERMINED AT DATUM PLANE H.

5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH

OR PROTRUSION SHALL NOT EXCEED 0.25 PER

SIDE. DIMENSION E1 IS DETERMINED AT DA-

TUM PLANE H.

E1

E

L

A1

NOTE 5

PIN 1

SEATING

PLANE

DETAIL A

C

NOTE 7

REFERENCE

1

12

0.20 C

e

2X 12 TIPS

24X b

B

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

NOTE 6

M

0.12

C A-B D

7. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

8. CONTOURS OF THE THERMAL PAD ARE UN-

CONTROLLED WITHIN THE REGION DEFINED

BY DIMENSIONS D2 AND E2.

TOP VIEW

DETAIL A

A

A2

h

0.10 C

M

MILLIMETERS

DIM MIN

MAX

1.75

0.10

1.65

0.30

0.20

c

A

A1

A2

b

---

0.00

1.10

0.19

0.09

A1

SEATING

PLANE

END VIEW

24X

C

SIDE VIEW

c

M

0.15

C A-B

D

8.64 BSC

NOTE 8

D2

E

2.37

2.67

D2

6.00 BSC

3.90 BSC

1.79 1.99

0.65 BSC

0.25 0.50

0.40 0.85

1.00 REF

0.25 BSC

E1

E2

e

M

0.15

C A-B

D

h

L

E2

L1

L2

M

NOTE 8

0

8

_

GENERIC

MARKING DIAGRAM*

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT

XXXXXXXXXG

AWLYYWW

2.72

XXXX = Specific Device Code

24X

1.15

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

2.19

6.40

(Note: Microdot may be in either location)

1

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

24X

0.40

0.65

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON96176F

SSOP24 NB EP

PAGE 1 OF 1

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


型号：	NCV7684DQR2G
厂家：	ONSEMI
描述：	LED 线性电流驱动器，12 沟道，60 mA，可控制 I2C 驱动驱动器
文件：	总18页 (文件大小：252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV7684DQR2G [ONSEMI]

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