NCV7704 [ONSEMI]
Mirror-Module Driver-IC;
| 型号： | NCV7704 |
| 厂家： | 
ONSEMI |
| 描述： | Mirror-Module Driver-IC |
| 文件： | 总34页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7704, NCV7714
Mirror-Module Driver-IC
The NCV7704/NCV7714 is a powerful Driver−IC for automotive
body control systems. The IC is designed to control several loads in
the front door of a vehicle. The monolithic IC is able to control mirror
functions like mirror positioning and heating. In addition, NCV7714
includes the electro−chromic mirror feature. The device features three
high−side outputs to drive LEDs or incandescent bulbs (up to 10 W).
To allow maximum flexibility, all lighting outputs can be PWM
controlled thru PWM inputs (external signal source) or by an internal
programmable PWM generator unit. The NCV7704/NCV7714 is
controlled thru a 24 bit SPI interface with in−frame response.
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SSOP36 EP
DQ SUFFIX
CASE 940AB
Features
• Operating Range from 5.5 V to 28 V
• Three High−Side and Three Low−Side Drivers Connected as
MARKING DIAGRAM
Half−Bridges
♦ 3 Half−bridges I
= 0.75 A; R
= 1.6 W @ 25°C
load
DS(on)
• Three High−Side Lamp Drivers
♦ 2x LED; I = 0.3 A; R
♦ 1x 10 W; Configurable as LED Driver; I
= 1.4 W @ 25°C
DS(on)
load
NCV77x4
AWLYYWWG
= 2.5 A;
load
R
DS(on)
= 300 mW @ 25°C
• One High−Side Driver for Mirror Heating; I
= 6 A;
load
R
DS(on)
= 100 mW @ 25°C
NCV7704 or NCV7714
= Specific Device Code
• Electro Chromic Mirror Control (NCV7714 Only)
♦ 1x 6−Bit Selectable Output Voltage Controller
A
= Assembly Location
= Wafer Lot
♦ 1x LS for EC Control; I
= 0.75 A; R
= 1.6 W @ 25°C
load
DS(on)
WL
YY
WW
G
= Year
• Independent PWM Functionality for All Outputs
= Work Week
= Pb−Free Package
• Integrated Programmable PWM Generator Unit for All Lamp Driver
Outputs
♦ 7−bit / 9−bit Selectable Duty−cycle Setting Precision
• Programmable Soft−start Function to Drive Loads with Higher
Inrush Currents as Current Limitation Value
• Multiplex Current Sense Analog Output for Advanced Load
Monitoring
ORDERING INFORMATION
†
Shipping
Device
Package
SSOP36−EP
GREEN
(Pb−Free)
NCV7704DQR2G
NCV7714DQR2G
1500 / Tape &
Reel
• Very Low Current Consumption in Standby Mode
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Charge Pump Output to Control an External Reverse Polarity
Protection MOSFET
• 24−Bit SPI Interface for Output Control and Diagnostic
• Protection Against Short−circuit, Overvoltage and Over−temperature
• Downwards Pin−to−Pin and SPI Registers Compatible with
NCV7707
Typical Applications
• AEC−Q100 Qualified and PPAP Capable
• SSOP36−EP Power Package
• This is a Pb−Free Device
• De−centralized Door Electronic Systems
• Body Control Units (BCUs)
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
April, 2016 − Rev. 0
NCV7704/D
NCV7704, NCV7714
VS
CHP
NCV7704/14
Diagnostic
short circuit
openload
Undervoltage
Lockout
Overvoltage
Lockout
Power−on Reset
Chargepump
overload
overtemperature
overvoltage
undervoltage
VCC
SI
SCLK
CSB
CONTROL _0 Register
VS
SO
OUT1
OUT2
OUT3
CONTROL _1 Register
CONTROL _2 Register
CONTROL _3 Register
PWM_4 Register
Driver
Interface
VS
VS
VS
PWM
Unit
PWM_5/6 Register
STATUS _0 Register
STATUS _1 Register
OUT4
OUT5
OUT6
VS
VS
STATUS _2 Register
CONFIG Register
VS
Special Function Register
OUT7
OUT7
PWM1
PWM1
PWM2
ISOUT/PWM2
MUX
ECON
ECFB
DAC
EC Control
6
NCV7714 only
GND
Figure 1. Block Diagram
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2
NCV7704, NCV7714
footstep
light
safety
light
Vbat
blinker
LED
OUT6
10W
LED
/LED
Switches
VS
OUT5
OUT4
CHP
NCV7704/14
High−Side High−Side
High−Side
Switch
Charge Pump
Switch
Switch
24−bit
Serial
Data
Ω)
Ω)
Ω)
SO
SI
(1.4
(1.4
(0.3/1.4
Power−on Reset
Interface
Current
Sensing
Logic Control
SCLK
CSB
Protection:
short circuit
open load
over temperature
VS undervoltage
VS overvoltage
PWM Generator Unit
Logic IN
mC
PWM1
Current Sensing
ISOUT /
PWM2
Rs
PWM
High−Side
Switch
High−Side
Switch
High−Side
Switch
High−Side
Switch
GND
Ω)
Ω)
(1.6
(1.6
Ω)
Ω)
(1.6
(0.1
Low−Side
Switch
Low−Side
Switch
Low−Side
Switch
Low−Side
Switch
DAC
EC Control
CAN/LIN SBC
Ω)
(1.6
Ω)
Ω)
Ω)
(1.6
(1.6
(1.6
(NCV7462)
VCC
OUT2
OUT1
OUT3
mirror
y−axis
ECON
OUT6
ECFB
OUT7
LIN
mirror
x−axis
mirror
defroster
(NCV7321)
LIN
CAN
ECM
NCV7714 only
Figure 2. Application Diagram
NCV7704
NCV7714
GND
OUT7
OUT6
OUT5
VS
OUT4
n.c.
VS
VS
PWM1
CHP
VS/TEST
n.c.
n.c.
GND
OUT7
OUT1
OUT2
OUT3
GND
1
36
1
36
GND
OUT7
OUT1
OUT2
OUT3
OUT7
OUT6
OUT5
ECFB
VS
VS
VS
VS
OUT4
n.c.
VS
SI
ISOUT/PWM2
CSB
SI
ISOUT/PWM2
CSB
VS
PWM1
CHP
ECON
n.c.
n.c.
n.c.
n.c.
SO
VCC
SCLK
n.c.
n.c.
n.c.
n.c.
n.c.
SO
VCC
SCLK
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
GND
n.c.
GND
18
18
19
19
Figure 3. Pin Connections (Top View)
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3
NCV7704, NCV7714
Table 1. PIN FUNCTION DESCRIPTION
Pin
No.
Pin Name
Pin Type
Description
1
GND
Ground
Ground Supply (all GND pins have to be connected externally)
Heater Output (has to be connected externally to pin 35)
Mirror common Output
2
OUT7
OUT1
OUT2
OUT3
VS
HS driver Output
Half bridge driver Output
Half bridge driver Output
Half bridge driver Output
Supply
3
4
Mirror x/y control Output
5
Mirror x/y control Output
6
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
SPI interface Serial Data Input
7
VS
Supply
8
SI
Digital Input
9
ISOUT/PWM2
Digital Input /
Analog Output
PWM control Input / Current Sense Output. This pin is a bidirectional pin. De-
pending on the selected multiplexer bits, an image of the instant current of the
corresponding HS stage can be read out.
This pin can also be used as PWM control input pin for OUT4 and OUT6.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CSB
SO
Digital Input
Digital Output
Supply
SPI interface Chip Select
SPI interface Serial Data Output
Logic Supply Input
VCC
SCLK
n.c.
Digital Input
SPI interface Shift Clock
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
GND
n.c.
Ground
Ground Supply (all GND pins have to be connected externally)
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
VS/TEST
Supply
Test Input, has to be connected to VS in application
(NCV7704 only)
ECON
(NCV7714 only)
ECM driver Output
Electrochromic mirror control DAC output. If the Electrochrome feature is select-
ed, this output controls an external Mosfet, otherwise it remains in high−imped-
ance state.
If the electrochrome feature is not used in the application and not selected via
SPI the pin can be connected to VS.
26
27
28
29
30
31
32
CHP
PWM1
VS
Analog Output
Digital Input
Supply
Reverse Polarity FET Control Output
PWM control Input for OUT1−3, OUT5 and OUT7
Battery Supply Input (all VS pins have to be connected externally)
Battery Supply Input (all VS pins have to be connected externally)
Not connected
VS
Supply
n.c.
OUT4
HS driver Output
Supply
LED / Bulb Output
VS
Connect to VS pins externally (no power connection)
(NCV7704 only)
ECFB
ECM Input / Output
Electrochromic Mirror Feedback Input, Fast discharge transistor Output
(NCV7714 only)
33
34
35
36
OUT5
OUT6
HS driver Output
HS driver Output
HS driver Output
Ground
LED Output
LED Output
OUT7
Heater Output (has to be connected externally to pin 2)
Ground Supply (all GND pins have to be connected externally)
Substrate; Heat slug has to be connected to all GND pins
GND
Heat slug
Ground
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4
NCV7704, NCV7714
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Min
Max
Unit
Vs
Power supply voltage
− Continuous supply voltage
− Transient supply voltage (t < 500 ms, “clamped load dump”)
V
−0.3
−0.3
28
40
Vcc
Vdig
Logic supply
−0.3
−0.3
−0.3
5.5
V
V
V
V
DC voltage at all logic pins (SO, SI, SCLK, CSB, PWM1)
Current monitor output / PWM2 logic input
Charge pump output (the most stringent value is applied)
Vcc + 0.3
Vcc + 0.3
Visout/pwm2
Vchp
−25
40
Vs − 25
Vs + 15
Voutx, Vecon,
Vecfb
Static output voltage (OUT1−7, ECON, ECFB)
−0.3
Vs + 0.3
V
A
Iout1/2/3
OUT1/2/3 Output current
− Tj w 25°C
−1.25
−1.35
1.25
1.35
− Tj < 25°C
Iout4
OUT4 Output current
− DC
− Transient
A
A
A
A
−5
5
Iout5/6
Iout7
OUT5/6 Output current
− DC
− Transient
−1.25
−10
1.25
OUT7 Output current
− DC
− Transient
10
Iout_ecfb
ECFB Output current
1.25
(NCV7714
only)
ESD_HBM
ESD Voltage, HBM (Human Body Model); (100 pF, 1500 W) (Note 1)
− All pins
− Output pins OUT1−3 and ECFB to GND (all unzapped pins grounded)
kV
V
−2
−4
2
4
ESD_CDM
ESD according to CDM (Charge Device Model) (Note 1)
− All pins
− Corner pins
−500
−750
500
750
Tj
Operating junction temperature range
Storage temperature range
−40
−55
150
150
°C
°C
Tstg
MSL
Moisture sensitivity level (Note 2)
MSL3
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charge Device Model tested per EIA/JES D22/C101, Field Induced Charge Model
2. For soldering information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
R
Thermal Characteristics, SSOP36−EP, 1−layer PCB
Thermal Resistance, Junction−to−Air (Note 3)
42
°C/W
θJA
R
Thermal Characteristics, SSOP36−EP, 4−layer PCB
Thermal Resistance, Junction−to−Air (Note 4)
19.5
°C/W
θJA
3. Values based on PCB of 76.2 x 114.3 mm, 72 mm copper thickness, 20% copper area coverage and FR4 PCB substrate.
4. Values based on PCB of 76.2 x 114.3 mm, 72 / 36 mm copper thickness (signal layers / internal planes), 20 / 90% copper area coverage (signal
layers / internal planes) and FR4 PCB substrate.
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NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
Vs
Supply voltage
Functional (see Vuv_vs / Vov_vs)
Parameter specification
5.5
8
28
18
V
Is(standby)
Supply Current (VS), Standby
mode
Standby mode,
mA
VS = 16 V, 0 V v VCC v 5.25 V,
CSB = VCC, OUTx/ECx = floating,
SI = SCLK = 0 V, Tj < 85°C
(Tj = 150°C)
3.5
12
(6.5)
7.5
(25)
20
Is(active)
Supply current (VS), Active mode
Active mode, VS = 16 V,
OUTx/ECx = floating
mA
Icc(standby)
Supply Current (VCC), Standby
mode
Standby mode,
mA
VCC = 5.25 V,
4.5
6
SI = SCLK = 0 V, Tj < 85°C
(Tj = 150°C)
(11.5)
5.5
(50)
8.4
Icc(active)
I(standby)
Supply current (VCC), Active mode Active mode, VS = 16 V,
OUTx/ECx = floating
mA
Total Standby mode supply current Standby mode,
8
18
mA
(Is + Icc)
VS = 16 V, Tj < 85°C,
CSB = VCC, OUTx/ECx = floating
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
Vuv_vs(on)
Vuv_vs(off)
Vuv_vs(hys)
Vov_vs(off)
Vov_vs(on)
Vov_vs(hys)
Vuv_vcc(off)
Vuv_vcc(on)
Vuv_vcc(hys)
td_uv
VS Undervoltage detection
VS increasing
5.6
5.2
6.2
5.8
V
V
V
V
V
V
V
V
V
ms
VS decreasing
VS Undervoltage hysteresis
VS Overvoltage detection
Vuv_vs(on) − Vuv_vs(off)
VS increasing
0.65
2
20
19
24.5
23.5
VS decreasing
VS Overvoltage hysteresis
VCC Undervoltage detection
Vov_vs(off) − Vov_vs(on)
VCC increasing
2.9
VCC decreasing
2
VCC Undervoltage hysteresis
VS Undervoltage filter time
Vuv_vcc(off) − Vuv_vcc(on)
0.11
Time to set the power supply fail bit
UOV_OC in the Global Status Byte
6
13
td_ov
VS Overvoltage filter time
Time to set the power supply fail bit
UOV_OC in the Global Status Byte
50
100
ms
CHARGE PUMP OUTPUT CHP
Vchp8
Vchp10
Vchp12
Ichp
Chargepump Output Voltage
Vs = 8 V, Ichp = −60 mA
Vs + 6 Vs + 9.5 Vs + 13
Vs + 8 Vs + 11 Vs + 13
Vs + 9.5 Vs + 11 Vs + 13
V
V
Chargepump Output Voltage
Chargepump Output Voltage
Chargepump Output current
Vs = 10 V, Ichp = −80 mA
VS > 12 V, Ichp = −100 mA
VS = 13.5 V, Vchp = Vs + 10 V
V
−750
−95
mA
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NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
MIRROR x/y POSITIONING OUTPUTS OUT1, OUT2, OUT3
Ron_out,12,3
On−resistance HS or LS
Tj = 25°C, Iout1,2,3 = 0.5 A
Tj = 125°C, Iout1,2,3 = 0.5 A
1.6
W
W
A
3
Ioc1,2,3_hs
Ioc1,2,3_ls
Overcurrent threshold HS
Overcurrent threshold LS
Tj < 25°C
Tj w 25°C
Tj < 25°C
Tj w 25°C
−1.35
−1.25
−0.75
0.75
1.35
1.25
A
Vlim1,2,3
Iuld1,2,3_hs
Iuld1,2,3_ls
Vds voltage limitation HS or LS
Underload detection threshold HS
Underload detection threshold LS
Output delay time, HS Driver on
Output delay time, HS Driver off
Output delay time, LS Driver on
Output delay time, LS Driver off
2
3
−10
32
6
V
mA
mA
ms
−32
10
−20
20
2.5
3
td_HS1,2,3(on)
td_HS1,2,3(off)
td_LS1,2,3(on)
td_LS1,2,3(off)
tdLH1,2,3
Time from CSB going high to
V(OUT1,2,3) = 0.1·Vs / 0.9·Vs (on/off)
6
ms
Time from CSB going low to
V(OUT1,2,3) = 0.9·Vs / 0.1·Vs (on/off)
1
6
ms
1
6
ms
Cross conduction protection time,
low−to−high transition including LS
slew−rate
0.5
22
ms
tdHL1,2,3
Cross conduction protection time,
high−to−low transition including HS
slew−rate
5.5
22
ms
Ileak_act_hs1,2,3
Ileak_act_ls1,2,3
Output HS leakage current,
Active mode
V(OUT1,2,3) = 0 V
V(OUT1,2,3) = VS
V(OUT1,2,3) = 0 V
−40
−5
−16
100
mA
mA
mA
Output pull−down current,
Active mode
160
Ileak_stdby_hs1,2,3 Output HS leakage current,
Standby mode
Ileak_stdby_ls1,2,3 Output pull−down current,
Standby mode
V(OUT1,2,3) = VS, Tj w 25°C
V(OUT1,2,3) = VS, Tj < 25°C
80
120
175
mA
mA
td_uld1,2,3
tdb_old1,2,3
td_old1,2,3
Underload blanking delay
Overload shutdown blanking delay Timer started after output activation
430
16
610
25
ms
ms
ms
Overload shutdown filter time
Timer started after blanking delay
elapsed
16
50
frec1,2,3L
frec1,2,3H
dVout1,2,3
Recovery frequency, slow
recovery mode
CONTROL_3.OCRF = 0
1
2
4
6
kHz
kHz
V/ms
Recovery frequency, fast
recovery mode
CONTROL_3.OCRF = 1
Slew rate of HS driver
Vs = 13.5 V, Rload = 64 W to GND
1.5
2.5
3.5
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NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
0.3
1.4
Max
Unit
BULB / LED DRIVER OUTPUT OUT4
Ron_out4_ICB
Ron_out4_LED
Ilim4_ICB
On−resistance to supply,
HS switch, Bulb mode
Tj = 25°C, Iout4 = −1 A
W
W
W
W
A
Tj = 125°C, Iout4 = −1 A
Tj = 25°C, Iout4 = −0.2 A
Tj = 125°C, Iout4 = −0.2 A
0.6
On−resistance to supply,
HS switch, LED mode
3
Output current limitation to GND,
Bulb mode
Tj < 25°C
Tj w 25°C
−3.9
−3.7
−2.5
Ilim4_LED
Iuld4_ICB
Overcurrent threshold,
LED mode
−1.1
−70
−15
−0.5
−5
−5
48
A
mA
mA
ms
Underload detection threshold,
Bulb mode
Iuld4_LED
Underload detection threshold,
LED mode
td_OUT4_ICB(on)
td_OUT4_ICB(off)
Output delay time, Driver on,
Bulb mode
Time from CSB going high to
V(OUT4) = 0.1·Vs / 0.9·Vs (on/off);
15
21
15
21
Rload = 16 W
Output delay time, Driver off,
Bulb mode
48
ms
td_OUT4_LED(on) Output delay time, Driver on,
LED mode
Time from CSB going high to
V(OUT4) = 0.1·Vs / 0.9·Vs (on/off);
Rload = 64 W
48
ms
td_OUT4_LED(off) Output delay time, Driver off,
LED mode
48
ms
Ileak_act4
Output leakage current,
Active mode
V(OUT4) = 0 V
V(OUT4) = 0 V
V(OUT4) = VS
−15
−5
mA
mA
Ileak_stdby4
Output leakage current,
Standby mode
Ileak_out_vs4
td_uld4_BULB
Output leakage current
1
mA
Underload blanking delay
Bulb mode
1350
430
200
100
200
50
1910
ms
td_uld4_LED
tdb_old_ICB4
td_old_ICB4
tdb_old_LED4
td_old_LED4
frec4L
Underload blanking delay
LED mode
610
290
160
290
100
2.1
6
ms
ms
Overload shutdown blanking
delay, Bulb mode
Timer started after output activation
Overload shutdown filter time,
Bulb mode
Timer started after blanking delay
elapsed
ms
Overload shutdown blanking
delay, LED mode
Timer started after output activation
ms
Overload shutdown filter time,
LED mode only
Timer started after blanking delay
elapsed
ms
Recovery frequency, slow
recovery mode recovery
CONTROL_3.OCRF = 0
1
kHz
kHz
frec4H
Recovery frequency, fast recovery CONTROL_3.OCRF = 1
mode (LED mode only)
2
dVout4_ICB
dVout4_LED
dVout4_ocr
Slew rate, Bulb mode
Slew rate, LED mode
Vs = 13.5 V, Rload = 16 W
Vs = 13.5 V, Rload = 64 W
Vs = 13.5 V, Rload = 16 W
0.22
0.22
2
V/ms
V/ms
V/ms
Slew rate in overcurrent recovery
mode
1
3
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NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
LED DRIVER OUTPUTS OUT5, OUT6
Ron_out5,6
On−resistance to supply,
HS switch
Tj = 25°C, Iout5,6 = −0.2 A
Tj = 125°C, Iout5,6 = −0.2 A
1.4
W
W
3
−0.3
−4
Ioc5,6
Overcurrent threshold
−0.6
−18
A
Iuld5,6
Underload detection threshold
Output delay time, Driver on
Output delay time, Driver off
mA
ms
ms
mA
td_OUT(on)5,6
td_OUT(off)5,6
Ileak_act5,6
Time from CSB going high to
V(OUT5,6) = 0.1·Vs / 0.9·Vs (on/off)
18
23
48
48
Output leakage current,
Active mode
V(OUT5,6) = 0 V
V(OUT5,6) = 0 V
V(OUT5,6) = VS
−10
−5
Ileak_stdby5,6
Output leakage current,
Standby mode
mA
Ileak_out_vs5,6
td_uld5,6
Output leakage current
1
mA
ms
Underload blanking delay
430
200
16
610
290
50
tdb_old_OUT5,6
td_old_OUT5,6
Overload shutdown blanking delay Timer started after output activation
ms
Overload shutdown filter time
Timer started after blanking delay
elapsed
ms
frec5,6L
frec5,6H
dVout5,6
Recovery frequency, slow
recovery mode
CONTROL_3.OCRF = 0
1
2
4
6
kHz
kHz
V/ms
Recovery frequency, fast recovery CONTROL_3.OCRF = 1
mode
Slew rate
Vs = 13.5 V, Rload = 64 W
0.2
0.1
HEATER OUTPUT OUT7
Ron_out7
On−resistance to supply,
HS switch
Tj = 25°C, Iout7 = −3 A
Tj = 125°C, Iout7 = −3 A
W
W
0.2
−6
Ioc7
Overcurrent threshold
−10
A
Iuld7
Underload detection threshold
Output delay time, Driver on
Output delay time, Driver off
−300
−30
12
mA
ms
ms
mA
td_OUT7(on)
td_OUT7(off)
Ileak_act7
Time from CSB going high to
V(OUT7) = 0.1·Vs / 0.9·Vs (on/off)
3
3
12
Output leakage current,
Active mode
V(OUT7) = 0 V
V(OUT7) = 0 V
V(OUT7) = VS
−10
−5
Ileak_stdby7
Output leakage current,
Standby mode
mA
Ileak_out7_vs
td_uld7
Output leakage current
1
mA
ms
Underload blanking delay
430
30
610
48
tdb_old_OUT7
td_old_OUT7
Overload shutdown blanking delay Timer started after output activation
ms
Overload shutdown filter time
Timer started after blanking delay
elapsed
16
25
ms
frec7L
frec7H
dVout7
Recovery frequency, slow
recovery mode
CONTROL_3.OCRF = 0
CONTROL_3.OCRF = 1
Vs = 13.5 V, Rload = 4 W
1
2
4
6
kHz
kHz
V/ms
Recovery frequency, fast
recovery mode
Slew rate
1.5
2.5
3.5
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9
NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
ELECTROCHROMIC MIRROR CONTROL (ECFB, ECON) (NCV7714 ONLY)
Ron_ecfb
On−resistance to GND, LS switch Tj = 25°C, Iecfb = 0.5 A
Tj = 125°C, Iecfb = 0.5 A
1.6
W
W
3
1.25
3
Ilim_ecfb_src
Vlim_ecfb
Output current limitation to GND
Vds voltage limitation
Vs = 13.5V, Vcc = 5 V
Output enabled
0.75
2
A
V
Iuld_ecfb
Underload detection threshold
Output delay time, LS Driver on
Output delay time, LS Driver off
Output leakage current, LS off
Vs = 13.5 V, Vcc = 5 V
10
20
1
35
12
12
15
10
610
48
50
mA
ms
ms
mA
mA
ms
ms
ms
td_ecfb(on)
td_ecfb(off)
Vs = 13.5 V, Vcc = 5 V,
Rload = 64 W,
V(ECFB) = 0.9·VS / 0.1·VS (on /off)
2
Ileak_ecfb_stdby
Ileak_ecfb_act
td_uld_ecfb
tdb_old_ecfb
td_old_ecfb
Vecfb = Vs, Standby mode
Vecfb = Vs, Active mode
−15
−10
430
30
Underload blanking delay
Overload shutdown blanking delay Timer started after output activation
Overload shutdown blanking delay Timer started after blanking delay
elapsed
16
dVecfb/dt(on/off)
Vctrl_max
Slew rate of ECFB, LS switch
Maximum EC control voltage
Vs = 13.5 V, Vcc = 5 V, Rload = 64 W
CONTROL_2.FSR = 1
CONTROL_2.FSR = 0
1 LSB = 23.8 mV
5
V/ms
V
1.4
1.12
−1
1.6
1.28
1
V
DNL
Differential non linearity
LSB
mV
dV_ecfb
Voltage deviation between target
and ECFB
dV_ecfb = Vtarget – Vecfb,
Iecon < 1 mA
gain
offset
−5%
−1 LSB
+5%
+1 LSB
dV_ecfb_lo
dV_ecfb_hi
Difference voltage between target dV_ecfb = Vtarget – Vecfb,
120
mV
mV
and ECFB sets flag if Vecfb is
below target
Toggle bit STATUS_2.ECLO = 1
Difference voltage between target dV_ecfb = Vtarget – Vecfb,
−120
and ECFB sets flag if Vecfb is
above target
Toggle bit STATUS_2.ECHI = 1
Vecon_min_hi
Vecon_max_lo
Iecon
ECON output voltage range
Iecon = −10 mA
Iecon = 10 mA
4.5
0
5.5
0.7
V
V
ECON output current capability
Vtarget > Vecfb + 500 mV,
Vecon = 3.5 V
−100
−10
mA
Vtarget < Vecfb – 500 mV,
Vecon = 0.5 V, Vtarget = 1 LSB,
Vecfb = 0.5 V
10
100
5
mA
kW
Recon_pd
Iq_econ
Pull−down resistance at ECON in
fast discharge mode
Vecon = 0.7 V,
CONTROL_1.ECEN = 1,
CONTROL_1.LSECFB = 1,
CONTROL_1.DAC[5:0] = 0
ECON quiescent current
Vecon = Vs,
CONTROL_1.ECEN = 0
1
mA
t_disc
t_rec
Auto−discharge pulse width
Auto−discharge blanking time
Config.LSPWM=1
Config.LSPWM=1
Config.LSPWM=1
230
2.25
350
300
3
360
3.75
450
ms
ms
mV
Vthdisc_abs
PWM discharge threshold level
V(ECON) (Note 5)
400
Vthdisc_diff
PWM discharge threshold level
V(ECON) – V(ECFB) (Note 5)
Config.LSPWM=1
−50
0
50
mV
5. If V(ECON) < Vthdisc_abs or V(ECON)−V(ECFB) < Vthdisc_diff then ECON_LOW =1; see description in paragraph Controller for Electro−
chromic Glass
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10
NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
CURRENT SENSE MONITOR OUTPUT ISOUT/PWM2
Vis
Current Sense output functional
voltage range
Vcc = 5 V, Vs = 8−20 V
0
Vcc –
0.5
V
Kis
Current Sense output ratio OUT7
and 4 (low on−resistance bulb
mode)
K = Iout / Iis,
0 V v Vis v 4.5 V, Vcc = 5 V
10000
2000
(Note 6)
Current Sense output ratio OUT5/6
and 4 (high on−resistance LED
mode)
Iis,acc
Current Sense output accuracy
OUT4 (low on−resistance bulb
mode)
0.3 V v Vis v 4.5 V, Vcc = 5 V
−2% −
6% FS
23% −
4% FS
Iout4 = 0.5−1.3 A
(Notes 7, 8)
Current Sense output accuracy
OUT4 (high on−resistance LED
mode)
0.3 V v Vis v 4.5 V, Vcc = 5 V
−6% −
4% FS
21% −
4% FS
Iout4 = 0.1−0.28 A
Current Sense output accuracy
OUT5/6
0.3 V v Vis v 4.5 V, Vcc = 5 V
−3% −
6% FS
17% −
3% FS
Iout5/6 = 0.1−0.4 A
Current Sense output accuracy
OUT7
0.3 V v Vis v 4.5 V, Vcc = 5 V
−7% −
5% FS
12% −
1% FS
Iout7 = 0.5−5.9 A
tis_blank
tis
Current Sense blanking time
Current Sense settling time
50
65
ms
ms
0 V to FSR (full scale range)
230
264
6. Kis trimmed at 150°C to higher value of spec range to be more centered over temp range.
7. Current sense output accuracy = Isout−Isout_ideal relative to Isout_ideal
8. FS (Full scale) = Ioutmax/Kis
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NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DIGITAL INPUTS CSB, SCLK, PWM1/2, SI
Vinl
Input low level
Vcc = 5 V
Vcc = 5 V
0.3·Vcc
V
V
Vinh
Input high level
Input hysteresis
CSB pull−up resistor
0.7·Vcc
500
Vin_hyst
Rcsb_pu
mV
kW
Vcc = 5 V,
0 V < Vcsb < 0.7·Vcc
30
120
60
60
60
60
250
220
220
220
220
Rsclk_pd
Rsi_pd
SCLK pull−down resistor
SI pull−down resistor
Vcc = 5 V,
Vsclk = 1.5 V
30
30
30
30
kW
kW
kW
kW
Vcc = 5 V,
Vsi = 1.5 V
Rpwm1_pd
Rpwm2_pd
PWM1 pull−down resistor
PWM2 pull−down resistor
Vcc = 5 V,
Vpwm1 = 1.5 V
Vcc = 5 V,
Vpwm2 = 1.5 V,
current sense disabled
Ileak_isout
Output leakage current
Pin capacitance
current sense enabled
−2
2
mA
Ccsb/sclk/pwm1/2
0 V < Vcc < 5.25 V (Note 9)
10
pF
DIGITAL INPUTS CSB, SCLK, SI; TIMING
tsclk
tsclk_h
tsclk_l
Clock period
Vcc = 5 V
1000
ns
ns
ns
ns
Clock high time
Clock low time
115
115
400
tset_csb
CSB setup time, CSB low before
rising edge of SCLK
tset_sclk
SCLK setup time, SCLK low
before rising edge of CSB
400
ns
tset_si
thold_si
tr_in
SI setup time
SI hold time
200
200
ns
ns
ns
Rise time of input signal SI, SCLK,
CSB
100
100
10
tf_in
Fall time of input signal SI, SCLK,
CSB
ns
tcsb_hi_stdby
Minimum CSB high time, switching Transfer of SPI−command to input
from Standby mode
5
2
ms
register, valid before tsact mode
transition delay expires
tcsb_hi_min
Minimum CSB high time,
Active mode
4
ms
9. Values based on design and/or characterization
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12
NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
DIGITAL OUTPUT SO
Vsol
Parameter
Test Conditions
Min
Typ
Max
Unit
Output low level
Iso = 5 mA
0.2·Vcc
V
V
Vsoh
Output high level
Iso = −5 mA
0.8·Vcc
Ileak_so
Tristate leakage current
Vcsb = Vcc,
0 V < Vso < Vcc
−10
10
10
mA
Cso
Tristate input capacitance
Vcsb = Vcc,
pF
0 V < Vcc < 5.25 V (Note 10)
DIGITAL OUTPUT SO; TIMING
tr_so
tf_so
SO rise time
SO fall time
Cso = 100 pF
Cso = 100 pF
80
50
140
100
250
ns
ns
ns
ten_so_tril
SO enable time from tristate to low Cso = 100 pF, Iload = 1 mA,
100
level
pull−up load to VCC
tdis_so_ltri
ten_so_trih
tdis_so_htri
td_so
SO disable time from low level to
tristate
Cso = 100 pF, Iload = 4 mA,
pull−up load to VCC
380
100
380
50
450
250
450
250
ns
ns
ns
ns
SO enable time from tristate to
high level
Cso = 100 pF, Iload = −1 mA,
pull−down load to GND
SO disable time from high level to Cso = 100 pF, Iload = −4 mA,
tristate
pull−down load to GND
SO delay time
Vso < 0.3·Vcc, or Vso > 0.7·Vcc,
Cso = 100 pF
10.Values based on design and/or characterization
0.8 • V
CC
0.2 • V
CSB
CC
t
t
t
set_csb
sclk
set_sclk
t
t
ri_in
csb_hi_min
t
f_in
0.8 • V
CC
SCLK
0.2 • V
0.2 • V
CC
CC
t
t
sclk_h
sclk_l
t
set_si
t
hold_si
0.8 • V
CC
SI
Valid
Valid
Valid
t
d_so
t
en_so_trix
0.7 • V
0.3 • V
0.7 • V
CC
CC
Valid
SO
Valid
Valid
CC
Figure 4. SPI Signals Timing Parameters
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13
NCV7704, NCV7714
Table 4. ELECTRICAL CHARACTERISTICS 4.5 V < Vcc < 5.25 V, 8 V < Vs < 18 V, −40°C < Tj < 150°C; unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
160
180
Unit
THERMAL PROTECTION
Tjtw_on
Tjtw_hys
Tjsd_on
Temperature warning threshold
Thermal warning hysteresis
Junction temperature
140
°C
°C
°C
5
Thermal shutdown threshold,
Tj increasing
Junction temperature
Junction temperature
160
160
Tjsd_off
Thermal shutdown threshold,
Tj decreasing
°C
Tjsd_hys
Thermal shutdown hysteresis
5
°C
°C
Tjsdtw_delta
Temperature difference between
warning and shutdown threshold
20
td_tx
Filter time for thermal warning and TW / TSD Global Status bits
shutdown
10
100
ms
OPERATING MODES TIMING
tact
tsact
tacts
Time delay for mode change from SPI communication ready after Vcc
30
ms
ms
ms
Unpowered mode into Standby
mode
reached Vuv_vcc(off) threshold
Time delay for mode change from Time until output drivers are enabled
190
360
300
Standby mode into Active mode
after CSB going to high and
CONTROL_0.MODE = 1
Time delay for mode change from Time until output drivers are disabled
Active mode into Standby mode via after CSB going to high and
SPI
CONTROL_0.MODE = 0
INTERNAL PWM CONTROL UNIT (OUT4 – OUT6)
PWMlo
PWMhi
PWM frequency, low selection
PWM frequency, high selection
CONTROL_2.PWMI=1,
PWMx.FSELx=0
135
175
360
170
225
440
190
250
500
Hz
Hz
Hz
CONTROL_2.PWMI=1,
PWMx.FSELx=1
PWMlo_boost
Boosted PWM frequency, low
selection
CONTROL_2.PWMI=1,
CONFIG.FEN_BOOST=1,
PWM_4.FSEL_BOOST=1,
PWMx.FSELx=0
PWMhi_boost
Boosted PWM frequency, high
selection
CONTROL_2.PWMI=1,
CONFIG.FEN_BOOST=1,
PWM_4.FSEL_BOOST=1,
PWMx.FSELx=1
440
550
630
Hz
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14
NCV7704, NCV7714
DETAILED OPERATING AND PIN DESCRIPTION
General
undervoltage threshold Vuv_vs(off) (Vs undervoltage
threshold) all output stages are switched to high−impedance
state and the global status bit UOV_OC is set. This bit is a
multi information bit in the Global Status Byte which is set
in case of overcurrent, Vs over− and undervoltage. In case
of undervoltage the status bit STATUS_2.VSUV is set, too.
Bit CONTROL_3.OVUVR (Vs under−/overvoltage
recovery behavior) can be used to select the desired recovery
behavior after a Vs under−voltage event. In case of OVUVR
= 0, all output stages return to their programmed state as
soon as Vs recovers back to its normal operating range. If
OVUVR is set, the automatic recovery function is disabled
thus the output stages will remain in high−impedance
condition until the status bits have been cleared by the
microcontroller. To avoid high current oscillations in case of
output short to GND and low Vs voltage conditions, it is
recommended to disable the Vs−auto−recovery by setting
OVUVR = 1.
The NCV7704/NCV7714 provides three half−bridge
drivers, four independent high−side outputs and a
programmable PWM control unit for free configuration.
Strict adherence to integrated circuit die temperature is
necessary, with a static maximum die temperature of 150°C.
This may limit the number of drivers enabled at one time.
Output drive control and fault reporting are handled via the
SPI (Serial Peripheral Interface) port. A SPI−controlled
mode control provides a low quiescent sleep current mode
when the device is not being utilized. A pull down is
provided on the SI and SCLK inputs to ensure they default
to a low state in the event of a severed input signal. A pull−up
is provided on the CSB input disabling SPI communication
in the event of an open CSB input.
Supply Concept
Power Supply Scheme − VS and VCC
The Vs power supply voltage is used to supply the half
bridges and the high−side drivers. An all−internal
chargepump is implemented to provide the gate−drive
voltage for the n−channel type high−side transistors. The
VCC voltage is used to supply the logic section of the IC,
including the SPI interface.
Due to the independent logic supply voltage the control
and status information will not be lost in case of a loss of Vs
supply voltage. The device is designed to operate inside the
specified parametric limits if the VCC supply voltage is
within the specified voltage range (4.5 V to 5.25 V).
Between the operational level and the VCC undervoltage
threshold level (Vuv_VCC) it is guaranteed that the device
remains in a safe functional state without any inadvertent
change to logic information.
Chargepump
In Standby mode, the chargepump is disabled. After
enabling the device by setting bit CONTROL_0.MODE to
active (1), the internal oscillator is started and the voltage at
the CHP output pin begins to increase. The output drivers are
enabled after a delay of tsact once MODE was set to active.
Driver Outputs
Output PWM Control
For all half−bridge outputs as well as the high−side outputs
the device features the possibility to logically combine the
SPI−setting with a PWM signal that can be provided to the
inputs PWM1 and ISOUT/PWM2, respectively. Each of the
outputs has a fixed PWM signal assigned which is shown in
Table 5. The PWM modulation is enabled by the respective
bits in the control registers (CONTROL_2.OUTx_PWMx
and CONTROL_3.OUTx_PWMx). In case of using pin
ISOUT/PWM2, the application design has to take care of
either disabling the current sense feature or to provide
sufficient overdrive capability to maintain proper logic input
levels for the PWM input.
In addition to the external signal control, all lighting outputs
(OUT4−6) can also be PWM controlled via an internal PWM
generator unit. Bits PWMx.FSELx individually select the PWM
frequency between 170 Hz and 225 Hz or 440 Hz and 550 Hz
if the boost setting is applied (CONFIG.FEN_BOOST=1 and
PWM_4.FSEL_BOOST=1). The duty cycle can be
programmed with 7−bits resolution PWMx.PW[6:0].
The resolution can be increased to 9 bits by setting bit
CONFIG.PWM_RESEN=1. Additional two LSB PWM
bits for all the outputs are located in register PWM_4. The
selection between the different signal sources for these
Device / Module Ground Concept
The high−side output stages OUT4−7 are designed to
handle DC output voltage conditions down to −0.3 V and
allow for short negative transient currents due to parasitic
line inductances. Therefore the application has to take care
that these ratings are not violated under abnormal operating
conditions (module loss of GND, ground shift if load
connected to external GND) by either implementing
external bypass diodes connected to GND or a direct
connection between load−GND and module−GND. Since
these output stages are designed to drive resistive loads,
restrictions on maximum inductance / clamping energy apply.
The heat slug is not hard−connected to internal GND rail.
It has to be connected externally.
Power Up/Down Control
In order to prevent uncontrolled operation of the device
during power up/down, an undervoltage lockout feature is
outputs
is
performed
by
programming
bit
implemented. Both supply voltages (V
and Vs) are
CC
CONTROL_2.PWMI. Default value is 0 (external signal
source). The general principle of the PWM generation
control scheme is shown in Figure 5.
monitored for undervoltage conditions supporting a safe
power−up transition. When Vs drops below the
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15
NCV7704, NCV7714
Table 5. PWM CONTROL SCHEME
PWM Control Input
CONTROL_2.PWMI = 1
CONFIG.PWM_RESEN=0
PWM1
CONFIG.PWM_RESEN=1
PWM1
Output
OUT1
OUT2
OUT3
OUT4
OUT5
CONTROL_2.PWMI = 0
PWM1
PWM1
PWM1
PWM1
PWM1
PWM1
PWM1
ISOUT/PWM2
PWM1
PWM_4.PW4[6:0]
PWM_5/6.PW5[6:0]
PWM_4.PW4[6:−2]
PWM_5/6.PW5[6:0] &
PWM_4.PW5[−1:−2]
OUT6
OUT7
ISOUT/PWM2
PWM1
PWM_5/6.PW6[6:0]
PWM1
PWM_5/6.PW6[6:0] &
PWM_4.PW6[−1:−2]
PWM1
CONTROL_2/3.OUTx_PWMx
PWM1/2
PWM enable
external PWM source
H… Enable Output
f4 (PWMhi _boost)
&
f3 (PWMlo _boost)
H … CT
=0
internal
clock
Counter 9 Bit
S
R
Prescaler
internal PWM source
f2 (PWMhi )
f1 (PWMlo )
9
PWM_x/y.FSELx
A
B
CONTROL_2.PWMI
A>B
9
CONFIG.FEN_BOOST
PWM_4.FSEL_BOOST
CONFIG.PWM_RESEN
&
7
2
PWM_x/y.PWx[6:0]
SPI
PWM_4.PWx[−1:−2]
SPI
Figure 5. PWM Generation Diagram
Programmable Soft−start Function to Drive Loads with
Inrush Current Behavior
recommended to only enable auto−recovery for a minimum
amount of time to drive the connected load into a steady state
condition. After turning off the auto−recovery function, the
respective channel is automatically disabled if the overload
condition still persists.
Loads with startup currents higher than the overcurrent
limits (e.g. inrush current of bulbs, block current of motors
and cold resistance of heaters) can be driven using the
programmable soft−start function (Overcurrent auto−recovery
mode). Each output driver provides a corresponding
overcurrent recovery bit (CONTROL_2/3.OCRx) to control
the output behavior in case of a detected overcurrent event.
If auto−recovery is enabled, the device automatically
re−enables the output after a programmable recovery time.
For all half−bridge outputs as well as the high−side outputs
OUT4−7 and OUT4 in LED mode, the recovery frequency
can be selected via SPI. OUT4 in bulb mode provides a fixed
recovery frequency only. The PWM modulated current will
provide sufficient average current to power up the load (e.g.
heat up the bulb) until the load reaches a steady state
condition. The device itself cannot distinguish between a
real overload and a non linear load like a bulb. Therefore a
real overload condition can only be qualified by time. It is
Inductive Loads
Each half bridge (OUT1−3) is built by internally
connected low−side and high−side N−MOS transistors. Due
to the built−in body diodes of the output transistors,
inductive loads can be driven at the outputs without external
free−wheeling diodes. The high−side drivers OUT4 to
OUT7 are designed to drive resistive loads. Therefore only
a limited clamping energy (W < 1 mJ) can be dissipated by
the device. For inductive loads (L > 100 mH) an external
freewheeling diode connected between GND and the
corresponding output is required.
The low−side driver at ECFB does not feature any
freewheeling diode or clamping structure to handle
inductive loads (NCV7714 only).
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NCV7704, NCV7714
Current Sensing
CONTROL_2.FSR to “1”, the maximum output voltage is
1.5 V. The resolution of the DAC output voltage is
independent of the full−scale−range selection.
Current Sense Output / PWM2 Input (Bidirectional Pin
ISOUT/PWM2)
The charging of the mirror (positive slope) is determined
by the positive slew rate of the transconductance amplifier
and the compensation capacitor, while in case of capacitive
loads, the negative slope is mainly determined by the current
consumption thru the load and its capacitance. To allow fast
settling time changing from higher to lower output voltage
values, the device provides two modes of operation:
The current sense output allows a more precise analysis of
the actual state of the load rather than the basic detection of
an under− or overload condition. The sense output provides
an image of the actual load current at the selected high side
driver transistor. The current monitor function is available
for the high current high−side output (OUT7) as well as for
the all bulb and LED outputs (OUT4−6).
The current sense ratio is fixed to 1/10000 for the low
resistance outputs OUT4 (bulb mode) and OUT7 and for the
high ohmic outputs OUT5/6 and OUT4 (LED mode) to
1/2000. To prevent from false readouts, the signal at pin
ISOUT is blanked after switching on the driver until correct
settlement of the circuitry (max. 65 ms). Bits
CONTROL_3.IS[3:0] are used to select the output to be
multiplexed to the current sense output.
The NCV7704/NCV7714 provides a sample−and−hold
functionality for the current sense output to enable precise
and simple load current diagnostics even during PWM
operation of the respective output. While in active high−side
output state, the current provided at ISOUT reflects a
(low−pass−filtered) image of the actual output current, the
IS−output current is sampled and held constant as soon as the
HS output transistor is commanded off via PWM
(high−impedance). In case no previous current information
is available in the Sample−and−hold stage (current sense
channel changed while actual channel is commanded off)
the sample stage is reset so that it reflects zero output current.
1. Fast discharge: When the target output voltage is
set to 0 V and bit CONTROL_1.LS_ECFB is set,
the voltage at pin ECFB is pulled to ground by a
1.6 W low−side switch.
2. PWM discharge: In case of PWM discharge being
activated (CONFIG.ECM_LSPWM = 1 and
CONTROL_1.LS_ECFB = 1) (Figure 6):
a. The circuit regulation starts in normal
regulation. The DAC value is turned to new
lower value.
b. If the loop is detected out of regulation for a
time longer than t_rec (~3 ms), the ECON
voltage is detected low (internal signal
ECON_LOW = 1), the regulator is switched off
(DAC voltage at 0) and the fast discharge
transistor is activated for ~300 ms (t_disc).
During this fast discharge, the ECON output is
pulled low to prevent from shoot−thru currents.
c. At the end of the discharge pulse t_disc the fast
discharge is switched off and the regulation
loop is activated again (with DAC to the correct
wanted value), so the loop goes back to step b.)
and the ECON_LOW comparator is observed
again. Before starting a discharge pulse, the
ECLO and ECHI comparator data is latched.
Electro Chromic Mirror (NCV7714 ONLY)
Controller for Electro−chromic Glass
The voltage of the electro−chromic element connected at
pin ECFB can be controlled to a target value which is set by
Control Register 1 (bits CONTROL_1.DAC[5:0]). Setting
bit CONTROL_1.ECEN enables this function. At the same
time OUT6 is enabled, regardless of its own control bit
CONTROL_1.HS6 and the respective PWM setting. An
on−chip differential amplifier is used to control an external
logic−level N−MOS pass device that delivers the power to
the electro−chromic element. The target voltage at ECFB is
binary coded with a selectable full scale range (bit
CONTROL_2.FSR). The default clamping value for the
output voltage (CONTROL_2.FSR = 0) is 1.2 V, by setting
The feedback loop out of regulation is monitored by
comparing V(ECON) versus V(ECFB) and versus 400 mV.
If the regulation is activated and ECON is below ECFB, or
below 400 mV, then the loop is detected as out of regulation
and internal signal ECON_LOW is made 1. By activating
the PWM discharge feature, the overcurrent recovery
function is automatically disabled, regardless of the setting
in CONTROL_2.OC_ECFB.
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17
NCV7704, NCV7714
new ECM target
voltage requested
CSB
V(ECON)
Sampling of
ECON−ECFB
voltage
Vtarget + offset
Vtarget − offset
V(ECFB)
V(ECON)
V(ECFB)
Vtarget,
V(ECFB),
V(ECON)
Vtarget
(CONTROL_1.DAC)
tdisc
disabled
trec
enabled
(on)
LS_ECFB
trec
trec
(off)
switch status
disabled
(5 kW to GND)
ECON status
enabled
enabled
ECON_LOW
(internal signal)
V(ECON) < V(ECFB),
out of regulation
Figure 6. PWM Discharge Mode for ECFB
The controller provides a chip−internal diode from ECFB
(Anode) to pin ECON (Cathode) to protect the external
MOSFET. A capacitor of at least 4.7 nF has to be added to
pin ECON for stability of the control loop. It is
recommended to place 220 nF capacitor between ECFB and
ground to increase the stability.
The status of the voltage control loop is reported via SPI.
Bit STATUS_2.ECHI = 1 indicates that the voltage on ECFB
is higher than the programmed target value,
STATUS_2.ECLO = 1 indicates that the ECFB voltage is
below the programmed value. Both status bits are valid if
they are stable for at least 150 ms (settling time of the
regulation loop). If PWM discharge is enabled
(CONFIG.ECM_LSPWM = 1), STATUS_2.ECHI is
latched at the end of the discharge cycle, therefore if set it
indicates that the device is in active discharge operation.
Since OUT6 is the output of a high−side driver, it contains
the same diagnostic functions as the other high−side drivers
(e.g. switch−off during overcurrent condition). In
electro−chrome mode, OUT6 can’t be controlled by PWM.
For noise immunity reasons, it is recommended to place the
loop capacitors at ECON as well as another capacitor
between ECFB and GND as close as possible to the
respective pins.
VS
NCV7714
OUT6
ECON
DAC−EC Control
6
DAC
SI
SCLK
SPI
Electro−Chromic
CSB
4.7 nF
Mirror
ECM
SO
ECFB
Auto
discharge
LS Discharge
Transistor
220 nF
Figure 7. Electro Chromic Mirror Application Diagram
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18
NCV7704, NCV7714
Openload (Underload) Detection
Diagnostic Functions
The openload detection monitors the load current in the
output stage while the transistor is active. If the load current
is below the openload detection threshold for at least td_uld,
the corresponding bit (ULDx) is set in the status registers
STATUS_1/2. The status of the output remains unchanged.
Once set, ULDx remains set regardless of the actual load
condition. It has to be reset by a read&write access to the
corresponding status register.
All diagnostic functions (overcurrent, underload, power
supply monitoring, thermal warning and thermal shutdown)
are internally filtered. The failure condition has to be valid
for the minimum specified filtering time (td_old, td_uld,
td_uvov and td_tx) before the corresponding status bit in the
status register is set. The filter function is used to improve
the noise immunity of the device. The undercurrent and
temperature warning functions are intended for information
purpose and do not affect the state of the output drivers. An
overcurrent condition disables the corresponding output
driver while a thermal shutdown event disables all outputs
into high impedance state. Depending on the setting of the
overcurrent recovery bits in the input register, the driver can
either perform an auto−retry or remain latched off until the
microcontroller clears the corresponding status bits.
Overtemperature shutdown is latch−off only, without
auto−retry functionality.
Overload Detection
An overcurrent condition is indicated by the flag
(UOV_OC) in the Global Status Byte after a filter time of at
least td_old. The channel dependent overcurrent flags are set
in the status registers (STATUS_0/2.OCx) and the
corresponding driver is switched into high impedance state
to protect the device. Each low−side and high−side driver
stage provides its own overcurrent flag. Resetting this
overcurrent flag automatically re−enables the respective
output (provided it is still enabled thru the Control register).
If the over current recovery function is enabled, the internal
chip logic automatically resets the overcurrent flag after a
fixed delay time, generating a PWM modulated current with
a programmable duty cycle. Otherwise the status bits have
to be cleared by the microcontroller by a read&clear access
to the corresponding status register.
Overvoltage / Undervoltage Shutdown
If the supply voltage Vs rises above the switch off voltage
Vov_vs(off) or falls below Vuv_vs(off), all output
transistors are switched to high−impedance state and the
global status bit UOV_OC (multi information) is set. The
status flag STATUS_2.VSOV, resp. STATUS_2.VSUV is
set, too, to log the over−/under−voltage event. The bit
CONTROL_3.OVUVR can be used to determine the
recovery behavior once the Vs supply voltage gets back into
the specified nominal operating range. OVUVR = 0 enables
auto−recovery, with OVUVR = 1 the output stages remain
in high impedance condition until the status flags have been
cleared. Once set, STATUS2.VSOV / VSUV can only be
reset by a read&clear access to the status register
STATUS_2.
Cross−current Protection
All six half−bridges are protected against cross−currents
by internal circuitry. If one driver is turned off (LS or HS),
the activation of the other driver of the same output will be
automatically delayed by the cross current protection
mechanism until the active driver is safely turned off.
Mode Control
Thermal Warning and Overtemperature Shutdown
The device provides a dual−stage overtemperature
protection. If the junction temperature rises above Tjtw_on,
a temperature warning flag (TW) is set in the Global Status
Byte and can be read via SPI. The control software can then
react onto this overload condition by a controlled disable of
individual outputs. If however the junction temperature
reaches the second threshold Tjsd_on, the thermal shutdown
bit TSD is set in the Global Status Byte and all output stages
are switched into high impedance state to protect the device.
The minimum shutdown delay for overtemperature is td_tx.
The output channels can be re−enabled after the device
cooled down and the TSD flag has been reset by the
microcontroller by setting CONTROL_0.MODE = 0.
Wake−up and Mode Control
Two different modes are available:
• Active mode
• Standby mode
After power−up of VCC the device starts in Standby
mode. Pulling the chip−select signal CSB to low level causes
the device to change into Active mode (analog part active).
After at least 10 ms delay, the first SPI communication is
valid and bit CONTROL_0.MODE can be used to set the
desired mode of operation. If bit MODE remains reset (0),
the device returns to the Standby mode after an internal
delay of max. 8 ms, clearing all register content and setting
all output stages into high impedance state.
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NCV7704, NCV7714
VCC Power−up
Delay (tact)
Output stages Hi−Z
Register content cleared
SPI not ready
SPI Control
General Description
The 4−wire SPI interface establishes a full duplex
synchronous serial communication link between the
NCV7704/NCV7714 and the application’s microcontroller.
The NCV7704/NCV7714 always operates in slave mode
whereas the controller provides the master function. A SPI
access is performed by applying an active−low slave select
signal at CSB. SI is the data input, SO the data output. The
SPI master provides the clock to the NCV7704/NCV7714
via the SCLK input. The digital input data is sampled at the
rising edge at SCLK. The data output SO is in high
impedance state (tri−state) when CSB is high. To readout the
global error flag without sending a complete SPI frame, SO
indicates the corresponding value as soon as CSB is set to
active. With the first rising edge at SCLK after the
high−to−low transition of CSB, the content of the selected
register is transferred into the output shift register.
MODE = 1
or
CSB = 0
Delay (tsact)
MODE = 1
CSB = 0
CSB = 1
and
MODE = 0
Standby
Output stages High−Z
Active
Output stages controlled
thru output registers
Register content cleared
CSB = 0
MODE = 0
and
CSB = 1
Delay timer
expired
Delay (tacts)
Output stages controlled
thru output registers
Register content valid
Figure 8. Mode Transitions Diagram
The NCV7704/NCV7714 provides four control registers
(CONTROL_0/1/2/3), two PWM configuration registers
(PWM_4 and PWM_5/6), three status registers
(STATUS_0/1/2) and one general configuration register
(CONFIG). Each of these register contains 16−bit data,
together with the 8−bit frame header (access type, register
address), the SPI frame length is therefore 24 bits. In
addition to the read/write accessible registers, the
NCV7704/NCV7714 provides five 8−bit ID registers
(ID_HEADER, ID_VERSION, ID_CODE1/2 and
ID_SPI−FRAME) with 8−bit data length. The content of
these registers can still be read out by a 24−bit access, the
data is then transferred in the MSB section of the data frame.
CSB
t
t
0
1
2
3
4
5
21 22 23
SCLK
D18
D23 D22 D21 D20 D19
CSB = 0
D2 D1 D0
SI
t
t
CONTROL_0.MODE = 1
active
Mode
standby
active
SPI Frame Format
Figure 10 shows the general format of the
NCV7704/NCV7714 SPI frame.
CSB = 0
&
MODE = 0
Mode
standby
active
standby
t
< 8 ms
Figure 9. Mode Timing Diagram
Access
Type
Register Address
Input Data
Input Data
CSB
SCLK
OC1
FLT
OC0
TF
A5
A4
A3
A2
A1
A0
DI6
DI2
DI1
DI0
DI7
SI
UOV
_OC
SO
RES
TSD
TW
ULD NRDY DO7
DO6
DO2
DO1
DO0
X
Device Status Bits
Address−dependent Data
Figure 10. SPI Frame Format
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20
NCV7704, NCV7714
24−bit SPI Interface
way. The device features a stuck−at−one detection, thus
upon detection of a command = FFFFFFh, the device will be
forced into the Standby mode. All output drivers are
switched off.
Both 24−bit input and output data are MSB first. Each
SPI−input frame consists of a command byte followed by
two data bytes. The data returned on SO within the same
frame always starts with the global status byte. It provides
general status information about the device. It is then
followed by 2 data bytes (in−frame response) which content
depends on the information transmitted in the command
byte. For write access cycles, the global status byte is
followed by the previous content of the addressed register.
Serial Data Out (SO)
The SO data output driver is activated by a logical low
level at the CSB input and will go from high impedance to
a low or high level depending on the global status bit, FLT
(Global Error Flag). The first rising edge of the SCLK input
after a high to low transition of the CSB pin will transfer the
content of the selected register into the data out shift register.
Each subsequent falling edge of the SCLK will shift the next
bit thru SO out of the device.
Chip Select Bar (CSB)
CSB is the SPI input pin which controls the data transfer
of the device. When CSB is high, no data transfer is possible
and the output pin SO is set to high impedance. If CSB goes
low, the serial data transfer is allowed and can be started. The
communication ends when CSB goes high again.
Command Byte / Global Status Byte
Each communication frame starts with a command byte
(Table 6). It consists of an operation code (OP[1:0], Table 7)
which specifies the type of operation (Read, Write, Read &
Clear, Readout Device Information) and a six bit address
(A[5:0], Table 8). If less than six address bits are required,
the remaining bits are unused but are reserved. Both Write
and Read mode allow access to the internal registers of the
device. A “Read & Clear”−access is used to read a status
register and subsequently clear its content. The “Read
Device Information” allows to read out device related
information such as ID−Header, Product Code, Silicon
Version and Category and the SPI−frame ID. While
receiving the command byte, the global status byte is
transmitted to the microcontroller. It contains global fault
information for the device, as shown in Table 10.
Serial Clock (SCLK)
If CSB is set to low, the communication starts with the
rising edge of the SCLK input pin. At each rising edge of
SCLK, the data at the input pin Serial IN (SI) is latched. The
data is shifted out thru the data output pin SO after the falling
edges of SCLK. The clock SCLK must be active only within
the frame time, means when CSB is low. The correct
transmission is monitored by counting the number of clock
pulses during the communication frame. If the number of
SCLK pulses does not correspond to the frame width
indicated in the SPI−frame−ID (Chip ID Register, address
3Eh) the frame will be ignored and the communication
failure bit “TF” in the global status byte will be set. Due to
this safety functionality, daisy chaining the SPI is not
possible. Instead, a parallel operation of the SPI bus by
controlling the CSB signal of the connected ICs is
recommended.
ID Register
Chip ID Information is stored in five special 8−bit ID
registers (Table 9). The content can be read out at the
beginning of the communication.
Serial Data In (SI)
During the rising edges of SCLK (CSB is low), the data
is transferred into the device thru the input pin SI in a serial
Table 6. COMMAND BYTE / GLOBAL STATUS BYTE STRUCTURE
Command Byte (IN) / Global Status Byte (OUT)
23
OP1
FLT
1
22
OP0
TF
0
21
A5
20
A4
TSD
0
19
A3
TW
0
18
17
A1
ULD
0
16
A0
Bit
NCV7704/14 IN
NCV7704/14 OUT
Reset Value
A2
UOV_OC
0
RESB
0
NRDY
1
Table 7. COMMAND BYTE, ACCESS MODE
OP1
OP0
Description
0
0
1
1
0
1
0
1
Write Access (W)
Read Access (R)
Read and Clear Access (RC)
Read Device ID (RDID)
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NCV7704, NCV7714
Table 8. COMMAND BYTE, REGISTER ADDRESS
A[5:0]
Access
Description
Content
Control Register
CONTROL_0
00h
R/W
Device mode control, Bridge outputs control
Control Register
CONTROL_1
01h
02h
03h
08h
09h
10h
11h
12h
3Fh
R/W
R/W
High−side outputs control, ECM control (NCV7714 only)
Bridge outputs recovery control, PWM enable, ECM setup (NCV7714 only)
High−side outputs recovery control, PWM enable, Current Sense selection
PWM control register for OUT4
Control Register
CONTROL_2
Control Register
CONTROL_3
R/W
PWM Control Register
PWM_4
R/W
PWM Control Register
PWM_5/6
R/W
PWM control register for OUT5/6
Status Register
STATUS_0
R/RC
R/RC
R/RC
R/W
Bridge outputs Overcurrent diagnosis
Status Register
STATUS_1
Bridge outputs Underload diagnosis
Status Register
STATUS_2
HS outputs Overcurrent and Underload diagnosis, Vs Over− and Under-
voltage, EC−mirror (NCV7714 only)
Configuration Register
CONFIG
Mask bits for global fault bits
Table 9. CHIP ID INFORMATION
A[5:0]
00h
Access
RDID
RDID
RDID
RDID
Description
ID header
Content
4300h
0000h
7700h
01h
Version
02h
Product Code 1
Product Code 2
03h
0400h (NCV7704)
0E00h (NCV7714)
3Eh
RDID
SPI−Frame ID
0200h
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NCV7704, NCV7714
Table 10. GLOBAL STATUS BYTE CONTENT
FLT
Global Fault Bit
Failures of the Global Status Byte, bits [6:0] are always linked to the Global Fault Bit FLT. This bit
is generated by an OR combination of all failure bits of the device (RESB inverted). It is reflected
via the SO pin while CSB is held low and NO clock signal is present (before first positive edge of
SCLK). The flag will remain valid as long as CSB is held low. This operation does not cause the
Transmission error Flag in the Global Status Byte to be set. Signals TW and ULD can be masked.
0
1
No fault Condition
Fault Condition
TF
0
SPI Transmission Error
No Error
Error
If the number of clock pulses within the previous frame was unequal 0 (FLT polling) or 24. The
frame was ignored and this flag was set.
1
RESB
Reset Bar (Active low)
0
1
Reset
Bit is set to “0” after a Power−on−Reset or a stuck−at−1 fault at SI (SPI−input data = FFFFFFh)
has been detected. All outputs are disabled.
Normal Operation
TSD
Overtemperature Shutdown
Thermal Shutdown Status indication. In case of a Thermal Shutdown, all output drivers including
the charge pump output are deactivated (high impedance). The TSD bit has to be cleared thru a
SW reset to reactivate the output drivers and the chargepump output.
0
1
No Thermal Shutdown
Thermal Shutdown
TW
0
Thermal Warning
No Thermal Warning
Thermal Warning
This bit indicates a pre−warning level of the junction temperature. It is maskable by the
Configuration Register (CONFIG.NO_TW).
1
UOV_OC
VS Monitoring, Overcurrent Status
0
1
No Fault
Fault
This bit represents a logical OR combination of under−/overvoltage signals (VS) and overcurrent
signals.
ULD
Underload
This bit represents a logical OR combination of all underload signals. It is maskable by the
Configuration Register (CONFIG.NO_ULDx). It is also possible to deactivate this flag for HS1 or
LS1, only (CONFIG.NO_ULD_HS1/LS1).
0
1
No Underload
Underload
NRDY
Not Ready
0
1
Device Ready
After transition from Standby to Active mode, an internal timer is started to allow the internal
chargepump to settle before any outputs can be activated. This bit is cleared automatically after
the startup is completed.
Device Not Ready
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NCV7704, NCV7714
SPI REGISTERS CONTENT
CONTROL_0 Register
Address: 00h
Bit
D15
D14
D13
D12
D11
D10
D9
−
D8
−
D7
−
D6
−
D5
−
D4
−
D3
−
D2
−
D1
−
D0
RW
Access type
Bit name
Reset value
RW
RW
RW
RW
RW
RW
HS1 LS1
HS2 LS2
HS3 LS3
0
0
0
0
0
0
0
0
0
MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSx
LSx
0
Description
Remark
0
0
1
1
default
OUTx High impedance
LSx enabled
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_2
register, the output is only activated if PWM1 (PWM2)
input signal is high. Since OUT1..OUT3 are
half−bridge outputs, activating both HS and LS at the
same time is prevented by internal logic.
HS/LS Outputs
OUT1−3 Driver
Control
1
0
HSx enabled
1
OUTx High impedance
MODE
Description
Remark
If MODE is set, the device is switched to Active mode.
Resetting MODE forces the device to transition into
Standby mode, all internal memory is cleared and all
output stages are switched into their default state (off).
0
default
Standby
Mode Control
1
Active
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24
NCV7704, NCV7714
CONTROL_1 Register
Address: 01h
NCV7704:
Bit
D15
−
D14
−
D13
D12
D11
D10
D9
D8
−
D7
−
D6
−
D5
−
D4
−
D3
−
D2
−
D1
−
D0
−
Access type
Bit name
Reset value
RW
RW
RW
RW
RW
0
0
HS4.1 HS4.0 HS5 HS6 HS7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NCV7714:
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
−
−
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
−
LS
ECFB
Bit name
0
0
0
0
HS4.1 HS4.0 HS5 HS6 HS7
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ECEN
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
HSx.1
HSx.0
Description
Remark
0
0
0
default
OUTx High impedance
Output enabled, low
current mode (LED mode)
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_3
register, the output is only activated if the
corresponding PWM input signal (PWM pin or internal
PWM signal) is high.
1
HS Outputs
OUT4 Control
Output enabled, high
current mode (bulb mode)
1
1
0
1
OUTx High impedance
HSx
Description
Remark
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_3
register, the output is only activated if the
corresponding PWM input signal (PWM pin or internal
PWM signal) is high.
HS Outputs
OUT5−7
Control
0
default
OUTx High impedance
1
OUTx enabled
NCV7714 ONLY:
LS ECFB
Description
Remark
ECFB
Pull−down
Output
Pull−down transistor
disabled (high impedance)
The ECFB−pull−down transistor can only be activated
if the DAC output voltage is set to 0 V (DAC[5:0]=0). If
the PWM enable bit CONTROL_2.ECFB_PWM1 is
set, the output will only be activated when the PWM1
signal input is high.
0
default
Control
Pull−down transistor
enabled
1
NCV7714 ONLY:
DAC[5:0]
Description
Remark
Electrochrom.
Mirror
Reference
Voltage
6
Reference voltage for
ECON/ECFB differential
amplifier
V(DAC) = 1 + (1.5 / 2 ) ⋅ DAC[5:0]
If bit CONTROL_2.FSR=0, the output voltage is
clamped to 1.2 V.
0
n
default
default
NCV7714 ONLY:
ECEN
Description
Remark
Electrochromic mirror
controller disabled
By enabling the electrochromic mirror controller
(ECEN=1), the output driver for the external pass
transistor (ECON) is enabled. In addition, OUT6 is
activated, regardless of the setting of
CONTROL_1.HS6.
0
Electrochrom.
Mirror Enable
Electrochromic mirror
controller enabled
1
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NCV7704, NCV7714
CONTROL_2 Register
Address: 02h
NCV7704:
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
RW
RW
RW
−
−
−
−
RW
RW
RW
RW
−
−
−
−
−
OUT1 OUT2 OUT3
PWM1 PWM1 PWM1
Bit name
OCR1 OCR2 OCR3
0
0
0
0
0
0
0
0
PWMI
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
NCV7714:
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
RW
RW
RW
−
−
−
RW
RW
RW
RW
RW
−
−
−
RW
RW
OCR
ECFB
OUT1 OUT2 OUT3
PWM1 PWM1 PWM1
ECFB
PWM1
Bit name
OCR1 OCR2 OCR3
0
0
0
0
0
0
PWMI
0
0
0
0
0
0
0
FSR
0
Reset value
0
0
0
0
0
0
0
0
OCRx
Description
Remark
During an overcurrent event the overcurrent status bit
STATUS_0/2.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled,
the output will be reactivated automatically after a
programmable delay time (CONTROL_3.OCRF).
Overcurrent Recovery
disabled
0
default
Overcurrent
Recovery
Overcurrent Recovery
enabled
1
PWMI
Description
Remark
Internal PWM unit
disabled
0
default
The device has three different PWM sources: external
pins PWM1, PWM2 and the internal PWM unit which
can be used to control the lamp drivers in an
PWM Unit
Internal PWM unit
enabled
1
additional way. PWMI selects the internal PWM unit.
OUTx PWM
Description
Remark
For the half−bridge outputs it is possible to select the
PWM input pin PWM1. In this case the dedicated
output (selected in CONTROL_0 register) is on if the
PWM input signal is high. All half−bridges are
controlled by PWM1.
0
default
PWMx not selected
PWM1
Selection
1
PWMx selected
NCV7714 ONLY:
FSR
Description
Remark
6
Vout = 1.5 / 2
⋅
DAC[5:0] clamped at
1.2 V
0
default
DAC Full−scale
Range Control
The default voltage at ECFB in electrochrome mode is
clamped at 1.2 V, when FSR=1 the maximum value is
1.5 V.
6
Vout = 1.5 / 2
DAC[5:0]
⋅
1
www.onsemi.com
26
NCV7704, NCV7714
CONTROL_3 Register
Address: 03h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
−
RW
RW
RW
RW
−
RW
RW
RW
RW
RW
RW
RW RW RW RW
OUT4 OUT5 OUT6 OUT7
PWM2 PWM1 PWM2 PWM1
Bit name
0
0
OCR4 OCR5 OCR6 OCR7
0
0
OCRF OVUVR IS3 IS2 IS1 IS0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCRx
Description
Remark
During an overcurrent event the overcurrent status bit
STATUS_0/2.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled,
the output will be reactivated automatically after a
programmable delay time (CONTROL_3.OCRF).
Overcurrent Recovery
disabled
0
default
Overcurrent
Recovery
Overcurrent Recovery
enabled
1
OUTx PWM
Description
Remark
For the HS outputs it is possible to select the PWM
input pins PWM1, PWM2 or internal PWMI unit
(OUT4−6 only). In this case the dedicated output
(selected in CONTROL_1 register) is on if the PWM
input signal is high. OUT4 and OUT6 are controlled by
PWM2, OUT5 and OUT7 are controlled by PWM1.
0
default
PWMx not selected
PWM1/2
Selection
1
PWMx selected
OCRF
Description
Remark
Overcurrent
Recovery
Frequency
Selection
Slow Overcurrent
recovery mode
0
default
If the overcurrent recovery bit is set, the output will be
switched on automatically after a delay time. The
recovery behavior of OUT4 in bulb mode is not
affected by this bit.
Fast Overcurrent
recovery mode
1
OVUVR
Description
Remark
Over− and undervoltage
recovery function enabled
Over− /
Under−voltage
Recovery
0
default
If the OV/UV recovery is disabled by setting
OVUVR=1, the status register STATUS_2 bits VSOV
or VSUV have to be cleared after an OV/UV event.
No over− and undervoltage
recovery
1
www.onsemi.com
27
NCV7704, NCV7714
IS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
current sensing deactivated
current sensing deactivated
current sensing deactivated
current sensing deactivated
current sensing deactivated
current sensing deactivated
current sensing deactivated
OUT4
Remark
The current in all high−side power stages
(except of OUT1/2/3) can be monitored at the
bidirectional multifunctional pin ISOUT/PWM2.
This pin is a multifunctional pin and can be
activated as output by setting the current
selection bits IS[3:0]. The selected high−side
output will be multiplexed to the output ISOUT.
Current
Sensing
Selection
OUT5
OUT6
OUT7
current sensing deactivated
current sensing deactivated
current sensing deactivated
current sensing deactivated
current sensing deactivated
PWM_4 Register
Address: 08h
Bit
D15
D14
D13
D12
RW
D11
RW
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
RW
−
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
FSEL
BOOST
PW4.−1 PW4.−2 PW5.−1 PW5.−2 PW6.−1 PW6.−2 FSEL4 PW4.6 PW4.5 PW4.4 PW4.3 PW4.2 PW4.1 PW4.0
Bit Name
0
0
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FSEL_BOOST
Description
Remark
Higher
Internal PWM
Frequency
0
1
default
f(PWM) = 170 / 225 Hz
f(PWM) = 440 / 550 Hz
If PW_4.FSEL_BOOST=1 and
CONFIG.FEN_BOOST=1, Internal PWM frequency is
boosted to 440 / 550 Hz
PWx[−1;−2]
Description
Remark
Additional 2
LSB PWM
Duty Cycle
selector for
OUT4−6
It is possible to control OUT4−6 by the internal PWM
unit if bit CONTROL_2.PWMI is set.
If CONFIG.PWM_RSEN=1, the accuracy of PWM4−6
duty cycle is increased from 7 to 9 bits.
0
default
Duty Cycle for OUTx =
(PWx[6:0].PWx[−1:−2] +1) /
512
1 .. 03h
PW4[6:0]
0
Description
Remark
PWM Duty
Cycle selector
for OUT4
default
default
Duty Cycle for OUT4 =
(PW4[6:0] +1) / 128
It is possible to control OUT4 by the internal PWM unit
if bit PWMI is set in the control register CONTROL_2.
1 .. 7Fh
FSEL4
Description
Remark
PWM
Frequency
selector for
OUT4
0
1
f(PWM) = 170 Hz or 440 Hz
f(PWM) = 225 Hz or 550 Hz
Bit FSEL4 selects between 170 and 225 Hz or 440
and 550 Hz (if PWM_4.FSEL_BOOST=1 and
CONFIG.FEN_BOOST=1) PWM frequency for OUT4.
www.onsemi.com
28
NCV7704, NCV7714
PWM_5/6 Register
Address: 09h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
Bit Name
Reset Value
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
FSEL5 PW5.6 PW5.5 PW5.4 PW5.3 PW5.2 PW5.1 PW5.0 FSEL6 PW6.6 PW6.5 PW6.4 PW6.3 PW6.2 PW6.1 PW6.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PW5[6:0]
0
Description
Remark
PWM Duty
Cycle
selector for
OUT5
default
Duty Cycle for OUT5 =
(PW5[6:0] +1) / 128
It is possible to control OUT5 by the internal PWM unit
if bit PWMI is set in the control register CONTROL_2.
1 .. 7Fh
FSEL5
Description
Remark
PWM
Frequency
selector for
OUT5
Bit FSEL5 selects between 170 and 225 Hz or 440
and 550 Hz (if PWM_4.FSEL_BOOST=1 and
CONFIG.FEN_BOOST=1) PWM frequency for OUT5.
0
1
default
default
default
f(PWM) = 170 Hz or 440 Hz
f(PWM) = 225 Hz or 550 Hz
PW6[6:0]
0
Description
Remark
PWM Duty
Cycle
selector for
OUT6
Duty Cycle for OUT6 =
(PW6[6:0] +1) / 128
It is possible to control OUT6 by the internal PWM unit
if bit PWMI is set in the control register CONTROL_2.
1 .. 7Fh
FSEL6
Description
Remark
PWM
Frequency
selector for
OUT6
0
1
f(PWM) = 170 Hz or 440 Hz
f(PWM) = 225 Hz or 550 Hz
Bit FSEL6 selects between 170 and 225 Hz or 440
and 550 Hz (if PWM_4.FSEL_BOOST=1 and
CONFIG.FEN_BOOST=1) PWM frequency for OUT6.
www.onsemi.com
29
NCV7704, NCV7714
STATUS_0 Register
Address: 10h
Bit
D15
R/RC R/RC R/RC R/RC R/RC R/RC
OC OC OC OC OC OC
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
−
−
−
−
−
−
−
−
−
−
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HS1 LS1 HS2 LS2 HS3 LS3
Reset Value
0
0
0
0
0
0
OCx
0
Description
Remark
During an overcurrent event in one of the HS or LS, the belonging
overcurrent status bit STATUS_0.OCx is set and the dedicated
output is switched off. (The global multi bit UOV_OC is set, also).
When the overcurrent recovery bit is enabled, the output will be
reactivated automatically after a programmable delay time
(CONTROL_3.OCRF). If the overcurrent recovery bit is not set the
microcontroller has to clear the OC failure bit and to reactivate the
output stage again.
No overcurrent
detected
OUT1−3
Overcurrent
Detection
1
Overcurrent detected
STATUS_1 Register
Address: 11h
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
R/RC R/RC R/RC R/RC R/RC R/RC
ULD ULD ULD ULD ULD ULD
−
−
−
−
−
−
−
−
−
−
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HS1 LS1
HS2 LS2
HS3 LS3
Reset Value
0
0
0
0
0
0
ULDx
Description
Remark
For each output stage an underload status bit ULD is available. The
underload detection is done in “on−mode”. If the load current is
below the undercurrent detection threshold for at least td_uld, the
corresponding underload bit ULDx is set.
If an ULD event occurs the global status bit ULD will be set.
With setting CONFIG.NO_ULD_OUTn the global ULD failure bit is
deactivated in general.
0
No underload detected
Underload detected
OUT1−3
Underload
Detection
1
www.onsemi.com
30
NCV7704, NCV7714
STATUS_2 Register
Address: 12h
NCV7704:
Bit
D15
D14
D13
R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC
OC ULD OC ULD OC ULD OC ULD
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
−
−
−
−
R/RC R/RC
VSUV VSOV
−
−
Bit name
0
0
0
0
0
0
0
0
0
0
0
0
HS4 HS4 HS5 HS5 HS6 HS6 HS7 HS7
Reset value
0
0
0
0
0
0
0
0
0
0
NCV7714:
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
−
−
R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC
OC ULD OC ULD OC ULD OC ULD OC ULD
HS4 HS4 HS5 HS5 HS6 HS6 HS7 HS7 ECFB ECFB
Bit name
0
0
0
0
VSUV VSOV ECLO ECHI
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCx
Description
Remark
During an overcurrent event in one of the HS the belonging
overcurrent status bit STATUS_2.OCx is set and the dedicated
output is switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled, the output
will be reactivated automatically after a programmable delay
time (CONTROL_3.OCRF). If the overcurrent recovery bit is not
set the microcontroller has to clear the OC failure bit and to
reactivate the output stage again.
0
1
No overcurrent detected
Overcurrent detected
OUT4−7
Overcurrent
Detection
ULDx
Description
Remark
For each output stage an underload status bit ULD is available.
The underload detection is done in “on−mode”. If the load
current is below the undercurrent detection threshold for at
least td_uld, the corresponding underload bit ULDx is set.
0
No underload detected
OUT4−7
Underload
Detection
If an ULD event occurs the global status bit ULD will be set.
1
Underload detected
It is possible to deactivate the global ULD failure bit by setting
the configuration bits CONFIG.NO_ULD_OUTn.
VSUV
Description
Remark
In case of an Vs undervoltage event, the output stages will be
deactivated immediately and the corresponding failure flag will
be set. By default the output stages will be reactivated
automatically after Vs is recovered unless the control bit
CONTROL_3.OVUVR is set. If this is the case (OVUVR=1) the
bit VSUV has to be cleared after an UV event.
0
No undervoltage detected
Vs
Undervoltage
1
Undervoltage detected
VSOV
Description
Remark
In case of an Vs overvoltage event, the output stages will be
deactivated immediately and the corresponding failure flag will
be set. By default the output stages will be reactivated
automatically after Vs is recovered unless the control bit
CONTROL_3.OVUVR is set. If this is the case (OVUVR=1) the
bit VSOV has to be cleared after an OV event.
0
No overvoltage detected
Vs
Overvoltage
1
Overvoltage detected
ECLO
ECHI
Description
Remark
0
0
1
1
0
1
0
1
ECM output regulation in range
ECM output V > Vregulation
ECM output V < Vregulation
not used
Two comparators monitor the voltage at pin ECFB (feedback)
in electrocrome mode. If this voltage is below / above the
programmed target these bits signal the difference after at least
32 ms. The bits are not latched and may toggle after at least
32 ms, if the ECFB voltage has not yet reached the target. They
are not assigned to the Global Error Flag.
EC Mirror
Control
Status
www.onsemi.com
31
NCV7704, NCV7714
CONFIG Register
Address: 3Fh
NCV7704:
Bit
D15
RW
D14
RW
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
−
0
0
−
0
0
−
0
0
−
0
0
−
0
0
−
−
−
RW
RW
RW
−
RW
−
FEN
BOOST RESEN
PWM
NO_ULD NO_ULD NO_
HS1
NO_ULD
OUTn
Bit Name
0
0
0
0
0
0
0
0
0
0
LS1
TW
Reset Value
0
0
0
0
0
0
NCV7714:
Bit
D15
RW
D14
RW
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access Type
−
0
0
−
0
0
−
0
0
−
0
0
−
0
0
−
0
0
RW
−
RW
RW
RW
−
RW
−
FEN
BOOST RESEN
PWM
ECM
LSPWM
NO_ULD NO_ULD NO_
HS1
NO_ULD
OUTn
Bit Name
0
0
0
0
0
0
LS1
TW
Reset Value
0
0
0
0
0
0
0
FEN_BOOST
Description
Remark
Higher Internal
PWM
Frequency
0
1
default
f(PWM) = 170 / 225 Hz
f(PWM) = 440 / 550 Hz
If CONFIG.FEN_BOOST=1 and
PW_4.FSEL_BOOST=1, Internal PWM frequency
is boosted to 440 / 550 Hz
PWM_RESEN
Description
7 bits PWM
Remark
Higher Internal
PWM
Resolution
0
1
default
default
If enabled, 2 additional PWM LSB bits are added
in PWM_4 resister
9 bits PWM
NO_TW
Description
Remark
0
Thermal warning flag active
No Thermal
Warning Flag
The global thermal warning bit TW can be
deactivated.
No thermal warning flag
active
1
NO_ULD_OUTn
Description
Remark
Global
Underload Flag
OUTn
0
default
default
Global underload flag active
By setting CONFIG.NO_ULD_OUTn the global
ULD failure bit is deactivated in general.
No global underload flag
active
1
NCV7714 ONLY:
ECM_LSPWM
Description
Remark
If this bit is set, automatic PWM discharge on the
ECM output is enabled. In case of PWM
discharge the Overcurrent recovery feature is
disabled, regardless of the setting of
CONTROL_2.OC_ECFB.
0
LS PWM feature disabled
ECM PWM
Discharge
1
LS PWM feature enabled
www.onsemi.com
32
NCV7704, NCV7714
PACKAGE DIMENSIONS
SSOP36 EP
CASE 940AB
ISSUE A
NOTES:
0.20 C A-B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
4X
DETAIL B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. DIMENSIONS D AND E1 SHALL BE
DETERMINED AT DATUM H.
A
X
36
19
X = A or B
e/2
E1
E
DETAIL B
6. THIS CHAMFER FEATURE IS OPTIONAL. IF
IT IS NOT PRESENT, A PIN ONE IDENTIFIER
MUST BE LOACATED WITHIN THE INDICAT-
ED AREA.
36X
0.25 C
PIN 1
REFERENCE
MILLIMETERS
1
18
DIM MIN
MAX
2.65
0.10
2.60
0.30
0.32
e
A
A1
A2
b
---
---
36X b
B
M
S
S
0.25
T A
B
2.15
0.18
0.23
NOTE 6
TOP VIEW
c
h
DETAIL A
A
A2
D
10.30 BSC
H
D2
E
5.70
5.90
10.30 BSC
7.50 BSC
3.90 4.10
0.50 BSC
0.25 0.75
0.90
c
E1
E2
e
h
0.10 C
h
A1
SEATING
PLANE
END VIEW
M1
36X
C
SIDE VIEW
D2
L
0.50
L2
M
0.25 BSC
0
8
_
_
_
M1
5
15
_
GAUGE
PLANE
M
E2
L2
SEATING
PLANE
C
36X
L
DETAIL A
BOTTOM VIEW
SOLDERING FOOTPRINT
36X
1.06
5.90
4.10
10.76
1
36X
0.36
0.50
PITCH
DIMENSIONS: MILLIMETERS
www.onsemi.com
33
NCV7704, NCV7714
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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NCV7704/D
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