NCV8412ASTT1G [ONSEMI]
Self-Protected Low Side Driver with In-Rush Current Management;
| 型号： | NCV8412ASTT1G |
| 厂家： | 
ONSEMI |
| 描述： | Self-Protected Low Side Driver with In-Rush Current Management |
| 文件： | 总14页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Self-Protected Low Side
Driver with In-Rush Current
Management
NCV8412, NCV8412D
The NCV8412 is a three terminal protected Low−Side Smart
Discrete FET. The protection features include Delta Thermal
Shutdown, overcurrent, overtemperature, ESD and integrated
Drain−to−Gate clamping for overvoltage protection. The device also
offers fault indication via the gate pin. This device is suitable for harsh
automotive environments.
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V
I MAX
D
(Limited)
DSS
R
TYP
DS(ON)
(Clamped)
42 V
145 mW @ 10 V
5.9 A
Features
• Short−Circuit Protection with In−Rush Current Management
• Delta Thermal Shutdown
• Thermal Shutdown with Automatic Restart
• Overvoltage Protection
• Integrated Clamp for Overvoltage Protection and Inductive
Switching
SOT−223 (TO−261)
SOIC−8 NB
CASE 751
CASE 318E
• ESD Protection
• dV/dt Robustness
• Analog Drive Capability (Logic Level Input)
MARKING DIAGRAM
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101 Grade 1
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
DRAIN
4
AYW
8412A G
G
8
8412AD
ALYWX
G
Typical Applications
1
2
3
• Switch a Variety of Resistive, Inductive and Capacitive Loads
• Can Replace Electromechanical Relays and Discrete Circuits
1
• Automotive/Industrial
Drain
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
Overvoltage
Protection
Gate
Input
= Work Week
8412A or 8412AD
= Specific Device Code
= Pb−Free Package
ESD Protection
G
Temperature
Limit
Current
Limit
Current
Sense
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Source
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2020 − Rev. 0
NCV8412/D
NCV8412, NCV8412D
MAXIMUM RATINGS
Rating
Symbol
Value
42
Unit
V
Drain−to−Source Voltage Internally Clamped
Drain−to−Gate Voltage Internally Clamped
Gate−to−Source Voltage
V
DSS
V
42
V
DG
GS
V
"14
V
Drain Current − Continuous
I
D
Internally Limited
Total Power Dissipation (SOT−223)
@ T = 25°C (Note 1)
P
1.44
2.20
W
A
D
D
D
@ T = 25°C (Note 2)
A
Total Power Dissipation (SOIC−8 Dual), both channels loaded equally
Total Power Dissipation (SOIC−8 Dual), only one channel loaded
@ T = 25°C (Note 1)
P
P
1.14
1.53
W
W
A
@ T = 25°C (Note 2)
A
@ T = 25°C (Note 1)
0.93
1.18
A
@ T = 25°C (Note 2)
A
Thermal Resistance (SOT−223)
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
Junction−to−Case (Top)
R
R
R
86.7
56.9
4.7
°C/W
q
q
q
JA
JA
JS
58
R
q
JCT
Thermal Resistance (SOIC−8 Dual), both channels loaded equallyJunction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
R
R
R
109.2
81.7
28.6
69
°C/W
°C/W
mJ
q
JA
JA
JS
q
q
Junction−to−Case (Soldering Point)
Junction−to−Case (Top)
R
q
JCT
Thermal Resistance (SOIC−8 Dual), only one channel loaded
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
Junction−to−Case (Top)
R
R
R
134.4
105.8
28.6
69
q
JA
JA
JS
q
q
R
q
JCT
Single Pulse Inductive Load Switching Energy
E
100
AS
(L = 50 mH, I
= 2 A, V = 5 V, R = 25 W, T
= 25°C)
Lpeak
GS
G
Jstart
Load Dump Voltage
(V = 0 and 10 V, R = 22 W) (Note 3)
U *
S
55
V
GS
L
Operating Junction Temperature
Storage Temperature
T
−40 to 150
−55 to 150
°C
°C
J
T
storage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (100 sq mm, 1 oz. Cu, steady state)
2. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state)
3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1.
ESD ELECTRICAL CHARACTERISTICS (Notes 4, 5)
Parameter
Test Condition
Symbol
Min
4000
1000
Typ
Max
Unit
Electro−Static Discharge Capability
Human Body Model (HBM)
Charged Device Model (CDM)
ESD
V
4. Not tested in production.
5. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than
2 x 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current
waveform characteristic defined in JEDEC JS−002−2018.
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2
NCV8412, NCV8412D
+
I
D
DRAIN
I
G
V
DS
GATE
+
SOURCE
V
GS
−
−
Figure 2. Voltage and Current Convention
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3
NCV8412, NCV8412D
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Clamped Breakdown
V
= 0 V, I = 10 mA
V
(BR)DSS
42
39
44
42
49
49
V
GS
D
Voltage
V
V
= 0 V, I = 10 mA, T = 150°C
D J
GS
(Note 6)
Zero Gate Voltage Drain Current
V
GS
= 0 V, V = 32 V
I
0.7
2.3
4.0
20
mA
mA
DS
DSS
= 0 V, V = 32 V, T = 150°C
GS
DS
(Note 6)
J
Gate Input Current
V
= 5 V, V = 0 V
I
52
72
GS
DS
GSS
ON CHARACTERISTICS
Gate Threshold Voltage
V
= V , I = 150 mA
V
GS(th)
1.0
1.6
3.1
2.2
V
GS
DS
D
Gate Threshold Temperature Coefficient
Static Drain−to−Source On Resistance
V
= V , I = 150 mA (Note 6)
V /T
GS(th) J
mV/°C
mW
GS
DS
D
V
= 10 V, I = 1.7 A
R
DS(ON)
145
255
200
400
GS
D
V
GS
= 10 V, I = 1.7 A, T = 150°C
D
J
(Note 6)
V
= 5.0 V, I = 1.7 A
D
180
310
230
460
GS
V
= 5.0 V, I = 1.7 A, T = 150°C
GS
GS
D
J
(Note 6)
V
= 5.0 V, I = 0.5 A
D
180
305
230
460
GS
V
= 5.0 V, I = 0.5 A, T = 150°C
D
J
(Note 6)
Source−to−Drain Forward On Voltage
I
S
= 7 A, V = 0 V
V
SD
0.95
1.2
V
GS
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Time (10% V to 90% I )
t
20
14
31
25
ms
ms
GS
D
ON
Turn−On Rise Time (10% I to 90% I )
t
D
D
rise
Turn−Off Time (90% V to 10% I )
t
OFF
96
140
50
ms
GS
D
V
DD
= 0 V to 10 V,
GS
V
= 12 V, I = 1 A
D
Turn−Off Fall Time (90% I to 10% I )
t
fall
37
ms
D
D
Slew Rate On (80% V to 50% V
)
−dV /dt
DS ON
0.45
0.3
1.0
0.4
V/ms
V/ms
DS
DS
Slew Rate Off (50% V to 80% V
)
dV /dt
DS OFF
DS
DS
SELF PROTECTION CHARACTERISTICS
Current Limit
V
= 10 V, V = 5.0 V
I
LIM
3.3
3.3
4.4
4.0
5.6
4.9
A
DS
GS
V
DS
= 10 V, V = 5.0 V, T = 150°C
GS J
(Note 6)
V
= 10 V, V = 10 V (Note 6)
GS
2.6
2.3
3.9
3.5
5.9
5.0
DS
V
= 10 V, V = 10 V, T = 150°C
GS J
DS
(Note 6)
Temperature Limit (Turn−Off)
Thermal Hysteresis
T
150
150
175
15
190
200
°C
mA
LIM(OFF)
V
= 5.0 V (Note 6)
= 10 V (Note 6)
GS
DT
LIM(ON)
Temperature Limit (Turn−Off)
Thermal Hysteresis
T
185
15
LIM(OFF)
V
GS
DT
LIM(ON)
GATE INPUT CHARACTERISTICS (Note 6)
Device ON Gate Input Current
V
= 5 V, V = 10 V, I = 1 A
I
GON
25
250
35
52
333
65
72
480
96
GS
DS
D
V
GS
= 10 V, V = 10 V, I = 1 A
DS D
Current Limit Gate Input Current
Thermal Limit Gate Input Current
V
GS
= 5 V, V = 10 V
I
GCL
DS
V
GS
= 10 V, V = 10 V
200
550
1350
390
630
1500
540
750
1650
DS
V
= 5 V, V = 10 V, I = 0 A
I
GTL
GS
GS
DS
D
V
= 10 V, V = 10 V, I = 0 A
DS
D
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Not tested in production.
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4
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
10
1000
100
10
T
Jstart
= 25°C
T
= 25°C
Jstart
T
Jstart
= 150°C
T
Jstart
= 150°C
1
10
100
10
100
L (mH)
L (mH)
Figure 3. Single Pulse Maximum Switch−off
Figure 4. Single Pulse Maximum Switching
Energy vs. Load Inductance
Current vs. Load Inductance
10
1000
100
10
T
= 25°C
Jstart
T
Jstart
= 25°C
T
Jstart
= 150°C
1
T
Jstart
= 150°C
0.1
1
10
1
10
TIME IN CLAMP (ms)
TIME IN CLAMP (ms)
Figure 5. Single Pulse Maximum Inductive
Figure 6. Single Pulse Maximum Inductive
Switching Energy vs. Time in Clamp
Switch−off Current vs. Time in Clamp
5
4
3
5
4
3
2
8 V
T = 25°C
A
V
DS
= 10 V
6 V
10 V
5 V
25°C
−40°C
4 V
150°C
105°C
3.5 V
2
1
0
3 V
1
0
V
= 2.5 V
GS
0
1
2
3
4
5
1
2
3
4
5
V
DS
(V)
V
GS
(V)
Figure 7. On−state Output Characteristics
Figure 8. Transfer Characteristics
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5
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
350
400
300
200
100
0
150°C, V = 5 V
150°C, I = 1.7 A
GS
D
150°C, I = 0.5 A
300
250
200
150
D
105°C, V = 10 V
GS
150°C, V = 10 V
GS
105°C, I = 1.7 A
D
105°C, I = 0.5 A
105°C, V = 5 V
D
GS
25°C, V = 5 V
GS
25°C, I = 1.7 A
D
25°C, V = 10 V
25°C, I = 0.5 A
GS
D
−40°C, I = 0.5 A
D
−40°C, V = 5 V
GS
100
50
−40°C, I = 1.7 A
D
−40°C, V = 10 V
GS
4
5
6
7
8
9
10
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
I (A)
D
2
V
GS
(V)
Figure 9. RDS(on) vs. Gate−Source Voltage
Figure 10. RDS(on) vs. Drain Current
2
1.75
1.5
8
7
6
I
D
= 1.7 A
V
DS
= 10 V
V
GS
= 5 V
25°C
−40°C
150°C
1.25
1
5
4
V
GS
= 10 V
105°C
0.75
0.5
3
2
−40 −20
0
20
40
60
80 100 120 140
5
6
7
8
9
10
T (°C)
J
V
GS
(V)
Figure 11. Normalized RDS(on) vs. Temperature
Figure 12. Current Limit vs. Gate−Source
Voltage
5.5
5
100
10
1
V
DS
= 10 V
V
= 0 V
GS
4.5
4
150°C
V
GS
= 10 V
0.1
105°C
25°C
V
GS
= 5 V
0.01
3.5
3
−40°C
0.001
−40 −20
0
20
40
60
80 100 120 140
10
15
20
25
(V)
30
35
40
T (°C)
V
J
DS
Figure 13. Current Limit vs. Junction
Temperature
Figure 14. Drain−to−Source Leakage Current
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6
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
1.2
1.1
1
1.1
I
V
= 150 mA
D
= V
GS
DS
1
0.9
0.8
0.7
−40°C
25°C
0.9
0.8
105°C
150°C
0.7
0.6
0.6
0.5
V
= 0 V
9
GS
−40 −20
0
20
40
60
80 100 120 140
1
2
3
4
5
I
6
7
8
10
T (°C)
(A)
S
J
Figure 15. Normalized Threshold Voltage vs.
Temperature
Figure 16. Source−Drain Diode Forward
Characteristics
1.5
1.0
160
140
120
100
80
I
= 1 A
= 12 V
= 0 W
I
= 1 A
= 12 V
= 0 W
D
D
V
V
DD
R
DD
R
G
G
t
r
t
ON
−dV /dt
DS ON
t
OFF
dV /dt
60
DS OFF
0.5
0
40
t
f
20
0
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
V
GS
(V)
V
GS
(V)
Figure 17. Resistive Load Switching Time vs.
Figure 18. Resistive Load Switching
Drain−Source Voltage Slope vs. Gate−Source
Gate−Source Voltage
Voltage
1.4
t , (V = 10 V)
OFF GS
−dV /dt , V = 10 V
DS ON
GS
100
80
1.2
1
I
= 1 A
= 12 V
D
V
DD
I
= 1 A
= 12 V
D
t , (V = 5 V)
OFF GS
V
DD
0.8
0.6
0.4
0.2
0
60
t
, (V = 5 V)
GS
ON
dV /dt
DS OFF GS
, V = 5 V
t , (V = 10 V)
f
GS
t , (V = 5 V)
r
GS
dV /dt
, V = 10 V
40
DS OFF GS
−dV /dt , V = 5 V
t , (V = 5 V)
DS ON
GS
f
GS
20
0
t
, (V = 10 V)
ON
GS
t , (V = 10 V)
r
GS
0
500
1000
(W)
1500
2000
0
500
1000
(W)
1500
2000
R
R
G
G
Figure 19. Resistive Load Switching Time vs.
Gate Resistance
Figure 20. Drain−Source Voltage Slope during
Turn On and Turn Off vs. Gate Resistance
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7
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
110
100
90
PCB Cu thickness, 1.0 oz
80
70
60
50
40
PCB Cu thickness, 2.0 oz
0
100
200
300
400
500
600
700
2
COPPER HEAT SPREADER AREA (mm )
Figure 21. RqJA vs. Copper Area − SOT−223
100
10
50% Duty Cycle
20%
10%
5%
2%
1
0.1
1%
Single Pulse
2
645 mm 1 oz. Copper
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE WIDTH (sec)
Figure 22. Transient Thermal Resistance − SOT−223
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8
NCV8412, NCV8412D
APPLICATION INFORMATION
Circuit Protection Features
junction temperature is exceeded. When activated at
typically 175°C, the NCV8412 turns off. This feature is
provided to prevent failures from accidental overheating.
The NCV8412 has three main protections. Current Limit,
Thermal Shutdown and Delta Thermal Shutdown. These
protections establish robustness of the NCV8412.
EMC Performance
Current Limit and Short Circuit Protection
The NCV8412 has current sense element. In the event that
the drain current reaches designed current limit level,
integrated Current Limit protection establishes its constant
level.
If better EMC performance is needed, connect a small
ceramic capacitor to the drain pin as close to the device as
possible according to Figure 23.
Delta Thermal Shutdown
Delta Thermal Shutdown (DTSD) Protection increases
higher reliability of the NCV8412. DTSD consist of two
independent temperature sensors – cold and hot sensors. The
NCV8412 establishes a slow junction temperature rise by
sensing the difference between the hot and cold sensors.
ON/OFF output cycling is designed with hysteresis that
results in a controlled saw tooth temperature profile
(Figure 24). The die temperature slowly rises (DTSD) until
the absolute temperature shutdown (TSD) is reached around
175°C.
Thermal Shutdown with Automatic Restart
Internal Thermal Shutdown (TSD) circuitry is provided to
protect the NCV8412 in the event that the maximum
Figure 23. EMC Capacitor Placement
TEST CIRCUITS AND WAVEFORMS
Thermal Transient Limitation Phase
Overtemperature
Cycling
Nominal
Load
V
G
I
LIM
I
D
I
NOM
TSD
Delta TSD
activation
T
J
Time
Figure 24. Overload Protection Behavior
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9
NCV8412, NCV8412D
R
L
V
IN
+
D
R
V
DD
G
−
G
DUT
S
I
DS
Figure 25. Resistive Load Switching Test Circuit
Figure 26. Resistive Load Switching Waveforms
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10
NCV8412, NCV8412D
L
V
DS
V
IN
D
+
R
V
DD
G
−
G DUT
S
t
p
I
DS
Figure 27. Inductive Load Switching Test Circuit
5 V
0 V
V
IN
t
av
t
p
V
(BR)DSS
I
pk
V
DD
V
I
DS
V
DS(on)
0
DS
Time
Figure 28. Inductive Load Switching Waveforms
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11
NCV8412, NCV8412D
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCV8412ASTT1G
8412A
SOT−223
(Pb−Free)
1,000 / Tape & Reel
1,000 / Tape & Reel
2,500 / Tape & Reel
NCV8412ASTT3G
8412A
SOT−223
(Pb−Free)
NCV8412ADDR2G
(In Development)
8412AD
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
NCV8412, NCV8412D
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
q
q
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13
NCV8412, NCV8412D
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
SOLDERING FOOTPRINT*
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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