NCV8881 [ONSEMI]
Automotive Buck Regulator with Watchdog;
| 型号： | NCV8881 |
| 厂家： | 
ONSEMI |
| 描述： | Automotive Buck Regulator with Watchdog |
| 文件： | 总33页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV8881
1.5A Automotive Buck
Regulator with Watchdog
The NCV8881 consists of a Buck switching regulator (SMPS) with
a combination SMPS output undervoltage monitor and CPU watchdog
circuit. In addition, two fixed−voltage low dropout regulator outputs
are provided, and share an LDO output voltage status output. Once
enabled, regulator operation continues until the Watchdog signal is no
longer present. The NCV8881 is intended for Automotive,
battery−connected applications that must withstand a 40 V load dump.
The switching regulator is capable of converting the typical 9 V to
19 V automotive input voltage range to outputs from 3.3 V to 8 V at a
constant switching frequency, which can be resistor programmed or
synchronized to an external clock signal. Enable input threshold and
hysteresis are programmable, with the enable input state replicated at
an open drain Ignition Buffer output. The regulators are protected by
current limiting, input overvoltage and overtemperature shutdown, as
well as SMPS short circuit shutdown.
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MARKING
DIAGRAMS
16
SO−16W EP
PW SUFFIX
CASE 751AG
NCV8881
16
AWLYYWWG
1
1
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
Features
• 1.5 A Switching Regulator (internal power switch)
• 100 mA, 5 V LDO Output
• 40 mA, 8.5 V LDO Output
(Note: Microdot may be in either location)
• Operating Range 5 V to 19 V
• Programmable SMPS Frequency
• SMPS can be Synchronized to an External Clock
• Programmable SMPS Output Voltage Down to 0.8 V
• $2% Reference Voltage Tolerance
PIN CONNECTIONS
1
16
IGNBUF
WDI
RDLY
RESB
EN
5P0
LDOMON
8P5
VIN
SW
• Internal SMPS Soft−Start
• Voltage−mode SMPS Control
• SMPS Cycle−by−Cycle Current Limit and Short−Circuit Protection
• Internal Bootstrap Diode
SYNC
ROSC
GND
BST
FB
COMP
• Logic level Enable Input
• Enable Input Hysteresis Programmable by External Resistor Divider
• Enable Input State is Replicated at an Open Drain Output
• CPU Watchdog with Resistor Programmable Delays
• Watchdog Reset Output also Indicates SMPS Output Out of Regulation
• Battery Input Withstands Load Dump to 40 V
• Low Standby Current
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.
• Thermal Shutdown (TSD)
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Controls
• These are Pb−Free Devices
Applications
• Audio
• Infotainment
• Safety – Vision Systems
• Instrumentation
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
January, 2011 − Rev. 1
NCV8881/D
NCV8881
IGNITION
BUFFER
RIGBUF
REGULATED
5.0V
IGNBUF
WDI
5P0
CS5P0
RMON
FROM CPU
WATCHDOG OUT
LDO
MONITOR
LDOMON
8P5
REGULATED
8.5V
BEAD
C8P5
RDLY
RESB
EN
RDLY
CS8P5
TO CPU
RESET
ENABLE
SYNC
RRESB
BATTERY
VIN
SW
CIN
REGULATED
SMPS OUTPUT
R1
L1
R2
CBST
COUT
DFW
CZ1
SYNC
ROSC
GND
BST
FB
RP2
RFB1
ROSC
CP1
RZ1
RFB2
CP3
COMP
Figure 1. Typical Application
RIGBUF
S+5
5P0
16
IGNITION
BUFFER
BUFFERED
ENABLE
IGNBUF
1
LOGIC
RMON
LDO
MONITOR
CS5
LDOMON
15
QIB
QLM
WATCHDOG
INPUT
TEMP
SENSE
MONITOR
TSD
WDI
2
8P5
14
S+8.5
BEAD
NOPULSE
WATCHDOG
TIMER
RDLY
3
DBST2
DBST1
C8P5
CS8P5
5V
REGULATOR
8.5V
REGULATOR
RDLY
CPU
RESET
BATTERY
VIN
13
VIN_OV
/UVLO
RRESB
RESB
4
CIN
FAULT(H)
POWER
SWITCH
QRB
ENABLE
SWITCHER
OUT
EN
5
SW
12
ENABLE
R1
R2
L1
CBST
RH
CLAMP
BST
11
COUT
DFW
HYSTERESIS
QH
UNDERVOLTAGE
MONITOR
CZ1
RP2
SW_UV
RFB1
SHORT CKT
MONITOR
OC
RUN
FB
10
ERROR
AMP
SYNC
SYNC
6
PWM
COMPARATOR
REF
OSCILLATOR
CP1
RZ1
ROSC
7
RFB2
CP3
ROSC
COMP
GND
8
9
NCV8881
Figure 2. NCV8881 Detailed Block Diagram
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2
NCV8881
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 7
−0.3 to 7
−0.3 to 7
−0.3 to 10
10
Unit
V
Min/Max Voltage on WDI
Min/Max Voltage on RDLY
Min/Max Voltage on RESB
Min/Max Voltage on EN
Max EN Current
V
V
V
mA
mA
V
Min EN Current (with zero VIN voltage)
Min/Max Voltage on SYNC
Min/Max Voltage on ROSC
Min/Max Voltage COMP
Min/Max Voltage FB
−10
−0.3 to 7
−0.3 to 7
−0.3 to 7
−0.3 to 7
V
V
V
Min Voltage SW
– DC
− 20 ns
−0.7
−3
V
Max Voltage VIN to SW
40
V
V
Max Voltage VIN
40
Min/Max Voltage BST
−0.3 to 30
−0.3 to 15
−0.3 to 9.5
70
V
Min/Max Voltage BST to SW
Min/Max Voltage on 8P5
V
V
Max 8P5 Current
mA
V
Min/Max Voltage on LDOMON
Min/Max Voltage on 5P0
−0.3 to 7
−0.3 to 7
−0.3 to 7
−55 to +150
−40 to + 150
V
Min/Max Voltage IGNBUF
Storage Temperature range
Operating Junction Temperature Range
ESD withstand Voltage Human Body Model
V
°C
°C
T
J
V
ESD
2.0
200
>1.0
kV
V
kV
Machine Model
Charged Device Model
Moisture Sensitivity
MSL
Level 1
260
Peak Reflow Soldering Temperature
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
THERMAL CHARACTERISTICS
Board/Mounting Conditions Typical Value
Minimum Pad (Note 1)
1 sq. inch (Note 2)
Parameter
Junction−to−case top (Y , q
Unit
°C/W
°C/W
°C/W
°C/W
)
30
70
16
65
17
55
JT JT
Junction−to−pin 1(Y , q
)
JL1 JL1
Junction−to−board (Y , q ) (Note 3)
15
JB JB
Junction−to−ambient (R , q
)
150
q
JA JA
Specific Notes on Thermal Characterization Conditions:
NOTE: All boards are 0.062” thick FR4, 3” square, with varying amounts of copper heat spreader, in still air (free convection) conditions.
Numerical values are derived from an axisymmetric finite−element model where active die area, total die area, flag area, pad area,
and board area are equated to the actual corresponding areas.
2
1. 1 oz. copper, 17.2 mm spreader area (minimum exposed pad, not including traces which are assumed).
2
2
2. 1 oz. copper, 645 mm (1 in ) spreader area (includes exposed pad).
3. “Board” is defined as center of exposed pad soldered to board; this is the recommended number to be used for thermal calculations, as it
best represents the primary heat flow path and is least sensitive to board and ambient properties.
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3
NCV8881
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
Description
1
IGNBUF
This open drain output is pulled low whenever the EN signal is latched and a low level is recognized at
the EN input.
2
3
4
WDI
RDLY
RESB
CMOS compatible Watchdog pulse input from a CPU. To be valid, the time between falling edges of this
signal must be less than the programmed Watchdog Delay.
Delay programming pin for POR, BOOT and Watchdog delays. Connect a resistor between this pin and
ground.
This is an open drain output for resetting a CPU. RESB goes low if the WDI signal period is longer than
the programmed Watchdog delay, if VIN is above or below operating voltage, if the SMPS output is out of
regulation, or if the part is in thermal shutdown.
5
EN
Logic compatible Enable input. Once a high is received at the EN pin, the part enters a startup
sequence. Until expiration of the Soft−Start Timer, a low at the EN pin will shut off the part. Upon
expiration of the Soft−Start Timer, a low at the EN pin will shut the part off only if the SMPS output is out
of regulation, or the signal at the WDI input is not valid.
6
7
SYNC
ROSC
Logic compatible Synchronization input. Grounding this input allows a resistor between the ROSC pin
and ground to control the switching frequency. Connecting this pin to an external clock synchronizes
switching to the rising edge of the clock.
Oscillator frequency programming pin. Connect an external resistor from this pin to GND to set the
switching frequency. Leave this pin floating to operate at the default frequency of the internal oscillator.
Switching frequency is not controlled by this resistance if a clock is present at the SYNC pin, but the
resistance remains in control of the modulator ramp amplitude.
8
9
GND
Battery return, and ground reference for output voltages.
COMP
Switching Regulator Error Amplifier output for tailoring SMPS transient response with external
compensation components.
10
11
FB
Feedback input pin to program Switching Regulator output voltage, and detect a low or shorted SMPS
output condition.
BST
Bootstrap input provides drive voltage higher than VIN to the SMPS N−channel Power Switch for
minimum switch R
and highest efficiency. For a typical application connect a 0.1 mF ceramic
DS(on)
capacitor from this pin to the SW pin, in close proximity to both pins.
12
SW
Switching node of the Switching Regulator. Connect the SMPS output inductor and cathode of the SMPS
freewheeling diode to this pin.
13
14
VIN
8P5
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
Output of the internal 8.5 V linear regulator. This provides regulated gate drive voltage to the SMPS
Power Switch. For a typical application connect a 4.7 mF ceramic capacitor in series with 0.5 W from this
pin to ground.
15
16
LDOMON
5P0
This open drain output is pulled low if either the 5P0 or 8P5 output is out of regulation.
Output of the internal 5 V linear regulator. For a typical application connect a 4.7 mF ceramic capacitor in
series with 0.5 W from this pin to ground.
EXPOSED
PAD
Solder this to a low thermal impedance path for cooling.
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4
NCV8881
GENERAL SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V
= 13.2 V, V = 2.0 V, C = 4.7 mF unless specified otherwise) Min/Max values are valid
for the temperature range −40°C vT v 150 °C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
VIN
EN
IN
J
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VIN UVLO
START Voltage Threshold
STOP Voltage Threshold
VIN UVLO Hysteresis
VIN OVERVOLTAGE
STOP Voltage Threshold
RESTART Voltage Threshold
QUIESCENT CURRENT
VIN Quiescent Current
VIN Shutdown Current
ENABLE (EN PIN)
V
5.0
4.2
0.7
5.6
4.6
1.1
6.0
5.0
V
V
V
STRT
V
STP
V
INHYST
V
V
19
18
20
21
V
V
OVSTP
19.2
OVSTT
I
V
= 1 V, T = 25°C, V
= 0 V
= 0 V
2
5
mA
qMAX
FB
J
SW
I
V
EN
= 0 V, T = 25°C, V
10
15
mA
qSBMAX
J
SW
EN Logic High Threshold
EN Logic Low Threshold
EN Input Current
V
1.6
V
V
ENSTHH
V
1.2
35
ENSTHL
I
V
V
= 1.2 V
= 1.6 V
42
55
mA
mA
ENSWL
EN
EN Input Current
I
0.8
1.4
3.0
ENSWH
EN
Response to Open Input
Enable Delay
NCV8881 is disabled
EN high to LDO turn−on
38
5
50
ms
mA
V
Clamp Current
V
EN
= 5 V
20
12
Clamp Voltage
I
= 10 mA
9
10.5
EN
IGNITION BUFFER (IGNBUF PIN)
IGNBUF Output leakage
IGNBUF Output Voltage Low
THERMAL SHUTDOWN (TSD)
Thermal Shutdown
V
> 1.6 V
0
5
mA
EN
V
V
EN
< 1.2 V, sinking 0.5 mA
0.02
0.1
V
IGBLO
T
(Note 4)
(Note 4)
160
170
35
180
°C
°C
TSD
Thermal Shutdown Hysteresis
4. Guaranteed by design.
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5
NCV8881
LDO REGULATORS
ELECTRICAL CHARACTERISTICS (V
= 13.2 V, V = 2.0 V, C = 4.7 mF unless specified otherwise) Min/Max values are valid
for the temperature range −40°C vT v 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
VIN
EN
IN
J
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
5P0 OUTPUT
Output UV START Threshold
Output UV STOP Threshold
Output UV Hysteresis
Output Voltage Range
Line Regulation
V
V
Percent of V
Percent of V
Percent of V
No load
91
89
95
93
2
99
97
%
%
5UVSTT
O5P0
5UVSTP
O5P0
O5P0
V
%
5VUVH
V
4.8
5.0
5.2
4
V
O5P0
I
= 1 mA, 6 V < V < 19 V
mV/V
mA
mV
OUT
IN
Current Limit
105
160
205
400
Dropout Voltage
I
= 70 mA, DV
= 2%
315
(Note 6)
5P0
5P0
Output Load Capacitance Range
Output Load Capacitance ESR Range
Power Supply Ripple Rejection
C
Output capacitance for stability (Note 5)
ESR for stability (Note 5)
3.9
0.2
100
5
mF
W
O
ESR
Co
PSRR
V
VIN
= 13.2 V + 0.5 V 100 Hz
60
dB
pp
sine−wave, C
= 10 mF (Note 5)
5P0
Startup Overshoot
R
= 5 kW; C
= 10 mF
3
%
5P0LOAD
5P0
(Note 5)
8P5 OUTPUT
Output UV START Threshold
Output UV STOP Threshold
Output UV Hysteresis
Output Voltage Range
Line Regulation
V
Percent of V
Percent of V
Percent of V
91
89
95
93
2
99
97
%
%
8UVSTT
O8P5
O8P5
O8P5
V
8UVSTP
V
%
8VUVH
V
No load; 9 V < V < 19 V
8.26
44
8.5
8.74
7
V
O8P5
IN
I
= 1 mA, 9.5 V < V < 19 V
mV/V
mA
mV
OUT
8P5
IN
Current Limit
68
85
Dropout Voltage
I
= 20 mA, DV
= 2%
165
(Note 6)
300
8P5
Output Load Capacitance Range
Output Load Capacitance ESR Range
Power Supply Ripple Rejection
C
Output capacitance for stability (Note 5)
ESR for stability (Note 5)
3.9
0.2
100
5
mF
W
O
ESR
Co
PSRR
V
= 13.2 V + 0.5 V 100 Hz sine
60
11
dB
VIN
pp
wave, C
= 10 mF (Note 5)
8P5
Startup Overshoot
Output Clamp Voltage
LDOMON OUTPUT
Output leakage
R
= 10 kW; C
= 10 mF (Note 5)
3
%
V
8P5LOAD
8P5
V
I
= 67 mA into the NCV8881
9
13
CLP8P5
8P5
V
V
> V
< V
and V
> V
8UVSTT
0.2
5
mA
5P0
5UVSTT
8P5
Output Voltage Low
V
or V
< V ,
8UVSTP
0.03
0.1
V
RBLO
5P0
5UVSTP
8P5
sinking 0.5 mA
5. Guaranteed by design.
6. T = 125°C
J
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6
NCV8881
SMPS REGULATOR
ELECTRICAL CHARACTERISTICS (V
= 13.2 V, V = 2.0 V, V
= V
+ 8.2 V, C
= 0.1 mF, C = 4.7 mF unless specified
VIN
EN
BST
SW
BST IN
otherwise) Min/Max values are valid for the temperature range −40°C vT v 150 °C unless noted otherwise, and are guaranteed by test,
J
design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ms
V
SOFT−START
Soft−Start Completion Time
t
SS
3
5
7
VOLTAGE REFERENCE (FB Pin)
FB Voltage (COMP connected to FB)
V
FBR
T = 25°C
J
0.792
0.784
0.8
0.8
0.808
0.816
−40°C vT v 150°C
J
FB PIN MONITOR (SMPS Output Monitor)
FB Monitor High Threshold
FB Monitor Low Threshold
FB Monitor Hysteresis
V
V
V
increasing; Percent of V
FBR
91
89
10
95
93
20
2.5
99
97
%
%
FBMONH
FB
V
decreasing; Percent of V
FBR
FBMONL
FBMONY
FB
V
mV
ms
FB Low to RESB Output Delay
ERROR AMPLIFIER
t
10
FBLDLY
FB Bias Current
I
V
= V
FBR
−0.1
70
8
0.1
mA
dB
FBBIAS
FB
DC Gain
A
V
(Note 7)
(Note 7)
Gain−Bandwidth Product
Slew Rate COMP Rising
GBW
MHz
V/ms
V
COMP
= V
− 25 mV, C = 50 pF,
COMP
6
FB
FBR
I
= −1 mA, V
within ramp
COMP
voltage levels. (Note 7)
Slew Rate COMP Falling
V
COMP
voltage levels. (Note 7)
= V
+25 mV, C = 50 pF,
COMP
6
V/ms
FB
FBR
I
= 1 mA, V
within ramp
COMP
COMP Source Current
COMP Sink Current
I
V
V
= 2.2 V
= 3.2 V
1.5
1.8
4
4
10
10
mA
mA
SOURCE
COMP
COMP
I
V
COMP
V
COMP
= 2.2 V
= 1.1 V
1.3
0.6
3
1.6
10
10
mA
mA
SINK
Ramp Peak Voltage
Ramp Valley Voltage
Ramp Amplitude
OSCILLATOR
2.8
1.1
1.6
3.1
1.2
1.9
3.2
1.3
2.0
V
V
V
Frequency
F
OSC
R
= open
ROSC
154
337
170
186
429
kHz
ROSC = 36 kW
Maximum ROSC Controlled Frequency
ROSC Pin Voltage
F
Resistor from ROSC to GND
= open
500
700
850
kHz
V
OSCMAX
V
R
0.970
1.02
1.080
ROSC
ROSC
SYNCHRONIZATION
Frequency Range
f
(Note 7)
160
200
6.6
600
500
10
kHz
ns
SYNCMX
Synchronization Delay
De−Synchronization Delay
t
From rising SYNC edge
370
7.8
SNCDLY
t
From last rising SYNC edge;
ROSC = open
ms
USNCDLY
Input Current
V
= 5.0 V
5
10
2
mA
V
SYNC
SYNC Logic High Threshold
SYNC Logic Low Threshold
Response to Input Held High
V
SNCTHH
V
0.8
V
SNCTHL
Reverts to internal oscillator
(Note 7)
7. Guaranteed by design.
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7
NCV8881
SMPS REGULATOR
ELECTRICAL CHARACTERISTICS (V
= 13.2 V, V = 2.0 V, V
= V
+ 8.2 V, C
= 0.1 mF, C = 4.7 mF unless specified
VIN
EN
BST
SW
BST IN
otherwise) Min/Max values are valid for the temperature range −40°C vT v 150 °C unless noted otherwise, and are guaranteed by test,
J
design or statistical correlation.
Parameter
SYNCHRONIZATION
Symbol
Conditions
Min
Typ
Max
Unit
Minimum High Pulse Width
Minimum Low Pulse Width
DUTY CYCLE LIMITATIONS
Minimum Off Time
t
time V
time V
is above 2 V (Note 7)
is below 0.8 V (Note 7)
50
50
ns
ns
PWHIMIN
SYNC
t
PWLIMIN
SYNC
t
SW falling to SW rising
SW rising to SW falling
50
120
330
200
550
ns
ns
MINOFF
Minimum On Time
t
100
MINON
CURRENT LIMIT
Current Limit
1.75
2.2
76
3
A
Current Limit Response Time (Note 7)
SHORT CIRCUIT DETECTOR
FB Pin Threshold
From time of power switch turn−on
200
ns
V
% of V
70
85
%
%
FBSC
FBR
Soft−Start Timer
t
From start of Soft−start, % of t (Note 7)
100
250
SSTIMR
SS
POWER SWITCH
ON Resistance
R
V
= V
+ 6.0 V, T = 25°C
360
mW
ns
DSON
BST
SW
J
(Note 7)
SW Risetime
Inductor current = 1 A, T = 25°C
(Note 7)
30
30
J
SW Falltime
Inductor current = 1 A, T = 25°C
(Note 7)
ns
J
7. Guaranteed by design.
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8
NCV8881
WATCHDOG
ELECTRICAL CHARACTERISTICS (V
= 13.2 V, V = 2 V, C = 4.7 mF unless specified otherwise) Min/Max values are valid for
the temperature range −40°C vT v 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
VIN
EN
IN
J
Parameter
WATCHDOG INPUT (WDI pin)
Input High Voltage
Symbol
Conditions
Min
Typ
Max
Unit
2.0
V
V
Input Low Voltage
0.8
10
Input Current
V
WDI
= 5.0 V
5
mA
Hz
Threshold Frequency
f
to prevent RESB low
WDTH
R
R
R
= 10 kW
= 20 kW
= 30 kW
20.85
10.42
6.95
DLY
DLY
DLY
RDLY INPUT
Output Voltage
Output Voltage
RESB OUTPUT
Output Voltage Low
Output leakage
POR Delay Time
R
R
= 10 kW
= 30 kW
0.917
0.940
0.99
1.02
1.067
1.092
V
V
DLY
DLY
V
V
V
V
< V
, sinking 0.5 mA
to RESB high;
0.03
0.4
0.1
5
V
RBLO
FB
FBMONL
FBMONH
FBMONH
> V
mA
ms
FB
FB
> V
= 10 kW
R
R
R
R
R
4.0
8
12
5
10
15
6.0
12
DLY
DLY
DLY
DLY
DLY
= 20 kW (Note 8)
= 30 kW (Note 8)
= open; R
= open; R
t
POR
18
50
= 36 kW (Note 8)
OSC
OSC
110
= open
Boot Delay Time
RESB high to low;
ms
ms
R
R
R
R
R
= 10 kW
40
80
50
100
150
60
120
180
500
1100
DLY
DLY
DLY
DLY
DLY
t
BD
= 20 kW (Note 8)
= 30 kW (Note 8)
120
= open; R
= open; R
= 36 kW (Note 8)
OSC
OSC
= open
Watchdog Delay Time
8. Guaranteed by design.
WDI low to RESB low;
R
R
R
R
R
= 10 kW
= 20 kW (Note 8)
= 30 kW (Note 8)
= open; R
= open; R
48
96
144
60
120
180
72
144
216
550
1300
DLY
DLY
DLY
DLY
DLY
t
WD
= 36 kW (Note 8)
= open
OSC
OSC
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9
NCV8881
FAULT RESPONSES
INPUTS
RESPONSE TO A SINGLE FAULT EVENT
FULL OPERATION
RESTORED BY:
FAULT EVENT
EN
EN Latch
UNLATCH
UNLATCH
5P0
8P5
SMPS
RESB
VIN > UVLO, EN
High
VIN Undervoltage
L
SHUTDOWN
SHUTDOWN
SHUTDOWN
SHUTDOWN
LOW
VIN Undervoltage
VIN Overvoltage
H
L
SHUTDOWN
SHUTDOWN
SHUTDOWN
SHUTDOWN
SHUTDOWN
Stays ON
SHUTDOWN
SHUTDOWN
SHUTDOWN
SHUTDOWN
SHUTDOWN
Stays ON
LOW
LOW
VIN > UVLO
VIN < OV Threshold
VIN < OV Threshold
Decrease Temp
Decrease Temp
Remove Overload
Remove Overload
Remove Overload
Remove Overload
EN High
Stays Latched SHUTDOWN
Stays Latched SHUTDOWN
Stays Latched SHUTDOWN
Stays Latched SHUTDOWN
Stays Latched Current limited
Stays Latched Current limited
VIN Overvoltage
H
L
LOW
Thermal Shutdown
LOW
Thermal Shutdown
H
L
LOW
5P0 Out of Regulation
5P0 Out of Regulation
8P5 Out of Regulation
8P5 Out of Regulation
SMPS Out of Regulation
SMPS Out of Regulation
SMPS shorted to ground
SMPS shorted to ground
Watchdog Signal Invalid
Watchdog Signal Invalid
No Effect
No Effect
No Effect
No Effect
LOW
H
L
Stays ON
Stays ON
Stays Latched
Stays Latched
UNLATCH
Stays ON
Stays ON
Current limited
Current limited
SHUTDOWN
Stays ON
Stays ON
H
L
Stays ON
SHUTDOWN
Stays ON
SHUTDOWN
Stays ON
H
L
Stays Latched
UNLATCH
LOW
Remove Overload
EN High
SHUTDOWN
Stays ON
SHUTDOWN
Stays ON
SHUTDOWN
Latched OFF
SHUTDOWN
Stays ON
LOW
H
L
UNLATCH
LOW
EN Low, then High
EN High
UNLATCH
SHUTDOWN
Stays ON
SHUTDOWN
Stays ON
LOW
H
Stays Latched
Pulses Low
Apply Valid WDI
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
14.0
12.0
10.0
8.0
13.2 V SUPPLY
13.2 V SUPPLY
6.0 V SUPPLY
2.0
1.5
1.0
0.5
0.0
6.0 V SUPPLY
6.0
4.0
2.0
0.0
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. Supply Current (EN Low) vs.
Temperature
Figure 4. Supply Current (EN High) vs.
Temperature
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
12.0
11.5
11.0
10.5
10.0
9.5
0.0
−40 −20
9.0
−40 −20
0
20
40 60 80 100 120 140 160
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. EN Clamp Voltage vs. Temperature
Figure 5. En Delay vs. Temperature
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VIN UVLO START Voltage vs.
Temperature
Figure 8. VIN UVLO STOP Voltage vs.
Temperature
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
20.8
20.7
20.6
20.5
20.4
20.3
20.2
20.1
20.0
19.9
19.8
19.8
19.7
19.6
19.5
19.4
19.3
19.2
19.1
19.0
18.9
18.8
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. VIN OV STOP Voltage vs.
Temperature
Figure 10. VIN OV RESTART Voltage vs.
Temperature
810
808
806
804
802
800
798
796
794
792
790
5.000
4.998
4.996
4.994
4.992
4.990
5.0
10.0
15.0
VOLTAGE (V)
20.0
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
Figure 11. Reference Voltage vs. Temperature
Figure 12. 5P0 Output Voltage vs. Input
Voltage
189
187
185
183
181
179
177
175
350
300
250
200
150
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. 5P0 Output Current Limit vs.
Temperature
Figure 14. 5P0 Dropout Voltage Limit vs.
Temperature
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
8.500
8.495
8.490
8.485
8.480
8.475
8.470
75.0
74.0
73.0
72.0
71.0
70.0
69.0
68.0
67.0
66.0
65.0
−40 −20
0
20 40 60 80 100 120 140 160
9.0
12.0
15.0
VOLTAGE (V)
18.0
TEMPERATURE (°C)
Figure 15. 8P5 Output Voltage vs. Input
Voltage
Figure 16. 8P5 Output Current Limit vs.
Temperature
200
180
160
140
120
100
80
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
9.8
60
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. 8P5 Dropout Voltage vs.
Temperature
Figure 18. 8P5 Output Clamp vs. Temperature
0.050
0.040
0.030
0.020
0.010
0.000
0.20
0.18
0.16
0.14
0.12
0.10
−40 −20
0
20 40 60 80 100 120 140 160
−40 −20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. LDOMON Low Voltage vs.
Temperature
Figure 20. LDOMON Leakage vs. Temperature
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
0.00
−0.05
−0.10
−0.15
−0.20
−0.25
−0.30
−0.35
−0.40
0.05
0.04
0.03
0.02
0.01
0.00
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. RESB Low Voltage vs. Temperature
Figure 22. RESB Leakage vs. Temperature
1.050
1.045
1.040
1.035
1.030
1.025
1.020
1.015
1.010
1.010
1.005
1.000
0.995
0.990
0.985
0.980
0.975
0.970
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. ROSC Voltage vs. Temperature
Figure 24. RDLY Voltage vs. Temperature
180
178
176
174
172
170
168
166
164
162
160
400
395
390
385
380
375
370
365
360
355
350
ROSC Open
ROSC = 36 kW
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. Switching Frequency vs.
Temperature
Figure 26. Switching Frequency vs.
Temperature
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
750
740
730
720
710
700
690
680
670
660
650
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
ROSC = 0
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. Maximum Switching Frequency vs.
Temperature
Figure 28. SMPS Current Limit vs.
Temperature
2.00
80.0
79.0
78.0
77.0
76.0
75.0
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. SMPS Short−Circuit Threshold vs.
Figure 30. SMPS Ramp Amplitude vs.
Temperature
Temperature
5.0
4.5
4.0
3.5
3.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
= 2.2 V
V
COMP
V
= 2.2 V
= 3.2 V
COMP
COMP
V
= 1.1 V
COMP
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 31. Error Amp Source Current vs.
Temperature
Figure 32. Error Amp Sink Current vs.
Temperature
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
0.050
0.040
0.030
0.020
0.010
0.000
5.30
5.20
5.10
5.00
4.90
4.80
4.70
4.60
−40 −20
0
20
40 60 80 100 120 140 160
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. Soft−Start Time vs. Temperature
Figure 34. IGNBUF Low Voltage vs.
Temperature
650
600
550
500
450
400
350
300
250
200
150
100
50
24
22
20
18
16
14
12
10
8
6
0
4
10
100
1000
10
15
20
25
R RESISTANCE (kW)
DLY
30
35
40
45
50
ROSC RESISTANCE (kW)
Figure 35. Switching Frequency vs. ROSC
Resistance
Figure 36. POR Delay vs. RDLY Resistance
300
275
250
225
200
175
150
125
100
75
300
275
250
225
200
175
150
125
100
75
50
50
10
15
20
25
30
35
40
45
50
10
15
20
25
30
35
40
45
50
R
RESISTANCE (kW)
R
RESISTANCE (kW)
DLY
DLY
Figure 37. Boot Delay vs. RDLY Resistance
Figure 38. Watchdog Delay vs. RDLY
Resistance
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NCV8881
TYPICAL PERFORMANCE CHARACTERISTICS
250
350
300
250
200
150
100
50
T = 25°C
J
T = 25°C
J
200
150
100
50
0
0
0
10 20 30 40 50 60 70 80 90 100
0
5
10
15
20
25
30
35
40
LOAD CURRENT (kW)
LOAD CURRENT (kW)
Figure 39. 5P0 Dropout Voltage vs. Load
Current
Figure 40. 8P5 Dropout Voltage vs. Load
Current
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NCV8881
OPERATING DESCRIPTION
INPUT VOLTAGE
VIN is the power supply input for all NCV8881 functions.
Prior to the appearance of a valid high at the Enable input
(EN pin), VIN voltage above the V
a low level at the Reset output (RESB).
reset, and the LDOs are shut off. Upon dropping below the
threshold, the LDOs will powerup and the SMPS
will begin a soft−start sequence regardless of the state of the
V
OVSTT
threshold produces
EN signal.
STRT
STATE DIAGRAM
INPUT UNDERVOLTAGE SHUTDOWN
An Undervoltage Lockout (UVLO) circuit monitors the
voltage at the VIN pin. If the voltage is below the V
threshold it pulls RESB low, inhibits switching, and shuts
Figure 41 shows the State Diagram for the NCV8881.
States within numbered ellipses have common responses
(such as to input overvoltage and high temperature
shutdown) which force an exit from all states within.
STP
down the LDOs.
INPUT OVERVOLTAGE SHUTDOWN
If input voltage is above the V
threshold, RESB is
OVSTP
pulled low, switching is inhibited, the Soft−start circuit is
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NCV8881
5
VIN < 19V &
POWER
ON
RESET
VIN > Vstrt
RESB LOW
LDOS ON,
SMPS OFF
Temp<Shutdown
RESB LOW
LDOS OFF,
SMPS OFF
VIN > 19V or
Temp > Shutdown
Enable = 0
Enable = 1
VIN < Vstp
RESB LOW
LDOS, SMPS OFF
LDOMON ACTIVE
RESB LOW
LDOS, SMPS OFF
LDOMON OFF
Enable = 0
VIN < 19V &
Temp<Shutdown
VIN > 19V or
Temp > Shutdown
RESB LOW
LDOS ON, SMPS OFF
LDOMON ACTIVE
INIT SS TIMER
Enable = 0
5P0 or 8P5
in regulation
LATCH
ENABLE
UNLATCH
ENABLE
UNLATCH
ENABLE
RESB LOW
LDOS, SMPS OFF
VIN < 19V &
Temp<Shutdown
VIN > 19V or
Temp > Shutdown
1
RESB LOW
LDOS ON, SMPS OFF
INIT SS TIMER
5P0 or 8P5
in regulation
RESB LOW
LDOS, SMPS ON
SS TIMER GOING
SS Timer Expired
VFB > SC
Threshold
VFB < SC
Threshold
RESB LOW
LDOS, SMPS ON
INIT DELAYS
2
Enable = 0 &
SS Timer Expired
SMPS in
regulation
SMPS out of
regulation
POR DELAY
LDOS, SMPS ON
RESB LOW
3
BOOT DELAY
LDOS, SMPS ON
RESB HIGH
4
WDI
Invalid
RESB HIGH
LDOS, SMPS ON
Figure 41. State Diagram
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NCV8881
ENABLE (EN PIN)
After VIN rises above V
, EN below V
will
ENSTHL
regulator. Once either the 5P0 or 8P5 LDO reaches
regulation, EN dropping below V has no effect until
the SS Timer expires. Thereafter, if the SMPS output voltage
STRT
maintain a standby mode which keeps the switching
regulator, Watchdog Circuit, and LDO outputs off, and
minimizes supply current. In this state the RESB output is
low. A high logic level at the EN input activates all functions.
ENSTHL
is out of regulation, or WDI pulse period exceeds the
Watchdog Delay time t , EN below V
puts the
WD
ENSTHL
Upon EN exceeding V
, 5P0 and 8P5 voltages are
part in standby mode.
ENSTHH
established, followed by soft−start of the switching
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5 Regulation Monitor Threshold
5P0 Regulation Monitor Threshold
8P5
5P0
SMPS
OUTPUT
Figure 42. Enable High Time Insufficient to be Latched
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5 Regulation Monitor Threshold
5P0 Regulation Monitor Threshold
8P5
5P0
SMPS
OUTPUT
Figure 43. Enable High Time Long Enough to be Latched
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NCV8881
ENABLE
SIGNAL
THRESHOLD
R1
NCV8881
EN
PIN
EXTERNAL
RESISTORS
R2
RHYST
30K
COMPARATOR
CLAMP
RPDOWN
1MEG
Figure 44. Enable Input Hysteresis Mechanism
When the EN pin is below V
parallel with RPDOWN making the internal resistance from
, RHYST is in
battery is the enable signal. Given the lowest voltage that
must enable the part VIH , and the highest voltage that
ENSTHL
MIN
the EN pin to ground lower than when the EN pin is above
must disable the part VIL
the divider resistor values
MAX
V
. This produces hysteresis in the Enable function
are:
ENSTHH
when there is resistance between the source of the Enable
signal and the EN pin. A resistive divider from the Enable
signal source to the EN pin (Figure 44) allows a wide range
of activation/deactivation voltages. Note that this divider is
also used in conjunction with an internal zener clamp to keep
the EN pin voltage below the maximum voltage rating when
R1 = 0.7874 * (VIL
[R2 in kW]
– 1.27)/(0.0005556 * 1/R2) [kW]
MAX
R2 = 1800*(1.2283 * VIL
− VIH
)/( VIH
–
MAX
MIN
MIN
86.823 * VIL
+ 108.7) [kW]
MAX
Minimum hysteresis is: 0.0415 * R1 [V] [R1 in kW]
NCV8881 Enable Input VILmax Programming Range versus VIHmin Setting
7
6
5
4
3
2
1
0
MUST BE OFF
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VIHmin Setting (V)
Figure 45. Enable Input VILmax Programming Range versus VIHmin Setting
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NCV8881
IGNITION BUFFER
8P5 OUTPUT
The Ignition Buffer output IGNBUF reports the EN pin
voltage level (high or low) detected by the EN input circuitry
when the EN signal is latched. The NCV8881 will pull the
IGNBUF output low if the Enable signal is low, and release
the IGNBUF output if the Enable signal is high. The
IGNBUF output is an open drain device which requires an
external pullup resistor to a logic supply. IGNBUF is no
longer controlled by EN when EN transitions low if the EN
signal is not latched.
The regulated voltage provided by the 8P5 output is used
to power the internal gate drive circuitry, but can also
provide current to modest external circuit loads that can
tolerate significant spike noise at the SMPS switching
frequency.
CURRENT LIMIT
8P5 output current is limited above the specified output
current capability in order to limit inrush current at turn−on
and also minimize power dissipation in the event of an
output short circuit.
THERMAL SHUTDOWN
A thermal shutdown circuit will inhibit switching, reset
the Soft−start circuit, and power down the 5P0 and 8P5
outputs if internal die temperature exceeds a safe level.
Operation is automatically restored when die temperature
has dropped below the thermal restart threshold regardless
of the state of the EN signal.
OUTPUT UNDERVOLTAGE MONITOR
Either the 8P5 output voltage must exceed V
or the
before the SMPS
8UVSTT
5P0 output voltage must exceed V
5UVSTT
will begin soft−start. The LDOMON output will be pulled
low if the 8P5 output voltage is below V
.
8UVSTP
OUTPUT OVERVOLTAGE CLAMP
5P0 OUTPUT
If current is forced into the 8P5 output, a clamp will limit
the voltage in order to protect the gate driver circuit from
excessive voltage.
CURRENT LIMIT
5P0 output current is limited above the specified output
current capability in order to limit inrush current at turn−on
and also minimize power dissipation in the event of an
output short circuit.
STABILITY CONSIDERATIONS
The output capacitor helps determine three main
performance characteristics of a linear regulator: starting
delay, load transient response, and loop stability. The
optimum capacitor type and value will depend on these three
characteristics, as well as cost, availability, size and
temperature constraints. Tantalum, aluminum electrolytic,
film, and ceramic are all acceptable capacitor types for most
applications. Values of 1 mF or more work in many cases,
however attention must be paid to the Equivalent Series
Resistance (ESR). Aluminum electrolytic capacitors are the
least expensive solution but both the value and ESR of this
type of capacitor change considerably at low temperatures
(−25°C or −40°C). The capacitor manufacturer’s data sheet
must be consulted for this information. Stability under all
load and temperature conditions is guaranteed by a capacitor
value greater than or equal to 4.7 mF and ESR between 0.2 W
and 5 W.
OUTPUT UNDERVOLTAGE MONITOR
Either the 5P0 output voltage must exceed V
8P5 output voltage must exceed V
will begin soft−start. If the output is below V
or the
before the SMPS
5UVSTT
8UVSTT
, the
5UVSTP
LDOMON output will be pulled low.
STABILITY CONSIDERATIONS
The output capacitor helps determine three main
performance characteristics of a linear regulator: starting
delay, load transient response, and loop stability. The
optimum capacitor type and value will depend on these three
characteristics, as well as cost, availability, size and
temperature constraints. Tantalum, aluminum electrolytic,
film, and ceramic are all acceptable capacitor types for most
applications. Values of 1 mF or more work in many cases,
however attention must be paid to the Equivalent Series
Resistance (ESR). Aluminum electrolytic capacitors are the
least expensive solution but both the value and ESR of this
type of capacitor change considerably at low temperatures
(−25°C or −40°C). The capacitor manufacturer’s data sheet
must be consulted for this information. Stability under all
load and temperature conditions is guaranteed by a capacitor
value greater than or equal to 4.7 mF and ESR between 0.2
and 5 W.
SMPS OPERATION
LDO OUTPUT UNDERVOLTAGE MONITOR
Besides requiring the input voltage to be above V
STRT
, either the 5P0
or the 8P5 output
and the EN input to be above V
ENSTHH
output voltage must exceed V
5UVSTT
voltage must exceed V
before the SMPS will begin
8UVSTT
soft−start.
Besides powering external loads, the 5P0 output can be
used to provide a regulated voltage to an ROSC pullup
resistor as a convenient way to decrease the factory−set
switching frequency.
SOFT−START
Upon being enabled and released from all fault
conditions, and after one of the LDO outputs reaches
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22
NCV8881
regulation, a soft−start circuit slowly raises the switching
programmed switching frequency should be no higher than
regulator error amplifier reference to V
overloading the input supply.
in order to avoid
the highest synchronization frequency if synchronization is
used.
FBR
VOLTAGE REFERENCE
SMPS SYNCHRONIZATION
An internal, temperature compensated Bandgap voltage
reference provides the SMPS Error Amplifier and the 5P0
and 8P5 linear regulators with a stable, precision reference
voltage.
Applying a clock signal to the SYNC pin will cause power
switch turn−on edges to coincide with rising edges of the
applied clock signal. When synchronization will be
significantly higher than the default frequency, an ROSC
resistor which sets the internal oscillator frequency at (but
no higher than) the synchronization frequency can be used
to maintain the switching frequency approximately the same
as the synchronization frequency in the absence of the
SYNC signal.
Besides controlling the switching frequency, the ROSC
resistor controls the internal ramp slope, and can be used to
adjust the gain of the pulse width modulator.
A steady low or high SYNC input will restore SMPS
operation to the factory−set default or ROSC programmed
frequency after the De−synchronization delay.
SMPS ERROR AMPLIFIER
The error amplifier is an operational amplifier. The
Voltage Mode control method employed by the NCV8881
requires Type III compensation for optimum regulator
response to load and line transients.
The output voltage of the error amplifier controls the duty
cycle of the power switch by controlling the moment at
which the power switch shuts off (power switch turn−ons
occur at a fixed rate).
SMPS OSCILLATOR
With no connections to the ROSC or SYNC pins, the
NCV8881 switching frequency will be the factory−set
OUTPUT VOLTAGE REGULATION MONITOR
When the FB voltage is below V , RESB is pulled
FBMONL
default frequency f
of the internal oscillator.
OSC
low, and the POR, BOOT and Watchdog Delays are
initialized. When FB voltage exceeds V the POR
FBMONH
ROSC SMPS FREQUENCY CONTROL
Delay begins to time out. If, when the FB voltage is below
, the Soft−Start Timer has expired and the EN
Connection of a resistor between the ROSC pin and
ground will raise the switching frequency above the
factory−set default according to the following equation.
V
FBMONL
input is low, the NCV8881 will completely shut off (see
Figures 46 through 48).
FSW + 6840 RROSC −0.97 ) 170
Connection of a resistor between the ROSC pin and 5P0 will
lower the switching frequency below the default. The
0
1
2
3
4
5
6
7
8
9
10
11
VIN
ENABLE
8P5
5P0
SOFT−START TIMER
Regulation Threshold
Short−Circuit Threshold
SMPS
Current is Limited
OUTPUT
Figure 46. SMPS Overload During Startup
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23
NCV8881
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5
5P0
SOFT−START TIMER
Regulation Threshold
Short−Circuit Threshold
SMPS
Current is Limited
OUTPUT
Figure 47. SMPS Overload after Successful Startup #1
SMPS OVERLOAD AFTER SUCCESSFUL STARTUP #2
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5
5P0
SOFT−START TIMER
Regulation Threshold
Short−Circuit Threshold
SMPS
Current is Limited
OUTPUT
Figure 48. SMPS Overload after Successful Startup #2
SMPS CURRENT LIMIT AND SHORT CIRCUIT
PROTECTION
Every cycle, the power switch will be shut off if switch
current exceeds the internal, fixed, current limit. After the
Soft−Start Timer has expired, an extreme overload is
prevented from producing switch current in excess of the
current limit by detecting excessively low voltage at the FB
pin and latching the SMPS regulator off. Toggling the EN
input low then high, or cycling input voltage off and on is
required to restart the SMPS (see bubble 5 of Figure 41, and
Figures 49 − 51).
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NCV8881
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5
5P0
SOFT−START TIMER
Regulation Threshold
Short−Circuit Threshold
SMPS
Current is Limited
OUTPUT
SMPS LATCHED OFF
Figure 49. SMPS Short−Circuit during Startup
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5
5P0
SOFT−START TIMER
Regulation Threshold
Short−Circuit Threshold
SMPS
Current is Limited
OUTPUT
SMPS LATCHED OFF
Figure 50. SMPS Short−Circuit after Successful Startup #1
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NCV8881
0
1
2
3
4
5
6
7
8
9
10
11
12
VIN
ENABLE
8P5
5P0
SOFT−START TIMER
Regulation Threshold
Short−Circuit Threshold
SMPS
OUTPUT
SMPS LATCHED OFF
Figure 51. SMPS Short−Circuit After Successful Startup #2
WATCHDOG
Watchdog Delay period is initiated. Otherwise the
NCV8881 enters another POR Delay period and the RESB
pin is pulled low, while the SMPS and LDO outputs continue
to regulate. If EN is low when the Watchdog Delay expires
(no falling edge has occurred at the WDI input), RESB is
pulled low and the NCV8881 shuts off all power outputs
(SMPS and LDOs) and minimizes supply current.
WATCHDOG FUNCTION
The Watchdog function monitors the WDI input to check
that WDI pulses arrive more frequently than the
programmed minimum rate. Monitoring commences after
two sequential time periods (the POR and BOOT Delays)
which start when the SMPS output reaches regulation. After
these initial time periods, time between WDI falling edges
exceeding the Watchdog Delay indicates abnormal
microcontroller activity, and the NCV8881 responds by
pulling the open drain RESB output low. A single external
resistor from the RDLY pin to ground programs the POR,
BOOT and Watchdog Delays.
In order to ensure that WDI pulses keep RESB from being
pulled low, they must never occur further apart than the
minimum specified t . However, RESB is not guaranteed
WD
to be pulled low unless pulses occur further apart than the
maximum specified t
.
WD
Removal of other conditions that cause RESB to go low
(V > V , temperature > T , and SMPS output
IN
OVSTP
TSD
When enabled and upon the SMPS output reaching
regulation, the NCV8881 enters the POR Delay period
voltage low) also initiate POR and BOOT Delays prior to
resumption of WDI monitoring.
Figures 52 through 57 illustrate the action of RESB and
the POR, BOOT, and Watchdog Delays during start−up and
shutdown.
The Watchdog Delay is internally limited to a maximum
value proportional to the switching period in case the
resistance at the RDLY pin becomes excessively high, such
as would occur if the path from the RDLY pin through the
RDLY resistance becomes an open circuit.
t
, during which the RESB pin is held low. When the
POR
POR Delay expires, the NCV8881 enters the BOOT Delay
period t during which the RESB output is allowed to be
BD
pulled up by the external resistance. When the BOOT Delay
expires, the Watchdog circuit begins monitoring the WDI
pin for a falling edge (from a microprocessor or other signal
source). If a falling edge arrives before the Watchdog Delay
period t
expires, RESB remains high and a new
WD
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NCV8881
2
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VIN
ENABLE
RESB
POR
DELAY
POR
DELAY
POR
DELAY
POR
DELAY
BOOT DELAY
BOOT DELAY
BOOT DELAY
WATCHDOG
DELAY
WATCHDOG
DELAY
WATCHDOG
DELAY
WDI
3.3V
5V
Figure 52. Watchdog Never Appears; EN Input HIGH
WATCHDOG STUCK HIGH, THEN RECOVERS; ENABLE = HIGH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VIN
ENABLE
RESB
POR
DELAY
POR
DELAY
POR
DELAY
BOOT DELAY
WATCHDOG
DELAY
BOOT DELAY
WATCHDOG
DELAY
BOOT DELAY
WDI
WDI STUCK HIGH
NORMAL RESPONSE
NORMAL RESPONSE
3.3V
5V
Figure 53. Watchdog Stuck HIGH, Then Normal; EN Input HIGH
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27
NCV8881
WATCHDOG STUCK LOW, THEN RECOVERS; ENABLE = HIGH
0
1
2
3
4
5
6
7
8
9
10
11
VIN
ENABLE
RESB
POR
DELAY
POR
DELAY
P
D
BOOT DELAY
WATCHDOG
DELAY
BOOT DELAY
WATCHDOG
DELAY
WDI
WDI STUCK LOW
NORMAL RESPONSE
3.3V
5V
Figure 54. Watchdog Stuck LOW, Then Normal; EN Input HIGH
0
1
2
3
4
5
6
7
8
9
10
11
VIN
ENABLE
RESB
POR
DELAY
POR
DELAY
PO
DELA
WATCHDOG
DELAY
WATCHDOG
DELAY
BOOT DELAY
BOOT DELAY
WDI
WDI TOO SLOW
WDI TOO SLOW
3.3V
5V
Figure 55. Watchdog is Too Slow; EN Input HIGH
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NCV8881
WATCHDOG STUCK HIGH; ENABLE = LOW, THEN EN = HIGH RESTARTS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VIN
ENABLE
RESB
POR
DELAY
POR
DELAY
WATCHDOG
DELAY
BOOT DELAY
BOOT DELAY
WDI
NORMAL RESPONSE
NORMAL RESPONSE
WDI STUCK HIGH
3.3V
5V
Figure 56. Watchdog Stuck HIGH, EN Input LOW; then EN Goes HIGH to Restart the Regulators
SMPS OUTPUT OUT OF REGULATION TO RESB LOW DELAY
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VFBMONL
THRESHOLD
3.3V
tFBLDLY
RESB
Figure 57. RESB Pulled Low as the SMPS Output Voltage (pullup source for RESB) Drops Out of Regulation
APPLICATION INFORMATION
Input Capacitors
requirements. Tantalum, Aluminum or Polymer
Electrolytic, capacitors can be used. Ceramic capacitors
should have series resistance added to be within the
recommended ESR range. There are many capacitor
vendors which supply automotive rated parts that fall within
these ranges. For example, the SUNCON EP−series
Aluminum Electrolytic capacitors are well suited well for
automotive radio applications.
The primary input capacitor should be a ceramic of at least
4.7 mF placed between the VIN pin and the ground terminal
of the SMPS freewheeling diode in order to reduce input
voltage perturbations present when the NCV8881 SMPS is
heavily loaded. A secondary 0.1 mF ceramic capacitor
positioned as closely as possible between the VIN and GND
pins of the NCV8881 provides greater reduction of input
perturbations than further increasing the value of the
primary ceramic capacitor, and can be more effectively
positioned than the larger 4.7 mF capacitor without
compromising PCB thermal conductivity.
Setting the SMPS Output Voltage
To set the output voltage of the switching regulator, use
the following equation:
ǒ1 ) R1Ǔ
is the Reference voltage, R1 is the resistor
to the FB pin and R2 is the resistor
connected from the FB pin to ground. To reduce the effect
(eq. 1)
VSWOUT + VREF
LDO Output Capacitor Selection
R2
The LDOs have been compensated to work with output
capacitors above 3.3 mF having an ESR from 200 mW up to
5 W over the full range of output current and temperature.
Lower capacitance and ESR can be used for lighter load
where V
REF
connected from V
SWOUT
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29
NCV8881
of input offset current error, it is customary to calculate R1
with R2 set at 1 kW.
the necessary capacitance, at the expense of higher ripple
current.
In continuous conduction mode, the peak−to−peak ripple
current is calculated using the following equation:
SMPS Snubber
A resistor and ceramic capacitor must be connected in
series between the SW pin and ground. Typical values are
10 W and 1 nF.
VSWOUT
VSWOUT
ǒ1 * Ǔ
VIN
(eq. 4)
IPP + TSW
L
Where T is the switching period. From this equation it
SW
SMPS Freewheeling Diode Selection
is clear that the ripple current increases as L decreases,
emphasizing the trade−off between dynamic response and
ripple current. For most applications, the inductor value falls
in the range between 10 mH and 22 mH. There are many
magnetic component suppliers providing energy storage
inductor product lines suitable such as the Wurth TPC series
or TOKO DSH104C series inductors, which are
recommended for the automotive radio applications.
The freewheeling diode in the SMPS provides the
inductor current path when the power switch turns off, and
is sometimes referred to as the commutation diode. The
diode peak inverse voltage must exceed the maximum
operating input voltage in order to accommodate any higher
peak voltage produced by switchnode ringing. The peak
conducting current is determined by the internal current
limit. The average diode current can be calculated from the
output current I
, the input voltage V and the output
by:
OUT
IN
SMPS Output Capacitor Selection
voltage V
SWOUT
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
it supplies the current to the load for first few microseconds,
where after the controller recognizes the load transient and
proceeds to increase the duty cycle. Neglecting the effect of
the ESL, the output voltage has a first drop due to the ESR
of the capacitor.
VSWOUT
ǒ1 * Ǔ
VIN
(eq. 2)
ID(avg) + IOUT
The freewheeling diode should have a current rating equal
to the maximum NCV8881 current limit, such as the
MBRA340T3.
(eq. 5)
DVSWOUT(ESR) + DISWOUT ESR
Inductor Selection
Mechanical and electrical considerations, as well as cost
influence the selection of an output inductor. From a
mechanical perspective, smaller inductor values generally
correspond to smaller physical size. Since the inductor is
often one of the largest components in SMPS system, a
minimum inductor value is particularly important in
space−constrained applications. From an electrical
perspective, smaller inductor values correspond to faster
transient response. The maximum current slew rate through
the output inductor for a buck regulator is given by:
A lower ESR produces a lower DV during load transient.
In addition, a lower ESR produces a lower output voltage
ripple. The voltage drop due to the output capacitance
discharge can be approximated using the following
equation:
DVSWOUT(CHARGE)
(eq. 6)
ǒ
Ǔ2
DISWOUT L
+
ǒ
Ǔ
2 CSWOUT VIN(MIN) DMAX * VSWOUT
dIL
dt
VL
L
(eq. 3)
Where, D
is the maximum duty cycle value, which is
Inductor Slew Rate +
+
MAX
90%. Although the ESR effect is not in phase with the
discharging of the output voltage, DV can be
Where I is the inductor current, L is the output inductance,
SWOUT(ESR)
L
added to DV
the maximum DV
to give a rough indication of
during a transient condition.
and V is the voltage drop across the inductor.
SWOUT(CHARGE)
L
This equation indicates that larger inductor values limit
the regulator’s ability to slew current through the output
inductor in response to output load transients.
Consequently, output capacitors must supply sufficient
charge to maintain regulation while the inductor current
“catches up” to the load. This results in larger values of
output capacitance to maintain tight output voltage
regulation. In contrast, smaller values of inductance increase
the regulator’s maximum achievable slew rate and decrease
SWOUT
Simulation can also help determine the maximum
DV ; however, it will ultimately have to be verified
SWOUT
with the actual load since the ESL effect is dependent on
layout and the actual load’s di/dt.
SMPS Input Capacitor Selection
Besides voltage rating, a primary consideration for
selecting the input capacitor is input RMS current rating.
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NCV8881
2
ȡ
ȣ
ǒV
FǓ
T
)V
SW
SWOUT
L
(
)
ǒ
1 * D
Ǔȧ
ȧ
ȧ
Ǹ
2
2
ISWOUT )
(eq. 7)
(
)
(
)
IIN(RMS) + D 1 * D I
)
1 * D
ȧ
ȧ
ȧ
ȧ
SWOUT
12
ȧ
ȧ
Ȣ
Ȥ
Where D is the Duty Cycle = t /(t +t ), and V is the
forward voltage of the freewheeling diode.
voltage initially rises past the Undervoltage Lockout
threshold.
ON ON OFF
F
Another consideration for the value of the input capacitor
is the ability to supply enough input charge to satisfy sudden
increases in output current (such as produced at start−up, or
upon maximum load step) without an unacceptable drop in
input voltage. This is sometimes important when the input
SMPS Compensation
The NCV8855 utilizes voltage mode control. The control
loop regulates V
by monitoring it and controlling the
SWOUT
power switch duty cycle. Inherent with all voltage−mode
control loops is a compensation network.
VIN
POWER
SWITCH
VOLTAGE
RAMP
DCR
VOUT
LOUT
DFW
C1
R1
C2
R2
C3
R3
VREF
COMP
ERROR
AMP
ESR
COUT
Figure 58.
The compensation network consists of the internal error
amplifier and the impedance networks Z (R1, R3 and C3)
in DC conditions to minimize the load regulation. The
open-loop gain magnitude versus frequency plot of a stable
control loop crosses zero dB with close to −20 dB/decade
slope and a phase margin greater than 45°.
IN
and Z (R2, C1 and C2). The compensation network has to
FB
provide a loop transfer function with the highest 0 dB
crossing frequency to have fast response and the highest gain
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NCV8881
dB
1
wZ1
=
R ‧C2
2
1
wZ 2
= (R + R )‧C3
1
3
1
wP1
=
⎛
⎞
C ‧C2
1
⎢
⎢
⎟
⎟
R ‧
2
C + C2
1
⎝
⎠
1
wP2
=
R ‧C3
3
w
1
wLC
=
Error Amplifier
Compensation Network
Modulator Gain
LOUT ‧COUT
Closed Loop Gain
1
wESR
=
ESR‧COUT
Figure 59.
To reiterate, there are 3 primary goals to compensating.
Goal 1 is to have a high a unity gain bandwidth (UGB) that
crossover frequency cannot exceed 1/2 F and the phase
SW
margin has to be greater than 0° at crossover. However, a
SMPS operating towards these absolutes will experience
severe ringing before it dampens out.
To achieve the above goals, the following guidelines
should be adopted.
is greater than 1/10 the switching frequency F , but less
SW
than 1/2 the switching frequency. UGB is also known as the
crossover frequency. This is the point where the loop gain =
0 dB or a gain of 1. In the plot above, the UGB is the point
where the red line crosses the TBD axis. Goal 2 is to have the
loop gain cross 0 dB with a −20 dB/decade slope also known
as a −1 slope. Goal 3 is to achieve over 45° of phase margin
when the gain crosses 0 dB. These are just goals. Sometimes
− Place w at half the resonance of w
Z1
LC
− Place w at or around w
Z2
LC
− Place w at w
P1
ESR
− Place w at half the switching frequency
P2
the crossover frequency is reduced below 1/10 F in order
to meet goal 3.
Conversely, some designs will push the crossover
Performing these calculations will take some amount of
iteration and bench testing is needed to verify results.
ON Semiconductor has developed a tool to speed up the
design process tremendously with great ease and accuracy.
This tool can be downloaded by following the link below:
http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP
SW
frequency as high as it can (as long as it is below 1/2 F
)
SW
with a reduced phase margin of 30° in order to get a faster
transient response. The only two absolutes are that the
ORDERING INFORMATION
Device
†
Package
SOIC−16W EP
Shipping
NCV8881PWR2G
1000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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32
NCV8881
PACKAGE DIMENSIONS
SOIC−16 WIDE BODY EXPOSED PAD
CASE 751AG−01
−U−
ISSUE A
A
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
16
1
9
P
B
M
M
W
0.25 (0.010)
R x 45
_
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
−W−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
G
14 PL
PIN 1 I.D.
DETAIL E
TOP SIDE
MILLIMETERS
INCHES
MIN
0.400
DIM MIN
MAX
MAX
0.411
0.299
0.104
0.019
0.035
C
A
B
C
D
F
10.15
7.40
2.35
0.35
0.50
10.45
F
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.020
−T−
0.10 (0.004)
T
SEATING
K
D16 PL
0.25 (0.010)
H
PLANE
G
H
J
1.27 BSC
0.050 BSC
M
S
S
T
U
W
J
3.45
0.25
0.00
4.72
0
3.66 0.136
0.32 0.010
0.10 0.000
4.93 0.186
0.144
0.012
0.004
0.194
7
DETAIL E
K
L
M
P
R
7
10.55
0
0.395
_
_
_
_
10.05
0.25
0.415
0.029
1
8
9
0.75 0.010
EXPOSED PAD
SOLDERING FOOTPRINT*
L
0.350
Exposed
Pad
16
0.175
0.050
BACK SIDE
C
L
0.188
0.200
0.376
C
L
0.074
0.024
0.150
DIMENSIONS: INCHES
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCV8881/D
相关型号：
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