NCV891930MW01R2G [ONSEMI]
Low Quiescent Current 2 MHz Automotive Synchronous Buck Controller;
| 型号： | NCV891930MW01R2G |
| 厂家： | 
ONSEMI |
| 描述： | Low Quiescent Current 2 MHz Automotive Synchronous Buck Controller 开关 |
| 文件： | 总33页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Quiescent Current
2 MHz Automotive
Synchronous Buck Controller
NCV891930
The NCV891930 is a 2 MHz fixed−frequency low quiescent current
buck controller with spread spectrum that operates up to 38 V
(typical). It may be synchronized to a clock or to separate
NCV891930. Peak current mode control is employed for fast transient
response and tight regulation over wide input voltage and output load
ranges. Feedback compensation is internal to the device, permitting
design simplification. The NCV891930 is capable of converting from
an automotive input voltage range of 3.5 V (4.5 V during startup) to
18 V at a constant base switching frequency above the sensitive AM
band, eliminating the need for costly filters and EMI countermeasures.
The switching frequency folds back to 1 MHz for input voltages
between 20 V up to 38 V (typical). Under load dump conditions up to
45 V the regulator shuts down. A high voltage bias regulator with
automatic switchover to an external 5 V bias supply is used for
improved efficiency. Several protection features such as UVLO,
current limit, short circuit protection, and thermal shutdown are
provided. High switching frequency produces low output voltage
ripple even when using small inductor values and an all−ceramic
output filter capacitor, forming a space−efficient switching solution.
(410 kHz version offered with NCV881930)
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24
1
QFNW24 4x4, 0.5P
CASE 484AE
Note: With wettable flanks – meets JEDEC MO220
MARKING DIAGRAM
24
1
ZZZZZ
30XX
ALYWG
G
= V8919, 8919A
= 00, 01
= Assembly Location
= Wafer Lot
= Year
ZZZZZ
XX
A
L
Y
W
G
Features
• 30 mA Operating Current at No Load
• 75 mV Current Limit Sensing
• Capable of 45 V Load Dump
• Board Selectable Fixed Output Voltages With Lockout
• 2 MHz Operating Frequency
• Adaptive Non−Overlap Circuitry
• Integrated Spread Spectrum
• Logic level Enable Input Can be Tied Directly to Battery
• Short Circuit Protection Pulse Skip
• Battery monitoring for UVLO and Overvoltage Protection
• Thermal Shutdown (TSD)
• Adjustable Soft−Start
• SYNCI, SYNCO, Enable, RSTB, ROSC
• QFN Package with Wettable Flanks (pin edge plating)
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
(Top View)
24
23
22
21
20
19
18
V_CS
CSP
CSN
VOUT
NC
1
2
3
4
5
6
VDRV
VIN
17
16
15
14
13
DBIAS
VSEL
V_SO
GND
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
EN
SYNCO
7
8
9
10
11
12
Typical Applications
• Radio and Infotainment
• Instrumentations & Clusters
• ADAS (safety applications)
• Telematics
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2020 − Rev. 4
NCV891930/D
NCV891930
VIN
+
VIN
−
6
5
4
3
2
1
NC
BST
7
8
9
24
Q1
Q2
NCV891930
NVMFS5C468NL
CBST
ROSC
GH
23
ROSC
RS
VSW
22
SSC
GND
L
+
GL
21
NVMFS5C468NL
C
10
11
12
GND
VOUT
PGND
20
RSTB
VOUT
−
VCCEXT
19
SYNCI
13
14
15
16
17
18
RSYNCI
VIN
Figure 1. 5 V Application Schematic Example
VIN
+
VIN
−
6
5
4
3
2
1
NC
BST
7
24
23
22
21
NVMFS5C468NL
CBST
Q1
Q2
NCV891930
ROSC
GH
8
ROSC
RS
VSW
GL
SSC
GND
9
L
+
NVMFS5C468NL
C
10
11
12
GND
VOUT
PGND
RSTB
VOUT
20
19
−
VCCEXT
SYNCI
13
14
15
16
17
18
RSYNCI
Open
or + 5 V
VIN
Figure 2. 3.3 V Application Schematic Example
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2
NCV891930
BST
24
VCCEXT
19
VDRV
18
VIN
17
LDO
5 V LDO
13
12
8
BYPASS
SYNC0
SYNCI
ROSC
23
22
GH
S
R
Q
Q
MIN
ON TIME
VSW
VDRV
NON
OVERLAP
21 GL
OSC
20
PGND
14
16
1
V_SO
DBIAS
V_CS
EN
PWMOUT
Current Limit
VNCL
INTERNAL
RAILS
SYNCI
PWM/
PULSE SKIP
FB
2
3
4
CSP
CSN
BANDGAP
6
VPCL
SLOPE
COMP
TSD
OVSD
UVLO
∑
CSA
FAULT
VOUT
VREF
SOFTSTART
+
VCOMP
FB
−
Z
RSTB
15 VSEL
11
10
9
RSTB
SSC
GND
Figure 3. Simplified Block Diagram
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3
NCV891930
PIN FUNCTION DESCRIPTION
Pin No.
QFN24
Pin Name
Description
1
V_CS
Supply input for the internal current sense amplifier. Not intended for external use. Application
board requires a 0.1 mF decoupling capacitor located next to IC referenced to quiet GND
2
3
4
CSP
CSN
Differential current sense amplifier non−inverting input
Differential current sense amplifier inverting input
VOUT
SMPS’s voltage feedback. Inverting input to the voltage error amplifier. Connect VOUT to
nearest point−of−load
5
6
NC
EN
No connection (Note 1)
Logic level inputs for enabling the controller. May be connected to battery
No Connection (Note 1)
7
NC
8
ROSC
SSC
GND
RSTB
SYNCI
Use a resistor to ground to raise the frequency above default value
Soft−start current source output. A capacitor to ground sets the soft−start time
Signal ground. Ground reference for the internal logic, analog circuitry and the compensators
Reset with adjustable delay. Goes low when the output is out of regulation
9
10
11
12
A logic low enables Low I capable operating mode. External synchronization is realized with
Q
an external clock. A logic high enables continuous synchronous operating mode (low I mode
Q
is disabled). Ground this pin if not used
13
SYNCO
Synchronization output active in synchronous operation mode. Refer to table for activation
delay when coming out of low I mode. Connecting to the SYNCI pin of a downstream
Q
NCV891930 results in synchronized operation
14
15
V_SO
VSEL
Supply voltage for the SYNCO output driver. Not intended for external use. Application board
requires a 0.1 mF decoupling capacitor located next to IC referenced to quiet GND
Output programmed to VSEL_LO when connected to ground or when pin is not connected.
Output programmed to VSEL_HI when connected to DBIAS via a 10 kW resistor (optional).
Voltage setting option will be latched prior to PWM soft−start. Latch will be reset whenever the
EN pin is toggled or during a UVLO event
16
DBIAS
IC internal power rail. Not intended for external use other than for VSEL. Application board
requires a 0.1 mF decoupling capacitor located next to IC referenced to quiet GND
17
18
VIN
Input voltage for controller, may be connected to battery
VDRV
5 V linear regulator supply for powering NFET gate drive circuitry and supply for bootstrap
capacitor
19
20
21
22
23
24
VCCEXT
PGND
GL
External 5 V bias supply. Overrides internal high voltage LDO when used. Application board
requires a 1 mF decoupling capacitor located next to IC referenced to PGND
Power ground. Ground reference for the high−current path including the N−FETs and output
capacitor
Push−pull driver output that swings between VDRV and PGND to drive the gate of an external
low side N−FET of the synchronous buck power supply
VSW
GH
Terminal of the high side push−pull gate driver connected to the source of the high side N−FET
of the synchronous buck power supply
Push−pull driver output that swings between SW and BST to drive the gate of an external high
side N−FET of the synchronous buck power supply
BST
The BST pin is the supply rail for the gate drivers. A 0.1 mF capacitor must be connected be-
tween this pin and the VSW pin. Bootstrap pin to be connected with an external capacitor for
powering the high side NFET gate with SW + (VDRV – 0.5 V) and PGND. Blocking diode is
internal to the IC
EPAD
Connect to pin 20 (electrical ground) and to a low thermal resistance path to the environment
1. True no connect. Printed circuit board traces are allowable.
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4
NCV891930
MAXIMUM RATINGS (Voltages with respect to GND unless otherwise indicated)
Rating
Symbol
Value
Unit
V
DC Supply Voltage (Note 2)
EN, VIN, V_CS
VSW
−0.3 to 45
Pin Voltage
t ≤ 50ns
−0.3 to 40
−2
V
Pin Voltage
GH,BST
−0.3 to 45
−0.3 to 7 V with respect to
VSW
V
Pin Voltage
Pin Voltage
CSN, CSP, VOUT
−0.3 to 10
−0.3 to 7
V
V
VDRV, GL,
VCCEXT
Pin Voltage
Pin Voltage
RSTB
−0.3 to 6
V
V
DBIAS, ROSC,
SSC, SYNCO,
V_SO, VSEL
−0.3 to 3.6
Operating Junction Temperature
Storage Temperature Range
T
−40 to 150
°C
°C
kV
−
J(max)
T
−65 to 150
STG
ESD Capability, Human Body Model (Note 3)
Moisture Sensitivity Level
ESD
2
1
HBM
MSL
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 4)
T
SLD
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics (Note 5)
°C/W
Thermal Resistance, Junction−to−Ambient (Note 6)
R
50
13
θJA
JT
Thermal Characterization Parameter, Junction−to−Top (Note 6)
y
5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2
6. Values based on copper area of 600 mm , 4 layer PCB, 0.062 inch FR−4 board with 2 oz. copper on top/bottom layers and 1 oz. copper on
°
the inside layers in a still air environment with T = 25 C.
A
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5
NCV891930
ELECTRICAL CHARACTERISTICS (V = V
= V = 4.5 V to 37 V, V
= V
+ (V
– 0.5V), C
= 0.1 mF, C
= 1 mF.
EN
BAT
IN
BST
SW
DRV
BST
DRV
°
o
Min/Max values are valid for the temperature range −40 C < T < 150 C unless noted otherwise, and are guaranteed by test, design or
J
statistical correlation.
Parameter
VIN_LOW
Test Conditions
Symbol
Min
Typ
Max
Unit
VIN_low threshold
VIN falling
VIN rising
V
7.0
7.3
7.31
7.65
7.65
8.0
V
INLF
INLR
V
VIN_low hysteresis
Response time
V
INLH
0.3
0.37
5.8
0.45
V
−
−
ms
VIN FREQUENCY FOLDBACK MONITOR (VIN_HIGH)
Frequency foldback threshold
VIN rising
VIN falling
V
V
18.4
18.0
−
−
20
19.8
V
FLR
FLF
Frequency foldback
hysteresis
V
FLHY
0.15
0.32
0.45
V
Response time
−
16
−
ms
VIN OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage stop threshold
V
V
37.0
0.5
38.0
1.0
39.0
1.5
V
V
OVSP
Overvoltage hysteresis
OVHY
QUIESCENT CURRENT
Quiescent current
VIN = 13 V, EN = 0 V, T = 25°C
I
I
−
−
−
6.0
6.0
30
−
mA
mA
mA
J
Q,SLEEP
°
VIN = 13 V, EN = 0 V, −40°C < T < 125 C
10
40
J
Q,SLEEP
VIN = 13 V, EN = 5 V, No switching,
I
Q
°
T = 25 C
J
VIN = 13 V, 100 mA load, VOUT = 5 V,
I
−
82
100
mA
Q100
VCCEXT = VOUT, EN = VIN,
T
= 25°C
ambient
(Not production tested. Measured on demo
board, refer to application note section)
DBIAS
DBIAS voltage
C
= 0.1 mF
V
DBIAS
2.0
−
2.4
V
DBIAS
UNDERVOLTAGE LOCKOUT (Note 8)
UVLO start threshold
UVLO stop threshold
UVLO hysteresis
VIN rising
VIN falling
V
V
4.0
3.2
−
−
−
4.5
3.5
−
V
V
V
UVST
UVSP
UVHY
V
0.9
ENABLE
Logic low threshold voltage
Logic high threshold voltage
Enable pin input Current
Will be disabled at maximum value
Will be enabled at minimum value
V
0
1.4
−
−
−
0.8
−
V
V
ENLO
V
ENHI
V
EN
= 5 V
E
0.125
0.26
mA
I,EN
OUTPUT VOLTAGE
Output voltage during regulation IOUT > 100 mA
NCV891930MW00R2G
V
V
OUT,REG
3.3 V (VSEL = GND)
5.0 V (VSEL = DBIAS)
NCV891930MW01R2G
3.65 V (VSEL = GND)
4.0 V (VSEL = DBIAS)
3.234
4.90
3.30
5.00
3.366
5.10
3.577
3.92
3.65
4.00
3.723
4.08
VOUT−GND resistance
EN = V , VIN > 4.5 V
ENLO
R
70
100
130
W
ENLO,VOUT
VSEL
VSEL input low threshold
voltage
V
LVSEL
0
−
0.8
V
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NCV891930
ELECTRICAL CHARACTERISTICS (V = V
= V = 4.5 V to 37 V, V
= V
+ (V
– 0.5V), C
= 0.1 mF, C
= 1 mF.
EN
BAT
IN
BST
SW
DRV
BST
DRV
°
o
Min/Max values are valid for the temperature range −40 C < T < 150 C unless noted otherwise, and are guaranteed by test, design or
J
statistical correlation.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VSEL
VSEL input high threshold
voltage
V
2.0
−
3.3
V
HVSEL
VSEL pin input current
VSEL = DBIAS
V
I,SEL
−
0.25
0.37
mA
RESET
Reset threshold 1
(as a function of VOUT)
VOUT decreasing
VOUT increasing
K
K
90
90.5
92.5
−
95
97
%
UVFAL
UVRIS
Reset hysteresis (ratio of VOUT)
Noise−filtering delay
K
0.5
5
−
−
2
%
RES_HYS
RES_FILT
t
25
ms
Reset delay time
I
I
I
= 1 mA
= 500 mA
= 100 mA
t
1.0
5
24
ms
ms
ms
RSTB
RSTB
RSTB
RESET
4
17
6
32
Reset delay modes
Power good mode (no delay)
Delay mode
(see Detailed Operating Description)
1000
−
−
−
−
600
mA
Reset output low level
I
= 1 mA
V
RESL
−
−
0.4
V
RSTB
Reset threshold 2
(as a function of VOUT)
VOUT increasing
VOUT decreasing
K
105
104
106.5
−
110
109
%
OVRIS
K
OVFAL
VOUT Output Clamp Current
VOUT = V
+ 10 %
I
0.5
1.0
1.5
mA
OUT,reg(typ)
CL,OUT
ERROR AMPLIFIER
Transconductance (Note 3)
Compensation network
Internal to IC
Internal to IC
g
−
26.6
−
mS
kW
M,OTA
R
C
COMP,OTA
NCV891930MW00DRG
3.3 V
5.0 V
−
−
400
506
−
NCV891930MW01DRG
3.65 V
4.0 V
−
−
360
386
−
−
Internal to IC
−
190
−
pF
COMP,OTA
(refer to application note section for die
distributed capacitance modeling information)
Internal to IC
R
−
56.7
−
MW
0,OTA
Slope compensation
NCV891930MW00DRG
NCV891930MW01DRG
S
a
−
−
29.4
39.0
−
−
mV/ms
OSCILLATOR
Switching frequency
R
= open
OSC
4.5 V < VIN <V
/V
f
1.8
0.9
2.0
1.0
2.2
1.1
MHz
FLR FLF
SW
V
/V
< VIN < V
FLR FLF OVSP
Switching frequency – R
4.5 V< VIN <VFLR/VFLF, R
= 9.01 kW
f
2.3
0.36
−
2.5
0.40
49
2.8
0.44
75
MHz
V
OSC
OSC
ROSC
R
reference voltage
R
= 9.01 kW
V
ROSC
OSC
OSC
Minimum off time
t
ns
OFF,MIN
SPREAD SPECTRUM
Modulation Frequency Range
V
/V
< VIN < V
/V
f
f
sw
−
f +
sw
14%
MHz
INLF INLR
FLR FLF
MOD
SYNCHRONIZATION
SYNCO output pulse duty ratio
SYNCO output pulse fall time
SYNCO output pulse rise time
SYNCO Logic High
C
C
C
= 40 pF. SYNCI = 0 or SYNCI = 1
= 40 pF, 90% to 10%
D
40
−
−
4.5
7.0
−
60
−
%
ns
ns
V
LOAD
LOAD
(SYNC)
t
R(SYNC)
= 40 pF, 10% to 90%
t
−
−
LOAD
F(SYNC)
I
= 100 mA source current
V
2.2
3.45
SYNCO
SYNCOHI
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NCV891930
ELECTRICAL CHARACTERISTICS (V = V
= V = 4.5 V to 37 V, V
= V
+ (V
– 0.5V), C
= 0.1 mF, C
= 1 mF.
EN
BAT
IN
BST
SW
DRV
BST
DRV
°
o
Min/Max values are valid for the temperature range −40 C < T < 150 C unless noted otherwise, and are guaranteed by test, design or
J
statistical correlation.
Parameter
SYNCHRONIZATION
SYNCO Logic Low
Test Conditions
Symbol
Min
Typ
Max
Unit
I
= 2 mA sink current
V
−
50
0
−
100
−
0.4
200
0.8
V
kW
V
SYNCO
SYNCOLO
SYNCI pull−down resistance
R
SYNCI
SYNCI input low threshold
voltage
V
LSYNCI
HSYNCI
HSYNCI
SYNCI input high threshold
voltage
V
2.0
−
5.5
V
SYNCI high pulse width
External SYNCI Frequency
Master Reassertion Time
t
100
1.8
−
−
−
ns
MHz
ms
f
2.5
SYNCI
Time from last rising SYNCI edge to first
un−synchronized turn−on.
t
l(SYNC)
SYNCI = VLSYNCI after falling SYNCI
edge
SYNCI = VHSYNCI after falling SYNCI
edge
−
−
1.25
1.75
−
−
SOFT−START CURRENT
Soft−start charge current
Soft−start complete threshold
I
6.9
10
14.3
mA
SS
V
−
1.0
−
V
SS
From EN = 1 until start of charging of soft−
start capacitor
Soft−start delay
t
−
190
75
−
ms
SSDLY
(DBIAS external capacitor = 0.1 mF)
PEAK CURRENT LIMITS
Positive current limit threshold
voltage
0 < (CSP – CSN) < 200 mV
1.2 V < CSN < 10.0 V
VIN < VIN_HIGH
V
V
67.5
72
82.5
88
mV
mV
PCL,2M
0 < (CSP – CSN) < 200 mV
1.2 V < CSN < 10.0 V
VIN > VIN_HIGH
80
PCL,1M
(Guaranteed by design)
Current limit response time
Comparator tripped until GH falling edge,
t
CL
−
39
125
ns
(V
– V
) = V
+ 5 mV
CSP
CSN
CL(typ)
Negative current limit threshold
voltage
−200 mV < (CSP – CSN) < 0
1.2 V < CSN < 10.0 V
V
NCL
−36
−52
−71
mV
Common−mode range
−
−
−
VOUT
0.1
−
1.0
−
V
CSP input bias source current
CSN input bias source current
mA
mA
I
30
BIAS,CSN
GATE DRIVERS
GH sourcing ON resistance
GH sinking ON resistance
GH−VSW resistance
V
– V = 2 V
R
1.6
1.3
−
2.5
2.5
20
5.3
4.3
−
Ω
Ω
BST
GH
GHSOURCE
V
GH
– V
= 2 V
R
SW
GHSINK
R
kΩ
Ω
GH,VSW
GL sourcing ON resistance
GL sinking ON resistance
GL−PGND resistance
V
V
– V = 2 V
R
1.6
1.3
−
2.5
2.5
20
5.3
4.3
−
DRV
GL
GLSOURCE
= 2 V
R
Ω
GL
GLSINK
R
kΩ
GL,PGND
GATE DRIVE SUPPLY
Driving voltage dropout
Driving voltage source current
Backdrive diode voltage drop
Driving voltage
V
V
V
– V
– V
, I
= 25 mA
= 5 mA
V
DRV,DO
−
65
0.3
100
−
0.6
−
V
mA
V
IN
DRV VDRV
= 1 V
I
DRV
IN
DRV
– V , I
V
D,BD
−
0.7
5.30
DRV
VDRV
IN d,bd
I
= 0.1 – 25 mA
V
DRV
4.75
5.00
V
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NCV891930
ELECTRICAL CHARACTERISTICS (V = V
= V = 4.5 V to 37 V, V
= V
+ (V
– 0.5V), C
= 0.1 mF, C
= 1 mF.
EN
BAT
IN
BST
SW
DRV
BST
DRV
°
o
Min/Max values are valid for the temperature range −40 C < T < 150 C unless noted otherwise, and are guaranteed by test, design or
J
statistical correlation.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
GATE DRIVE SUPPLY
VDRV POR start threshold
VDRV POR stop threshold
LDO bypass start threshold
LDO bypass stop threshold
LDO bypass input current
(Note 8)
V
V
3.75
2.85
4.48
4.31
−
4.0
3.1
−
4.25
3.35
4.80
4.65
−
V
V
DRVST
(Note 8)
DRVSP
VCCEXT rising
V
VCCEXT falling
−
V
Pulse skip, VCCEXT = 5 V
VCCEXT = 5 V, VDRV load = 50 mA
3.1
1.93
mA
W
LDO bypass R
1.07
2.79
DS(on)
THERMAL SHUTDOWN
Thermal shutdown threshold
Thermal shutdown hysteresis
T rising
T
155
5
170
15
190
20
°C
°C
J
SD
T
SD,HYS
T falling
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Spread spectrum function will be disabled when IC operated using external frequency synchronization.
8. Operating with VIN near IC UVLO thresholds may result in insufficient gate drive voltage drive amplitude to permit switching of external
MOSFETs. Use of an external bias voltage to maintain sufficient VDRV voltage may be required.
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9
NCV891930
FUNCTIONALITY INFORMATION TABLE
SYNCI
SYNCI
Spread
VIN (V)
pin
Behaviour
Frequency
FUNCTION
SYNCO
Spectrum
ROSC
VIN < Vin_low
Logic−0
Synchronous mode,
recirculation FET turns−off
when −50 mV current sense
voltage is detected.
2 MHz * or less.
Minimum off−time may
be skipped depending
on VIN, output voltage
option and operating
current.
Disabled
Enabled,
2 MHz
Disabled
Disabled
Logic−1
Pulse skip not allowed when
VIN < Vin_low
F
sync
F
if minimum
Enabled
Disabled
F
sync
sync
off−time is not skipped
Vin_low < VIN <
Vin_high (No Pulse
Skip Condition)
Logic−0
Synchronous mode,
recirculation FET turns−off
when when < 0 V current
sense voltage is detected.
f
with spread
Enabled,
follows
spread
spectrum
Enabled
Enabled
ROSC
spectrum.
When exiting
Pulse Skip mode,
function resumes
Disabled during
1−3 500 kHz
pulses upon
Upon exiting Pulse Skip
mode, first 1−3 pulses
500 kHz followed by
2 MHz pulses.
within 14 2 MHz exiting Pulse Skip
pulses.
Mode.
Logic−1
Forced PWM mode,
recirculation FET turns−off
when −50 mV current sense
voltage is detected.
f
with spread
Disabled
Enabled
Enabled
Enabled
ROSC
spectrum
F
sync
F
sync
Enabled
Disabled
F
sync
Disabled
Disabled
Disabled
Disabled
Vin_low < VIN <
Vin_high (Pulse
Skip Condition)
Logic−0
Pulse skip mode
Disabled
Disabled
VIN > Vin_high
X
Synchronous mode,
recirculation FET turns−off
when −50 mV current sense
voltage is detected.
1 MHz
Disabled
Enabled,
2 MHz
Disabled
Disabled
Pulse skip not allowed when
VIN > Vin_high
Soft−start
X
Forced PWM mode with
pulse skip allowed,
2 MHz
Disabled
Disabled
Disabled
Disabled
recirculation FET turns−off
when when < 0 V current
sense voltage is detected
Vout undervoltage
X
X
RSTB activated.
Fixed frequency
No PWM
No change in No change in
Disabled
No PWM
No change in
behaviour
(K
)
behaviour
behaviour
UV
Vout overvoltage
(K
RSB activated.
No PWM
No Change
in behaviour
No PWM
)
OV
*GH off pulses will be skipped to maintain output voltage regulation whenever GH toff is less than toff,MIN occurs.
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10
NCV891930
1
60
50
40
30
20
10
0
GL
GH
0.1
0.01
1
10
100
0
2
4
6
8
10
t
SS
(ms)
Load Capacitance (nF)
Figure 4. Soft−Start Time vs Capacitance
Figure 5. Driver Rise Time vs Load Capacitance
90
85
80
75
70
65
60
55
50
45
40
35
30
25
45
40
35
30
25
20
15
10
5
VCCEXT = OPEN
GL
GH
0
−50 −25
0
25
50
75
100
125 150
0
2
4
6
8
10
Temperature (°C)
Load Capacitance (nF)
Figure 7. Operating Quiescent Current vs
Figure 6. Driver Fall Time vs Load Capacitance
Temperature (5 V/100 mA)
80
79
78
77
76
75
74
73
72
71
70
10
9
8
7
6
5
4
3
2
1
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 8. Quiescent Current (Shutdown) vs
Temperature
Figure 9. Peak Current−Limit Threshold vs
Temperature
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11
NCV891930
100.5%
100.4%
100.3%
100.2%
100.1%
100.0%
99.9%
2.01
2.008
2.006
2.004
2.002
2
1.998
1.996
1.994
1.992
1.99
99.8%
99.7%
99.6%
99.5%
−50
−25
0
25
50
75
100
125
−50 −25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 10. VREF vs Temperature
Figure 11. Oscillator Frequency vs Temperature
4.4
4.3
4.2
4.1
4
29
27
25
23
21
19
17
15
GH: High to Low
GL: Low to High
VIN FALLING
VIN RISING
3.9
3.8
3.7
3.6
3.5
3.4
3.3
GH: Low to High
GL: High to Low
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 12. Non−Overlap Delay vs Temperature
Figure 13. UVLO vs Junction Temperature
5.1
5.08
5.06
5.04
5.02
5
24
22
20
18
16
14
12
10
8
I
= 25 mA
DRV
4.98
4.96
4.94
4.92
4.9
6
4
−50
−25
0
25
50
75
100
125
0.1
0.2
0.3
0.4
0.5
I
Temperature (°C)
RSTBx (mA)
Figure 15. Reset Delay Time vs IRSTBx
Figure 14. VDRV vs Temperature
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12
NCV891930
VIN=6V
VIN=16V
VIN=8V
VIN=18V
VIN=10V
VIN=20V
VIN=12V
VIN=22V
VIN=14V
VIN=34V
VIN=6V
VIN=16V
100
VIN=8V
VIN=18V
VIN=10V
VIN=20V
VIN=12V
VIN=22V
VIN=14V
VIN=34V
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
0.01
0.01
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Output Current (mA)
Output Current (mA)
Figure 16. 3.3 V Demo Board Efficiency
(SYNCI = 0 V)
Figure 17. 5 V Demo Board Efficiency
(SYNCI = 0 V)
DETAILED OPERATING DESCRIPTION
General
♦ −10% at 125°C
• DC bias voltage
Preset internal slope and feedback loop compensation
results in predetermined values for current sense resistors
and output filtering.
♦ −0.6% for 3.3 V, −1.0% of 3.65 V, −1.5% for 4 V,
−3.1% for 5 V
A capacitor technology mix of ceramic and aluminum
polymer or solid aluminum electrolytic capacitors results in
a cost effective solution. Non−solid aluminum electrolytic
capacitors are not recommended due to their large cold
temperature ESR properties. An all ceramic solution filter
implementation using 10 mF capacitor (like the
GCM32DR71C106KA37) was considered for Table 1 and
Table 2 for a design objective of 3% transient voltage for
a 50% load transient. Tolerances used in determining the
number of required capacitors were:
• AC RMS voltage
♦ −4.4%
Additional tolerances such as aging may need to be
considered during the design phase.
At higher currents, optimal inductor and current sense
resistor values may become limited. It may be necessary to
parallel 3 resistor values to achieve the desired current sense
resistor value. The manufacturer’s inductor tolerance and
properties must be considered when determining the current
sense resistor for desired current limiting under worst case
component values.
• Initial tolerance
♦ −10%
• Temperature tolerance
Table 1. MW891930MW00R2G VALUE RECOMMENDATIONS
3.3 V Option
5 V Option
Current
Sense
Resistor (W)
Output
Capacitance
(ceramic) (mF)
Current
Sense
Resistor (W) (Ceramic) (mF)
Output
Capacitance
Inductor
Value (mH)
Inductor
Value (mH)
Output
Current (A)
MOSFET
2
2.2
1.5
0.028
0.018
70
3.3
2.2
0.028
50
80
NVTFS5C478NL
NVMFD5C470NL
NVTFS5C478NL
NVMFD5C470NL
NVTFS5C478NL
NVMFS5C468NL
NVMFS5C468NL
3
110
0.0195
4
5
6
1.0
0.0135
0.011
0.009
140
180
220
1.5
1.2
1.0
0.0135
0.011
0.009
110
120
150
0.80
0.65
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13
NCV891930
Table 2. MW891930MW01R2G VALUE RECOMMENDATIONS
3.65 V Option
4 V Option
Current
Sense
Resistor
(Ω)
Current
Sense
Resistor
(Ω)
Output
Capacitance
(Ceramic)
(mF)
Inductor
Value
Inductor
Value
Output
Capacitance
(ceramic) (mF)
Output
Current
(A)
(mH)
(mH)
MOSFET
2
2.2
0.028
80
2.2
0.028
70
NVTFS5C478NL
NVMFD5C470NL
NVTFS5C478NL
NVMFD5C470NL
NVTFS5C478NL
NVMFS5C468NL
NVMFS5C468NL
3
1.5
0.018
110
1.5
0.018
100
4
5
6
1.0
0.0135
0.011
0.009
150
190
220
1.2
1.0
0.8
0.0135
0.011
0.009
130
170
200
0.80
0.80
Input Voltage
resulting from VIN, output voltage and operating losses, one
or more GH turn−off may be skipped to maintain output
regulation. Despite the default 2 MHz operating frequency,
this skipped pulse will result in the power stage exhibiting
a switching frequency of 1 MHz or less.
An undervoltage lockout (UVLO) circuit monitors the
input and can inhibit switching and reset the soft−start
circuit if there is insufficient voltage for proper regulation.
Depending on the output conditions (voltage option and
loading), the NCV891930 may lose regulation and run in
drop−out mode before reaching the UVLO threshold. When
the input voltage is sufficiently low so that the part cannot
regulate due to maximum duty cycle limitation, the
high−side MOSFET can be kept on continuously for up to
32 clock cycles (16 μs), to help lower the minimum voltage
at which the controller loses regulation.
An overvoltage monitoring circuit automatically
terminates switching and disables the output if the input
exceeds 37 V (minimum). However, the NCV891930 can
withstand input voltages up to 45 V.
GL has a ~140 ns minimum pulse width requirement when
VIN < VIN_LOW. Depending on the duty ratio requirement
To avoid skipping switching pulses and entering an
uncontrolled mode of operation, the switching frequency is
reduced by a factor of 2 when input voltage exceeds the V
IN
frequency foldback threshold (see Figure 18 below).
Frequency reduction is automatically terminated when the
input voltage drops back to below the VIN frequency
voltage foldback threshold. This also helps limit the
MOSFET switching power losses and reduce losses for
generating the drive voltage for the Power Switches at high
input voltage. Above the frequency foldback threshold,
improved efficiency may be expected due to the lower
switching frequency.
FSW
(MHz)
2
1
37
3.2 4.5
18 20
39
45
VIN (V)
Figure 18. NCV891930 Worst−Case Switching Frequency Profile vs Input Voltage
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14
NCV891930
Output Voltage
The output may be programmed to VSEL_LO when
VSEL is ground referenced.
conditions when the SYNCI pin is logic−low. The VOUT
pin sinks 1 mA when any of the following conditions are
present:
When VSEL is connected to DBIAS via an optional 10 kW
resistor, the output voltage is programmed to VSEL_HI.
The output voltage setting option must be selected prior to
enabling the IC via the EN pin. The voltage setting option
will be latched prior to initiation of soft−start. The voltage
option latch will be reset whenever the EN pin is toggled or
during a UVLO event.
• SYNCI = logic−high
• SYNCI is driven by an external clock
• VIN < VIN_low threshold
• VIN > frequency foldback threshold voltage
VCCEXT
VIN supplies VDRV and logic power via the IC’s internal
LDO. VCCEXT pin is ignored if connected to a voltage less
than 5 V or is left unconnected. For improved efficiency, an
external 5 V source may be connected to VCCEXT to permit
bypassing of the internal LDO (Table 3). The LDO bypass
efficiency improvement is reduced at lower currents when
the IC enters pulse−skip mode. An IC power consumption
reduction of about 250 mW has been measured on a demo
board configured with NVMFS5C468NL power transistors
at an input voltage of 13 V.
IC−VIN
A 1 mF decoupling capacitor is recommended between
IC−VIN and ground. PCB layout inductance separating this
decoupling capacitor and the input EMI capacitor may result
in low amplitude high−Q ringing. A 1 W damping resistor
between the PCB VIN and IC−VIN is recommended.
Switching noise will be greater at the high side drain than
at the input EMI ceramic filter capacitor. The trace providing
voltage to IC−VIN should originate from the EMI ceramic
filter capacitor. The VOUT pin sinks 0 mA under typical
Table 3. NCV891930MW00R2G/AR2G 5 V DEMO BOARD TYPICAL IC POWER CONSUMPTION IMPROVEMENT
VCCEXT = VOUT vs VCCCEXT = OPEN, I
> 1 A
OUT
VIN (V)
mW
6
8
10
12
14
279
16
18
9.1
88.7
151
213
386
448
When the NCV891930MW00R2G/AR2G is configured
for a 5 V output (VSEL connected to DBIAS) and VCCEXT
is connected to the power supply’s output, VFB and CSN
traces must be independent from the VCCEXT power trace.
VDRV circuitry gate drive current pulses circulate through
the VCCEXT PCB trace. Voltage disturbance from the trace
parasitic layout inductance will distort CSN and IC−VOUT
measurements.
The IC structure has a 2 series anode−cathode diode path
between pins VCCEXT and VIN (Figure 19). If the
controller VIN power source is disconnected while
VCCEXT is connected to an independent external 5 V
supply, the diode path will deliver current to the converter’s
input. VIN pin may remain biased to VCCEXT minus 2
diode drops and could supply other devices sharing the same
rail as the IC. To avoid unpredictable operating behaviour,
the EN pin must be set to a logic−low state to disable PWM
operation upon disconnection of the IC’s power source and
independent VCCEXT power source must be disabled if the
IC VIN rail is shared by other devices.
Figure 19. VCCEXT to VIN Diode Path
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15
NCV891930
Soft−Start
Following activation of the EN pin, there will be eight
~250 ns GL pulses (500 kHz repetition rate) prior to
initiation of the soft−start to charge the bootstrap capacitor.
During this event, there will be no GH pulses. If VOUT is
< ~0.2 V at EN activation, the pulses are not required and the
logic may disable the eight GL pulses.
Should the power supply output voltage foldback from
current limiting, it is necessary to prevent the feedback
opamp from clamping high to avoid output overshoot when
current limiting ends. If the opamp feedback pin is less than
750 mV, the SSC pin voltage will be discharged to the opamp
feedback voltage + 123 mV (Figure 20). Voltage returns to
nominal regulation via soft−start behaviour.
The NCV891930 features an externally adjustable
soft−start function, which reduces inrush current and
overshoot of the output voltage. Figure 20 shows a typical
soft−start sequence.
Soft−start is achieved by charging an external soft−start
capacitor connected to the SSC pin via an internal 10 mA
current source. Should the FB voltage slew rate be less than
that of the SSC, the SSC pin will be clamped to
V(FB) + 123 mV. Once the SSC voltage is greater than
0.75 V, the clamp is released.
During soft−start, the SYNCI function is disabled and the
controller will operate in diode−emulation mode. Pulse skip
is allowed. The logic will enable the SYNCI function once
SSC voltage exceeds 1.075 V.
EN
Nominal Output Voltage
75% of Nominal Voltage
VOUT
Lowest
Dominates
2.2 V
SSC −123 mV
1 V Reference
+
+
FB
−
SSC
1 V
123 mV
FB
(internal)
Figure 20. Soft−Start Behaviour During Output Overload Current Limiting Event
Expression t may be used to calculate soft−start time for soft−start capacitor C
(Farads).
ss
ssc
1 V
SSC 10 mA
tSS + tSSDLY ) C
(s)
(eq. 1)
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16
NCV891930
STATE DIAGRAM
Figures 21 and 22 and illustrate the state diagram for the NCV891930.
Shutdown
Mode
EN = LOW*
EN = High,
TJ < TSD – TSH,HYS,
Vuv < VIN < Vov
TJ > TSD
OVSD:
VIN > Vov
Over temperature
Protection Circuit
Activated
TJ > 85°C
UVLO:
VIN < Vuv
Fault Logic
Enabled
Vcurrent _sense > VPCL
Pulse
Skipped
SKIP GH PULSE
VCCEXT > LDO
Bypass Threshold
IC Enabled
VCCEXT < LDO
Bypass Threshold
Notes
VSEL Voltage
Option Lock
*At any state, an EN low
signal will bring the part into
shutdown mode.
Internal LDO Bypassed**
SYNCO, Spread
Spectrum, and ROSC
Functionality still
Disabled
** At any state after the IC is
enabled, the VCCEXT
connection can be changed
to bypass the internal LDO or
not.
SEND 8 GL
Pulses
Sent
RESB and
VCCEXT Active, RSTB = 0,
Forced PWM Active, GL Disabled,
No Spread Spectrum
SSC Ramping
Start Up Complete:
SSC ≥ 1.075 V
SSC > 1.075 V
AND
KUV < VOUT < KOV
Default,
ROSC Active,
RSTB = 1
RSTB = 0,
GL Disabled
SSC < 1.075 V OR
VOUT < KUV OR
VOUT > KOV
VIN and ROSC
Dependent Frequency
Logic
SSC > 0.75 V
VOUT < 0.75(VOUT)
SSC Clamped to
V(FB)+ 0.123 V
Figure 21. NCV891930 State Diagram
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17
NCV891930
VIN > VIN_HIGH
VIN < VIN_LO W
VIN_LO W<VIN<VIN_HIGH
FOSC = 1 MHz,
Forced PWM Mode
SYNCO = 2 MHz,
SYNCI, Spread Spectrum,
and ROSC Disabled
VIN > VIN_HIGH
VIN < VIN_LO W
VIN > VIN_HIGH
VIN_LO W<VIN<VIN_HIGH
VIN < VIN_LO W
2 MHz with Spread
Spectrum, SYNCO
Enabled
ROSC, and
Spread Spectrum Disabled.
Forced PWM Mode and
Min. On Time
VIN_LO W<VIN<VIN_HIGH
Enabled.
SYNCI = 0, 1
(FSW = SW node
waveform frequency)
SYNCI = FSYNC
SYNCI = FSYNC
SYNCI = FSYNC
Forced PWM mode,
FOSC and SYNCO = FSYNC,
ROSC Disabled
If Min. Off Time is
not skipped, SYNCO
and FSW = FSYNC
SYNCI = 0
SYNCI = 1
FSW ≤ 2 MHz,
SYNCO = 2 MHz
SYNCI = 0, 1
SYNCI = 0
SYNCI = FSYNC
SYNCI = FSYNC
SYNCI = 1
Diode Emulaꢀon Mode
Pulse Skip Allowed
SYNCI = 0
Forced PWM Mode,
SYNCO = Spread
Spectrum
SYNCI = 1
VCOMP > Pulse
Skip Threshold
ROSC Enabled
SYNCO
SYNCO = 2 MHz,
ROSC Disabled
VCOMP < Pulse
Skip Threshold
ROSC Enabled,
Spread Spectrum
Enabled
Dependent on
ROSC
VCOMP < Pulse
Skip Threshold
Pulse Skip Mode:
First 1-3 Pulses at 500 kHz
followed by 2 MHz Pulses
SYNCO, ROSC, and Spread
Spectrum Disabled
VCOMP > Pulse
Skip Threshold
PULSE SKIP THRESHOLD IS AN INTERNAL VALUE
Figure 22. NCV891930 State Diagram – Dependent Switching Logic
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18
NCV891930
Peak Current Mode Control
As a result of the IC’s CSP−CSN high input impedance,
noise reduction measures should be used for effective noise
immunity from the current sense feedback traces.
The NCV891930 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on*time of the
power switch. The oscillator is used as the frequency clock
to ensure a PWM switching operation. The resulting control
scheme features several advantages over conventional
voltage mode control. First, derived directly from the
inductor, the ramp signal responds immediately to line
voltage transients. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse*by*pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This permits simpler internal compensation.
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be less than a
maximum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. Recommended inductor
values are described in Table 2. Other values may be
possible.
• Current sense resistors have a small inherent parasitic
inductance that will result in a small voltage excursion
equaling L ⋅dI /dt distortion superimposed on the
RSNS L
triangular current sense waveform. The differential
noise resulting from such a distortion can be minimized
with the use of parallel sense resistors. The amplitude
of such a distortion is difficult to predict (data not
normally provided in resistor datasheets), validation of
current limit response during power supply bench
evaluation is required
• Trace routing must not be adjacent to a switch node or
other high noise trace
• Traces should be coincident with of each other on inner
layers to minimize coupling from external radiated
fields. Traces should be shielded by a top or bottom
ground layer (use both layers when possible)
♦ On layers having the feedback traces, there should
be a ground poor next on each side of the traces for
additional shielding
• It is recommended that an output filter ceramic
capacitor be located near RSNS/RSNS1 to help
mitigate output switching noise at RSF2
• An optional R−C−R p−filter on the IC’s CSP/CSN pins
(Figure 24) is sometimes used to filter differential and
common mode noise
Current Sensing (CSP−CSN):
V_CS is derived from VIN. It is a supply input for the
internal current sense amplifier and should never be used to
power external circuitry. The V_CS ceramic decoupling
capacitor a minimum of 50 V voltage rating.
Kelvin connections to current sense resistor (RSNS) are
required. CSP−CSN feedback nodes must not be in−line
with the power path. An example of a good design practice
is to connect the sense lines at the center of the inside edge
of the sense resistors (Figure 23).
♦ To avoid creating a common−mode noise filter
imbalance at the IC current sense pins, simple RC
differential filters are not recommended
♦ The p−filter must be adjacent to the IC to minimize
field induced noise sensitivity on the high
impedance side (IC side) of the filter
♦ If used, a p−filter −3 dB roll−off frequency > 1 MHz
is recommended to prevent the filter transfer
function zero from influencing the feedback loop
response. RSF1 = RSF2 = 49.9 W and
CSF1 = 100 pF is a recommended starting point
RSNS1
RSNS2
Output
L1
CO
RSF1
RSF2
Place RSF1, RSF2 and
CSF1 near CSP−CSN
IC pins
CSF1
Figure 24. Current Sense Resistor p−Filter
Figure 23. Kelvin Sense Location for Parallel Current
Sense Resistors
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19
NCV891930
CSN pin sources a bias current of amplitude I
.
The RSTB signal can either be used as a reset with delay
or as a power good (no delay). The delay is determined by
the current into the RSTB pin, set by a resistor, show in
Figure 25.
BIAS,CSN
RSF2 will create a voltage offset on the CSP−CSN
differential current sense current. This offset may be taken
into account using the following current CSP−CSN current
sense expression.
VOUT
VCSP_CSN
VRSNS ) RSF2⋅IBIAS_CSN
(eq. 1)
IL_PEAK
+
+
RSNS
RSNS
RRSTB
There is a diode path between IC−CSN and IC−VOUT.
This diode path could conduct and interfere with the
feedback loop if an appreciable voltage drop is present
between the 2 pins. Intentional voltage drop on the power
path between the CSN side of the current sense resistors
(CSN) and the IC−VOUT feedback kelvin point is to be
avoided.
RSTB
RST
Short Circuit Protection
When the peak inductor current reaches the current limit
threshold, duty−cycle limiting occurs and output voltage
will be foldback accordingly.
A GH pulse skip will occur under severe short−circuit
conditions if the inductor current exceeds the peak current
limit threshold at the beginning of the next GH activation
cycle. GL pulses will continue to operate during this GH
pulse skip operation.
Figure 25. Reset Delay Time
Use the following equation to determine the ideal reset delay
time using currents less than 500 mA:
9.9
tRESET
+
(eq. 2)
4⋅IRSTBx
Reset
where:
The RSTB pin is a high impedance node. To minimize
noise coupling onto its PCB connected trace, care must be
exercised during PCB layout to avoid running the trace
adjacent to a switching node.
When EN is in low−state irrespective of VIN voltage,
RSTB is floating (high impedance).
t
I
: ideal reset delay time (ms)
: current into the RSTB pin (mA)
RESET
RSTB
Using I
= 1 mA removes the delay and allows the
RSTB
reset to function as a “power good” pin.
The RSTB resistor is commonly tied to VOUT. A RSTB
resistor value setting the current at the reset pin in the range
of 0.6 mA to 1 mA is not recommended due to the variation
of the threshold between a set delay time and power good.
Depending on the output voltage option, typical reset delay
times pull−up can be achieved with the following resistor
values.
When the voltage on the VOUT pin is out of regulation
(below K
or greater than K ), the open−drain
UVRIS
UVFALL
output RSTBx is asserted (pulled low) after a short
noise−filtering delay (t ). A pull−up resistor is
RES−FILT
required to generate a logic−high signal on this open−drain
pin and to set the delay time, simplifying the connection to
a micro−controller. The pin can be left unconnected if the
function is unused.
Table 4.
R
t
(ms) – VSEL_LO
t
(ms) – VSEL_HI
RESET
RSTB
RESET
(kW, VOUT Pull−Up)
(VOUT = 3.3 V)
(VOUT = 5 V)
6.65
10
5
−
7.5
5
15
11.3
15.0
18.7
24.9
7.4
9.9
12.3
16.4
20
24.9
33.2
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20
NCV891930
In the event of an overvoltage (VOUT > K
), an
UVRIS
When VIN < VIN_LOW and VOUT falls below
internal comparator enables a 1 mA current source discharge
path on VOUT within typically 2.7 ms. The overvoltage
comparator is set 7.5% above the 1 V feedback voltage
reference (i.e. 1.075 V) and has a 68 mV hysteresis.
regulation, the period on GH pin on−time is 16 μs and the
off−time is 200 ns (Figure 27). If this occurs while operating
under light load, the VSW pin has 70 ns to decay below
0.4 V for the internal logic to set the GL pin high. If the VSW
pin is greater than 0.4 V after 70 ns, the GL pin will be forced
high for 100 ns (Figure 28).
Enable
An EN pin ground referenced resistor is not required. The
IC has a pull−down current (E
). For low system I
I,EN
Q
200 ns
operating requirements, such a resistor would result in a
larger input quiescent current consumption when the IC is in
an enabled state.
The NCV891930 is designed to accept either a logic−level
signal or battery voltage as an Enable signal. However, if
voltages above 45 V are expected, EN should be tied to VIN
through a 10 kW resistor to limit the current flowing into the
pin’s internal ESD clamp.
GH
70 ns
GL
100 ns
Figure 27. Gate Drive Waveforms for VSW < 0.4 V
Within 70 ns of GH Going Low
A low signal on Enable induces a shutdown mode which
shuts off the regulator and minimizes its supply current to
less than 6 mA by disabling all functions. Pull−down
200 ns
GH
R
between IC−VOUT and IC−GND is present if
ENLO_VOUT
GL
VIN > 4.5 V to permit discharging the power supply output
voltage.
> 100 ns
Once the IC is enabled, a soft−start is always initiated.
The IC has internal filtering to prevent spurious operation
Figure 28. Gate Drive Waveforms for VSW > 0.4 V
After 70 ns of GH Going Low
from noise on EN. There is a t
delay between the EN
SSDLY
command entering a logic−high state and initiation of
soft−start activity on pin SSC. There is an approximately
15 μs delay between the EN command entering a logic−low
state and cessation of PWM activity.
Feedback Voltage Error Amplifier
An operational transconductance amplifier (OTA) is used
to condition the feedback voltage information. The OTA
output can sink/source up to 3 μA. During normal operation,
the minimum error amplifier voltage operates between a
minimum of 1.0 V and 2.2 V.
t
delay
EN
GH
During startup, there is no minimum clamp voltage on the
OTA output.
At light load, the logic will enter pulse−skip operating
mode. During pulse−skip mode the minimum voltage clamp
is 0.975 V, changing to 1.075 V during initial low frequency
pulse burst (up to 3 pulses).
Figure 26. EN Low Response Behaviour
The voltage feedback and compensation networks are
The low I IC feature is active in diode−emulation mode
Q
represented in Figure 29. Z (s) and Z (s) are resistor
U
L
only. With exception of the overtemperature protection
function and output voltage monitoring function used to
initiate GH pulse bursts for output voltage regulation,
non−essential functions are turned−off to minimize
quiescent current consumption.
networks used as the input voltage feedback divider. R and
o
C are the OTA output impedance characteristic. Z
(s) is
o
comp
the OTA compensation network establishing the cross−over
frequency and phase margin. Block A(s) is a level shift block
having an AC gain of 0.1875.
The silicon implementation of the compensation resistor
Duty Cycle and Maximum Pulse Width Limits
in Z (s), Z (s), and Z (s) consists of numerous series
Maximum GH duty ratio is defined by t , the
off,MIN
U
L
comp
connected high resistance segments. Each resistor segment
has a very low parasitic capacitance to ground. On a
cumulative basis, the distributed capacitances may not be
neglected as they affect the feedback loop phase response at
cross−over frequency. A feedback loop analysis making use
minimum permissible GH off time. When this maximum
duty ratio is reached while VIN < VIN_LOW, one or more
GH off cycle pulse will be skipped to permit maintaining
output voltage regulation. Although the internal 2 MHz
clock frequency remains unchanged, skipping a GH off
pulse results in a measured reduction of the operating
frequency. For instance, skipping a single GH off pulse
results in a 1 MHz measured waveform frequency.
of datasheet parameters R
and C
without taking
comp
comp
into account the described distributed capacitances is to be
avoided.
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21
NCV891930
The web model contains the necessary information to
establish analytical models for Z (s), Z (s), Z (s) and
minimizing the body diode conduction time, while
protecting against cross−conduction (shoot−through) of the
MOSFETs. A block diagram of the non−overlap and gate
drive circuitry used in the chip and related external
components are shown in Figure 30.
U
L
comp
A(s). Z (s) and Z
(s) will be different between VSEL
L
comp
output voltage options.
Vout
The GL driver is enabled when VSW is less than the
non−overlap detection comparator threshold of 0.4 V. The
GL driver response time is dependent on the comparator
differential voltage that develops below the 0.4 V detection
threshold; approximately 25 ns response time may be
expected when operating in continuous conduction mode.
To maintain output voltage regulation when SYNCI = 0 V
(or open) and VINLx < VIN < VINH, GH on−time may be
as low as 0 ns during non−pulse skipping mode operation.
ZU(s)
VFB
−
Vc
A(s)
Vctrl
gm
Vref
+
ZL(s)
Ro
Co
Zcomp(s)
MOSFET response will depend on its Q (tot)
characteristics.
Figure 29. OTA Feedback and Compensation Block
Diagram
g
If the SW pin voltage is still greater than 0.4 V 70 ns
following the rising edge of the SYNCI pulse, the IC logic
will send a GL pulse to force a recharge of the bootstrap
capacitor. The GL pulse width will be no greater than the
SYNCI pulse width minus 70 ns. The GL pulse width must
be of sufficient duration to fully turn−on the low side
MOSFET. The time duration required to turn−on the low
side MOSFET will be dependent on the MOSFET’s gate
charge specification.
The GH driver is enabled when GL voltage is less than the
non−overlap detection comparator threshold of 2 V. The GH
driver response time is dependent on the comparator
differential voltage that develops below the 0.4 V detection
threshold; response time is approximately 40 ns.
Bootstrap
During startup, the bootstrap capacitor is charged by a
sequence of eight 250 ns GL pulses having a 2 μs period
before the SSC pin is allowed to ramp up. For additional
details, refer to the Soft−Start detailed application
information.
Drivers
The NCV891930 has a gate drivers to switch external
N−Channel MOSFETs. This allows the NCV891930 to
address high−power, as well as low−power conversion
requirements. The gate drivers also include adaptive
non−overlap circuitry. The non−overlap circuitry increases
efficiency, which minimizes power dissipation, by
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22
NCV891930
BST
24
VIN
17
VCCEXT
19
VDRV
18
LDO
5 V LDO
13
12
8
BYPASS
SYNC0
SYNCI
ROSC
23
22
GH
S
R
Q
Q
MIN
ON TIME
VSW
VDRV
NON
OVERLAP
21 GL
OSC
20
PGND
14
16
1
V_SO
DBIAS
V_CS
EN
PWMOUT
Current Limit
VNCL
INTERNAL
RAILS
SYNCI
PWM/
PULSE SKIP
FB
2
3
4
CSP
CSN
BANDGAP
6
VPCL
SLOPE
COMP
TSD
OVSD
UVLO
∑
CSA
FAULT
VOUT
VREF
SOFTSTART
+
VCOMP
FB
−
Z
RSTB
15 VSEL
11
10
9
RSTB
SSC
GND
Figure 30. Simplified Block Diagram
A capacitor is placed from VSW to BST and an internal
bootstrap diode is located between VDRV to BST to create
a bootstrap supply on the BST pin for the high−side floating
gate driver. This ensures that the voltage on BST is about
doesn’t run out of headroom. VDRV must supply charge to
both the BST capacitor and the low−side driver, so the
VDRV capacitor must be sufficiently larger than the BST
capacitor. A 10:1 VDRV/BST capacitor ratio is effective. A
1 mF VDRV capacitor along with a 0.1 mF BST capacitor is
recommended.
Careful selection and layout of external components is
required to realize the full benefit of the onboard drivers.
The capacitors between VINand GND and between BST and
VSW must be placed as close as possible to the IC. The
current paths for the GH and GL connections must be
optimized to minimize PCB parasitic resistance and
inductance.
4.5 Vhigher than V to drive the high−side MOSFET. The
SW
boost capacitor supplies the charge used by the gate driver
to charge up the input capacitance of the high−side
MOSFET, and is typically chosen to be at least a decade
larger than its gate capacitance. Since the BST capacitor
recharges when the low−side MOSFET is on, pulling VSW
down to ground, the NCV891930 has a minimum off−time.
This also means that the BST capacitor cannot be arbitrarily
large, since VDRV needs to be able to replenish charge
during this minimum off−time so the high−side gate driver
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23
NCV891930
SYNC Feature
Diode−Emulation Mode
V_SO is a supply voltage strictly intended for the SYNCO
output driver and should never be used to power external
circuitry. The V_SO ceramic decoupling capacitor a
minimum of 5 V voltage rating. Ground this pin if not used.
An external pulldown resistor is recommended at the
SYNCI pin if the function is unused. The SYNCO pulse may
be used to synchronize other NCV891930 ICs. If a part does
not have its switching frequency controlled by the SYNCI
input, the part will operate at the oscillator frequency. A
rising edge of the SYNCI pulse causes an NCV891930 to
send a GH pulse. If another rising edge does not arrive at the
SYNCI pin, the NCV891930 oscillator will take control
after the master reassertion time delay which may last up to
3 clock cycles if SYNCI is stopped at logic−low level, up to
4 cycles if SYNCI is stopped at logic−high level. During the
master reassertion time, GH will be off and GL will be
active−high (i.e. switch node tied to ground). As a result,
SYNCI operating mode change is not advised.
Diode−emulation mode is active when SYNCI is either
open or grounded. A comparator in the current sense block
detects the CSP−CSN voltage transition from a positive
voltage (positive inductor current) to 0 V (0 A inductor
current). When 0 A is detected, the bottom GL signal turns
off the low side MOSFET to prevent negative inductor
current.
Pulse−Skip Mode
Pulse−skipping is used at near discontinuous conduction
mode operation as a method to improve low current
operating efficiency. Pulse−skip PWM regulation is used to
mimic discontinuous conduction mode (DCM) behaviour
(Figure 32). The architecture does not use current sensing
for pulse−skip detection. The current sense amplifier
response time and its input voltage hysteretic characteristics
would have resulted in potentially objectionable output
voltage ripple. Instead, the internal voltage feedback OTA
compensation output voltage (VCOMP) is used to monitor
near−DCM operating condition.
After soft−start event, SYNCO becomes active when SSC
voltage > 1.075 V. V
requires about 2 V headroom
HSYNCI
from VIN to for its rated amplitude. Amplitude will be
reduced when VIN is below approximately 5 V.
During pulse−skip mode, the oscillator enters sleep mode
• When VCOMP reaches a predetermined lower voltage
threshold, the IC control logic enters pulsed−skip mode
to maintain regulation. Some output voltage ripple
associated with the pulse skipping is to be expected
for low I operation power management and SYNCO is
Q
inactive. SYNCO functionality resumes when the IC exits
pulse−skip mode.
When active, SYNC0 is in phase with SYNCI (Figure 31).
Rise/fall edge waveforms have a typical 10 ns delay relative
to corresponding SYNCI waveform edges.
SYNCO will be a fixed frequency 2 MHz signal under
normal voltage when part is in current limit and VOUT
• Low−I operating mode is entered during
Q
pulse−skipping event, permitting higher efficiency
operation under low output power operation. The
duration is dependent on operating conditions. When
the controller exits pulse−skip mode, normal PWM
regulation is preceded by up to three 500 kHz pulses
drops by 7.5% (K ). The VOUT pin sinks 0 mA under
UVFAL
typical conditions when the SYNCI pin is logic−low. The
VOUT pin sinks 1 mA when any of the following conditions
are present:
(2 MHz/4) as internal logic comes out of low−I mode
Q
• As the OTA VCOMP is used for feedback control, the
VCOMP will not remain constant, increasing to resume
PWM activity
• SYNCI = logic−high
• SYNCI is driven by an external clock
• VIN < VIN_low threshold
• VIN > frequency foldback threshold voltage
Ch 1: Power supply output voltage (50 mV/div)
Ch 2: Power supply input voltage
(between input EMI filter and buck converter, 20 mV/div)
Ch 3: Output inductor current (1 A/div)
Ch 4: IC gate high (GH) (10 V/div)
Figure 32. IC Pulse−Skip PWM Behaviour, Borderline
Pulse−Skip Region
Ch 1: SYNCI (2 V/div)
Ch 2: SYNCO (5 V/div)
Ch 3: GH (10 V/div)
Ch 4: GL (5 V/div)
Figure 31. SYNCO Behaviour
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NCV891930
The thermal shutdown protection circuitry is activated at
peak inductor current occurs after this propagation delay,
duty ratio will decrease.
T ≈ 85°C and remains active during pulse−skipping,
J
consuming additional quiescent current.
Oscillator
ROSC resistance value will have no influence on f
Feedback Loop Measurement
SW
The compensation network and voltage feedback OTA are
internal to the IC. Monitoring points permitting
measurements of the modulator control−to−output response
and the OTA compensation network are not accessible. The
open−loop−response in closed−loop−form may be measured
by injecting a signal between the power supply output and
IC−VOUT. The signal injection path must not share a power
path; traces to IC−VCCEXT and IC−CSN must kept outside
the signal injection path.
When operating in diode−emulation mode, the OTA
feedback loop is disabled when pulse skipping occurs and a
hysteretic type mode control is activated. It may be found in
literature that feedback loop measurements from small
signal injection with hysteretic control yields meaningless
information.
below 2 MHz. ROSC and f
frequency range of 2 MHz (46 kW) to 2.5 MHz (9.01 kW)
with the following expression.
may be calculated for a
ROSC
ROSC + a⋅(fROSC * b)c kW
(eq. 3)
Where
a = 5.5689
b = 1.8638
c = −1.0380
f
expressed in MHz
ROSC
ȡ
ȣ
MHz
Ȥ
B
fROSC + 2 @ A )
(eq. 4)
ȧ
Dȧ
Ǔ
ROSC
C
1 ) ǒ
Ȣ
Where
A = 0.93976
B = 3.6294
C = 0.93511
D = 1.04638
Current Limiting and Overcurrent Protection
Current limit activation propagation delay between the
sense resistor reaching the threshold and the GH gate turning
off is typically about 39 ns delay. Voltage regulation
continues despite slight increase in peak inductor current as
a consequence of this current limit propagation delay. If the
ROSC expressed in kW
When operating under frequency foldback conditions, the
frequency will be 1 MHz.
f
ROSC
Figure 33. fROSC vs ROSC
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NCV891930
Spread Spectrum
radiated emissions with some spread spectrum techniques.
Spread spectrum is a method used to reduce the peak
electromagnetic emissions of a switching regulator.
In SMPS devices, switching translates to higher
efficiency. As a consequence, the switching also leads to a
higher EMI profile. We can greatly reduce some of the peak
Time Domain
Frequency Domain
Unmodulated
V
t
fc 3fc 5fc 7fc 9fc
Modulated
V
t
fc 3fc 5fc 7fc 9fc
Figure 34. Spread Spectrum Comparison
The NCV891930 has spread spectrum functionality for
reduced peak radiated emissions. This IC uses a
pseudo−random generator to set the oscillator frequency to
one of 8 discrete frequency bins. Each digital bin represents
a shift in frequency by 40 kHz over the range 2.0 MHz to
2.28 MHz. Over time, each bin is used an equal number of
times to ensure an even spread of the spectrum. This reduces
the peak energy at the fundamental 2 MHz frequency, and
spreads it into a wider band.
The period of each cycle will change inversely to the
switching frequency but the duty cycle, however, will
remain constant.
Thermal Shutdown
A thermal shutdown circuit inhibits switching and resets
the soft−start circuit if internal temperature exceeds a safe
level indicated by the thermal shutdown activation
temperature (T ). Switching is automatically restored
SD
when temperature returns to a safe level based on the thermal
shutdown hysteresis (T
).
SD,HYS
Table 5. PSEUDO−RANDOM FREQUENCY BINS
Efficiency
14% Pseudo Random Bin #
Switching Frequency
2.00 MHz
During the brief time duration when both high−side and
low−side transistors are turned−off, free−wheeling current
flows through the low−side transistor’s intrinsic body diode.
An optional Schottky diode across the low−side transistor
may be used for an incremental efficiency improvement.
Efficiency curves for NCV891930 5 V demo board
(VCCEXT = VOUT) are shown in Figure 35.
0
1
2
3
4
5
6
7
2.04 MHz
2.08 MHz
2.12 MHz
2.16 MHz
2.20 MHz
2.24 MHz
2.28 MHz
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NCV891930
VIN=6V
VIN=16V
VIN=8V
VIN=18V
VIN=10V
VIN=20V
VIN=12V
VIN=22V
VIN=14V
VIN=34V
100
90
80
70
60
50
40
0
1000
2000
3000
4000
5000
6000
Output Current (mA)
Figure 35. Efficiency vs Load Current (5 V Demo Board, SYNCI = 0 V)
Exposed Pad
recommended to connect these two pins directly to the
EPAD with a PCB trace. Recommended layout information
may be found on the web accessible demo board
information.
The EPAD must be electrically connected to both the
analog and the power electrical ground GND and PGND
pins on the PCB for proper, noise−free operation. It is
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27
NCV891930
APPLICATIONS INFORMATION
Design Methodology
case, the frequency can be programmed to a lower value
with ROSC and then a higher−frequency signal can be
applied to the SYNC pin to increase the frequency
dynamically to avoid given frequencies. A spread spectrum
signal could also be used for the SYNC input, as long as the
lowest frequency in the range is above the programmed
frequency set by ROSC. Additionally, the highest SYNC
frequency must not exceed maximum switching frequency
limits.
Choosing external components encompasses the following
design process:
1. Operational parameter definition
2. Switching frequency selection (ROSC)
3. Output inductor selection
4. Current sense resistor selection
5. Output capacitor selection
6. Input capacitor selection
There are two limits on the maximum allowable switching
frequency: minimum off−time and minimum on−time.
These set two different maximum switching frequencies, as
follows:
7. Thermal considerations
(1) Operational Parameter Definition
Before proceeding with the rest of the design, certain
operational parameters must be defined. These are
application dependent and include the following:
1 * DMAX
fS(MAX)1
+
(eq. 8)
TMinOff
V : input voltage, range from minimum to
IN
maximum with a typical value [V]
DMIN
V : output voltage [V]
OUT
fS(MAX)2
+
(eq. 9)
TMinOn
I
: output current, range from minimum to
OUT
maximum with initial start−up value [A]
: desired typical current limit [A]
A number of basic calculations must be performed
where: f
minimum off−time [Hz]
: maximum switching frequency due to
S(MAX)1
I
CL
T
: minimum off−time [s]
MinOff
up−front to use in the design process, as follows:
f
: maximum switching frequency due to minimum
S(MAX)2
VOUT
on−time [Hz]
DMIN
+
T
: minimum on−time [s]
(eq. 5)
(eq. 6)
(eq. 7)
MinOn
VIN(MAX)
VOUT
Alternatively, the minimum and maximum operational
input voltage can be calculated as follows:
D +
VOUT
VIN(TYP)
VIN(MIN)
+
(eq. 10)
(eq. 11)
1 * TMINOff⋅fs
VOUT
VOUT
DMAX
+
VIN(MAX)
+
VIN(MIN)
TMINOn⋅fs
where: D
: minimum duty cycle (ideal) [%]
: maximum input voltage [V]
MIN
where: f : switching frequency [Hz]
S
V
IN(MAX)
The switching frequency is programmed by selecting the
resistor connected between the ROSC pin and ground. The
grounded side of this resistor should be directly connected
to the GND pin. Avoid running any noisy signals beneath the
resistor, as injected noise could cause frequency jitter. The
graph in Figure 33 shows the required resistance to program
the frequency.
D: typical duty cycle (ideal) [%]
V
D
V
: typical input voltage [V]
: maximum duty cycle (ideal) [%]
IN(TYP)
MAX
: minimum input voltage [V]
IN(MAX)
These are ideal duty cycle expressions; actual duty cycles
will be marginally higher than these values. Actual duty
cycles are dependent on load due to voltage drops in the
MOSFETs, inductor and current sense resistor.
(3) Output Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the power supply, a minimum
inductor value is particularly important in space−
constrained applications. From an electrical perspective, an
inductor is chosen for a set amount of ripple current and to
assure adequate transient response.
(2) Switching Frequency Selection (ROSC)
Selecting the switching frequency is a trade−off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values to achieve the same inductor current ripple
and output voltage ripple. However, increasing the
frequency increases the switching losses of the MOSFETs,
leading to decreased efficiency, especially noticeable at light
loads.
Larger inductor values limit the switcher’s ability to slew
current through the output inductor in response to output
Typically, the switching frequency is selected to avoid
interfering with signals of known frequencies. Often, in this
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28
NCV891930
load transients, impacting incremental dynamic response.
expression to 0 W if there is no filter)
: peak inductor current at rated output current [A]
K: design margin to account for inductor variation as well as
extra current required to support load transient response. A
value of ~120% is commonly used [%].
While the inductor is slewing current during this time,
output capacitors must supply the load current. Therefore,
decreasing the inductance allows for less output capacitance
to hold the output voltage up during a load transient.
I
L(PK)
A ripple current dI equaling 20−40% of the output rated
Alternative current measurement methods such as
lossless inductor current sensing may be feasible but beyond
the scope of this document.
L
current is a typical objective when selecting an inductor
value for a duty ratio D normally selected at the nominal
input operating voltage. The inductor value may be
calculated using the following expression:
(5) Output Capacitor Selection
When used in conjuncture with ceramic capacitors,
(
)
VOUT⋅ 1 * D
aluminum
polymer/hybrid
bulk
capacitors
are
L +
(eq. 12)
recommended instead of aluminum electrolytic capacitors
dIL⋅fs
°
°
due to their low −40 C/25 C ESR ratio. Use of EMI bulk
Inductor saturation current is specified by inductor
manufacturers as the current at which the inductance value
has dropped a certain percentage from the nominal value,
typically 10−30%. It is recommended to choose an inductor
with saturation current sufficiently higher than the peak
output current, such that the inductance is very close to the
nominal value at the peak output current. This introduces a
safety factor and allows for more optimized compensation.
Inductor efficiency is another consideration when
selecting an output inductor. Inductor losses include DC and
AC winding losses as well as core losses. Core losses are
proportional to the amplitude of the ripple current and
operating frequency.
AC winding losses are based on the AC resistance of the
winding and the RMS ripple current through the inductor,
which is much lower than the DC current. AC winding losses
are due to skin and proximity effects and are typically much
less than the DC losses, but increase with frequency. The DC
winding losses in the inductor can be calculated with the
following equation:
°
°
capacitors having a high −40 C/25 C ESR ratio may result
in an ineffective output filter along with potential stability
issues under cold temperature operating conditions.
The output capacitor is a basic component for the fast
response of the power supply. During the first few
microseconds following a load step, it supplies the
incremental load current. The controller immediately
recognizes the load step and increases the duty cycle, but the
current slew rate is limited by the inductor. During a load
release, the output voltage will overshoot. The capacitance
will decrease this undesirable response, decreasing the
amount of voltage overshoot.
The worst case is when initial current is at the current limit
and the initial voltage is at the output voltage set point,
calculating. The overshoot is:
L
+ Ǹ
dVOS(MAX)
⋅ICL 2 ) VOUT 2 * VOUT
(eq. 15)
C
Accordingly, a minimum amount of capacitance can be
chosen for a maximum allowed output voltage overshoot:
PL(DC) + IOUT 2⋅RDC
(eq. 13)
2
L⋅ICL
(eq. 16)
Cmin
+
where: P
: DC winding losses in the output inductor
L(DC)
ǒ
Ǔ
dVOS(MAX)⋅ 2⋅VOUT ) dVOS(MAX)
R
: DC resistance of the output inductor (DCR)
DC
where: C
voltage overshoot to dV
: minimum amount of capacitance to minimize
MIN
(4) Current Sense Resistor Selection
[F]
OS(MAX)
Current sensing for peak current mode control relies on
the amplitude of the inductor current. The current is
translated into a voltage via a current sense resistor placed
in series with the output inductor located between the output
inductor and capacitors. The resulting voltage is then
measured differentially by a current sense amplifier,
generating a single−ended output to use as a control signal.
If a current sense p−filter is implemented as in Figure 24, the
following expression may be used to determine the current
sense resistor value.
dV
: maximum allowed voltage overshoot during a
OS(MAX)
load release to 0 A [V]
A maximum amount of capacitance can be found based on
the output inductor overshoot current and current limit. To
calculate the output inductor startup overshoot current, the
following approximation may be used (inductor ripple
current not considered):
COUT⋅V
+
(eq. 17)
IL(OS)
OUT ) IOUT(i)
tss
VPCL,N ) RSF2⋅ICSN
where: I
: Output inductor overshoot current during
L(OS)
Ri +
(eq. 14)
startup [A]
: Output current during startup [A]
IL(PK)⋅K
I
OUT(i)
Where V
: positive current limit threshold voltage [V]
PCL,N
R
SF2
: p−filter CSN−V
resistor [W] (set value in
OUT
www.onsemi.com
29
NCV891930
During soft−start, the inductor current must provide current
where: P
= power loss from the input capacitors
CIN
to the load as well as current to charge the output capacitor.
The current limit defines the maximum current which the
inductor is allowed to conduct. Setting the inrush current to
the current limit places a limit on the maximum capacitor
value (inductor ripple current not considered) as follows:
R
= effective series resistance of the input
ESR(CIN)
capacitance
Due to large current transients through the input
capacitors, electrolytic, polymer or ceramics should be used.
Aluminum electrolytic specifications often require closer
scrutiny due to poor ESR cold temperature characteristics.
As a result of the large ripple current, it is common to place
ceramic capacitors in parallel with the bulk
electrolytic/polymer input capacitors to reduce switching
voltage ripple. A value of 0.01 μF to 0.1 μF placed near the
MOSFETs is also recommended.
ǒ
Ǔ
ICL * IOUT ⋅tss
(eq. 18)
CMAX
+
VOUT
where: C
: maximum output capacitance [F]
MAX
Capacitors should also be chosen to provide acceptable
output voltage ripple with a DC load, in addition to limiting
voltage overshoot during a dynamic response. Key
specifications are equivalent series resistance (ESR) and
equivalent series inductance (ESL). The output capacitors
must have very low ESL for best transient response. The
PCB traces will add to the ESL, but by positioning the output
capacitors close to the load, this effect can be minimized and
ESL neglected when determining output voltage ripple.
Output impedance magnitude of the EMI filter
Z
(f) must be much smaller than input impedance
outFILTER
magnitude of the filtered converter Z
(f).
inSMPS
ŤZ
(f)Ť<<ŤZ
(f)Ť
(eq. 23)
outFILTER
inSMPS
Analysis of these impedances may require complex
calculations or simulations. For simple LC input EMI filters,
a good first order approximation for evaluating the
inequality may be obtained with the use of the following
approximation:
The total peak−to−peak ripple dV
is defiǓned as:
OUT
1
(eq. 19)
ǒ
dVOUT + dIL⋅
) rESR
LEMI
8⋅C⋅fSW
(eq. 24)
ZoutFILTER
[
Ǹ
CEMI
Where: dV
: total output voltage ripple due to output
OUT
capacitance and its ESR [V ]
VIN 2⋅h
pp
(eq. 25)
ZinFILTER
[
r
: output capacitor ESR [W]
ESR
POUT
Capacitor ESR corresponding to the operating frequency f
s
where: h = power supply efficiency [%]
must be used. The steady−state power lost from the capacitor
ESR may be calculated as follows:
(7) Thermal Considerations
1
This controller is intended to be used in applications
where currents of up to 6 A may exist. The following should
be considered for best performance.
• Use of 2 oz (70 micron) copper for the high current
handling layers
• 4 layer (or more) boards are best suited to facilitate
thermal management of lossy devices (output inductor,
MOSFETs, IC)
(eq. 20)
PC(ESR)
+
⋅dIL 2⋅rESR
3
(6) Input Capacitor Selection
The input EMI capacitors must sustain the ripple current
produced during the on time of the high−side MOSFET and
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
Ǹ
(eq. 21)
(
)
IIN(RMS) + IOUT⋅ D⋅ 1 * D
♦ High frequency layout methods dictate that the
controller will be placed near the synchronous
MOSFET switches. Inadequate thermal management
of the power dissipating devices will result in
significant localized PCB temperature rise from
thermal coupling between devices and case−ambient
thermal resistances. Resulting IC (and MOSFET)
case temperatures may become significantly higher
than ambient temperature
where: I
= input RMS current [A]
IN(RMS)
The peak harmonic current will be at the switching
frequency. The above equation reaches its maximum value
/2. The input capacitors must
be rated to handle the RMS ripple current.
with D = 0.5, I
= I
IN(RMS)
OUT
Input capacitor RMS current losses may be calculated with
the following equation:
PCIN + IIN(RMS) 2⋅RESR(CIN)
(eq. 22)
Maximizing thermal dissipation surface area beneath the
IC along with liberal use of thermal vias is recommended.
www.onsemi.com
30
NCV891930
Table 6. ORDERING INFORMATION
†
Device
Status
Output Voltage
Marking
Package
Shipping
QFN24
(Pb−Free)
4000 / Tape & Reel
NCV891930MW00R2G
Not Recommended
for New Designs
3.3 V/5.0 V
3.65 V/4.0 V
3.3 V/5.0 V
3.65 V/4.0 V
V8919
3000
NCV891930MW01R2G
NCV891930MW00AR2G
NCV891930MW01AR2G
Not Recommended
for New Designs
V8919
3001
Recommended
8919A
3000
Recommended
8919A
3001
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: The NCV891930 will not offer the alternate construction leadframe version illustrated in Detail A and Detail B in the Package
Dimensions.
www.onsemi.com
31
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW24 4x4, 0.5P
CASE 484AE
ISSUE A
24
1
DATE 07 AUG 2018
SCALE 2:1
NOTES:
D
A
B
L3
L3
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN ONE
LOCATION
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
DETAIL A
ALTERNATE
CONSTRUCTION
E
MILLIMETERS
DIM MIN
NOM
0.85
−−−
0.20 REF
−−−
0.25
4.00
2.80
4.00
2.80
MAX
0.90
0.05
A
A1
A3
A4
b
D
D2
E
0.80
−−−
EXPOSED
COPPER
TOP VIEW
A4
A1
0.10
0.20
3.90
2.70
3.90
2.70
−−−
0.30
4.10
2.90
4.10
2.90
DETAIL B
0.10
0.08
C
PLATING
A1
A4
C
ALTERNATE
CONSTRUCTION
A
L
E2
e
C
C
A3
DETAIL B
0.50 BSC
−−−
0.40
SEATING
PLANE
A1
C
K
L
L3
0.20
0.35
0.00
−−−
0.45
0.10
NOTE 4
SIDE VIEW
0.05
A4
D2
GENERIC
DETAIL A
24X
7
MARKING DIAGRAM*
L3
PLATED
13
SURFACES
XXXXXX
XXXXXX
ALYWG
G
SECTION C−C
E2
K
1
24
19
24X b
e
e/2
XXXXXX = Specific Device Code
0.10 C A B
A
L
= Assembly Location
= Wafer Lot
NOTE 3
0.05 C
BOTTOM VIEW
Y
W
G
= Year
= Work Week
= Pb−Free Package
RECOMMENDED
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
4.72
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
24X
0.71
2.90
1
2.90
4.72
24X
0.27
0.50
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON17722G
QFNW24 4x4, 0.5P
PAGE 1 OF 1
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