NCV896530MWATXG [ONSEMI]
双输出降压变压器，低电压，2.1 MHz;
| 型号： | NCV896530MWATXG |
| 厂家： | 
ONSEMI |
| 描述： | 双输出降压变压器，低电压，2.1 MHz 变压器 |
| 文件： | 总10页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Buck Converter - Low
Voltage, Dual, Output
DFN10
CASE 485C
2.1 MHz
MARKING DIAGRAM
NCV896530
The NCV896530 dual step−down dc−dc converter is a monolithic
integrated circuit dedicated to automotive driver information systems
from a downstream voltage rail.
NCV89
6530
ALYWG
G
Both channels are externally adjustable from 0.9 V to 3.3 V and can
source totally up to 1600 mA. Converters are running at 2.1 MHz
switching frequency above the sensitive AM band and operate 180
out of phase to reduce large amounts of current demand on the rail.
Synchronous rectification offers improved system efficiency.
The NCV896530 provides additional features expected in
automotive power systems such as integrated soft−start, hiccup mode
current limit and thermal shutdown protection. The device can also be
synchronized to an external clock signal in the range of 2.1 MHz.
The NCV896530 is available in a space saving, 3 x 3 mm 10−pin
DFN package.
A
L
Y
= Assembly Location
= Wafer Lot
= Year
W = Work Week
G
= Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTIONS
FB2
1
2
3
4
5
FB1
EN1
10
9
Features
EN2
POR
GND
SW2
Synchronous Rectification for Higher Efficiency
2.1 MHz Switching Frequency, 180 Out−of−Phase
Sources up to 1600 mA Total and 1 A Per Channel
Adjustable Output Voltage from 0.9 V to 3.3 V
2.7 V to 5.5 V Input Voltage Range
Thermal Limit and Short Circuit Protection
Auto Synchronizes with an External Clock
Wettable Flanks – DFN
8
SYNC
VIN
7
SW1
6
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 8 of this data sheet.
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This is a Pb−Free Device
Typical Applications
Audio
Infotainment
Vision System
Instrumentation
2.2 mH
VOUT1
4
7
2
3
5
1
8
6
VIN
SW1
FB1
11
10 mF
GND
EN1
POR
OFF ON
2.1MHz
POR
2.2 mH
SYNC
EN2
SW2
FB2
VOUT2
10 mF
OFF ON
9
10
Figure 1. NCV896530 Typical Application
Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
July, 2023 − Rev. 5
NCV896530/D
NCV896530
BLOCK DIAGRAM
EA1
EA2
UVLO
1
2
3
4
5
10
9
FB1
EN1
FB2
EN2
VREF
VREF
Thermal
shutdown
VIN
LOGIC
CONTROL
LOGIC
Voltage
reference
CONTROL
8
SYNC
VIN
POR
GND
SW2
Oscillator
EA1
EA2
VIN
AVIN
Ramp generator
PVIN
AVIN
PVIN
Q1
Q2
Q 3
7
0
180
PWM
PWM
CONTROL
CONTROL
Q4
6
SW1
SYNC
ILIMIT
ILIMIT
Figure 2. Simplified Block Diagram
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2
NCV896530
PIN FUNCTION DESCRIPTION
Pin
1
Pin Name
FB1
Type
Description
Analog Input
Digital Input
Feedback voltage from the output 1. This is the input to the error amplifier.
2
EN1
Enable for converter 1. This pin is active HIGH (equal or lower Analog Input voltage)
and is turned off by logic LOW.
Do not let this pin float.
3
4
SYNC
VIN
Digital Input
Oscillator Synchronization. This pin can be synchronized to an external clock in the
range of 2.1 MHz.
If not used, the pin must to be connected to ground.
Analog / Power
Input
Power supply input for the PFET power stage, analog and digital blocks. The pin must
be decoupled to ground by a 10 mF ceramic capacitor.
5
6
7
SW1
SW2
GND
Analog Output
Analog Output
Analog Ground
Connection from power MOSFETs of output 1 to the Inductor.
Connection from power MOSFETs of output 2 to the Inductor.
This pin is the GROUND reference for the analog section of the IC. The pin must be
connected to the system ground.
8
POR
Digital Output
Power On Reset. This is an open drain output. This output is shutting down when one
of the output voltages are less than 90% (typ) of their nominal values. A pull−up resist-
or around 500 kW should be connected between POR and VIN, VOUT1 or VOUT2
depending on the supplied device.
9
EN2
Digital Input
Enable for converter 2. This pin is active HIGH (equal or lower Analog Input voltage)
and is turned off by logic LOW.
Do not let this pin float.
10
11
FB2
Analog Input
Feedback voltage from the output 2. This is the input to the error amplifier.
Exposed Pad
Power Ground
This pin is the GROUND reference for the NFET power stage of the IC. The pin must
be connected to the system ground and to both input and output capacitors.
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3
Unit
V
Minimum Voltage All Pins
Maximum Voltage All Pins
V
min
max
max
V
V
6.0
V
Maximum Voltage ENx, SYNC, FBx, , SWx, POR
Thermal Resistance Junction−to−Ambient (3x3 DFN) (Note 1)
Storage Temperature Range
VIN+0.3
40
V
R
C/W
C
q
JA
T
stg
−55 to 150
−40 to 150
Junction Operating Temperature
T
J
C
ESD Withstand Voltage
Human Body Model
Machine Model
V
esd
2.0
200
kV
V
Moisture Sensitivity Level
MSL
3
per IPC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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3
NCV896530
ELECTRICAL CHARACTERISTICS (2.7 V < V < 5.5 V, Min and Max values are valid for the temperature range −40C T
IN
J
+150C unless noted otherwise, and are guaranteed by test design or statistical correlation, Typical values are referenced to T = +25C)
A
Rating
INPUT VOLTAGE
Conditions
Symbol
Min
Typ
Max
Unit
Quiescent Current
SYNC = GND, V = 0 V
I
Q
−
2.0
3.0
mA
FB
EN1 = EN2 = 2 V, No Switching
Standby Current
EN1 = EN2 = 0 V
I
−
2.2
−
4.0
2.4
100
10
2.6
150
mA
V
STBMAX
Under Voltage Lockout
Under Voltage Hysteresis
SYNC
V
IN
falling
V
UVLO
V
mV
UVLOH
SYNC Threshold Voltage
V
Logic high
Logic Low
V
1.2
−
−
IHSYNC
V
0.4
50
ILSYNC
ILSYNC
SYNC Pin Bias Current
External Synchronization
SYNC Pulse Duty Ratio
EN1, EN2
V
SYNC
= 5 V
I
2
mA
MHz
%
F
1.8
2.7
SYNC
SYNC
T
50
ENx Threshold Voltage
V
Logic high
Logic Low
V
1.2
2
−
−
IHENx
V
0.4
50
ILENx
ILENx
ENx Pin Bias Current
V
ENx
= 5 V
falling
= 0.4 V
I
mA
POWER ON RESET
Power On Reset Threshold
Power On Reset Hysteresis
Sink Current
V
OUT
V
87%
−
93%
3%
V
V
PORT
PORH
SIPOR
V
V
I
2
mA
POR
OUTPUT PERFORMANCES
Feedback Voltage Threshold
Feedback Voltage Accuracy
FB1, FB2
T = 25C
V
−
0.6
1
−
−
−
V
FB
%
V
V
A
OUT
−40C < T < 125C
−2
400
1.8
−
+2
A
OUT
Soft−Start Time
Time from EN to 90% of output voltage
t
−
1000
2.6
100
ms
MHz
%
START
Switching Frequency
EN1 = EN2 = 1, V = 5 V
F
SW
2.1
−
IN
Duty Cycle
D
POWER SWITCHES
High−Side MOSFET On−resistance
Low−Side MOSFET On−resistance
High−Side MOSFET Leakage Current
Low−Side MOSFET Leakage Current
Minimum On Time
I
I
= 600 mA, V = 5 V, T = 25C
R
−
−
−
−
−
500
450
820
820
5
mW
mW
mA
RDS(on)
IN
A
ONHS
= 600 mA, V = 5 V, T = 25C
R
ONLS
RDS(on)
IN
A
V
IN
= 5 V, V = 0 V, V
= 0 V
I
LEAKHS
LX
ENx
V
LX
= 5 V, V
= 0 V
I
LEAKLS
5
mA
ENx
T
80
ns
ONMIN
PROTECTION
Current Limit
Peak inductor current, V = 5 V,
I
PK
1.4
2.0
A
IN
100% duty cycle
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Hiccup Time
T
150
5
170
60
190
20
C
C
%
SD
T
SDH
% of Soft−Start Time
t
hcp,dly
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCV896530
TYPICAL CHARACTERISTICS CURVES
2.4
2.35
2.3
12
T = 25C,
EN1 = EN2 = 1
T = 25C
J
J
10
8
6
4
2.25
2.2
2
0
2.5
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
IN
, INPUT VOLTAGE (V)
V
SYNC
, SYNC VOLTAGE (V)
Figure 3. Switching Frequency vs. Input
Voltage
Figure 4. Sync Pulldown Current vs. Sync
Voltage
12
10
8
14
12
10
8
T = 25C
J
T = 25C
J
6
6
4
4
2
2
0
2.5
0
0
1
2
3
4
5
6
3
3.5
V , INPUT VOLTAGE (V)
IN
4
4.5
5
5.5
V
, ENABLE VOLTAGE (V)
ENX
Figure 5. Enable Pulldown Current vs. Enable
Voltage
Figure 6. Standby Current vs. Input Voltage
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
600.0
599.5
599.0
598.5
598.0
597.5
597.0
596.5
596.0
−40
10
60
110
−40
10
60
110
T , JUNCTION TEMPERATURE (C)
J
T , JUNCTION TEMPERATURE (C)
J
Figure 7. Current Limit vs. Temperature
Figure 8. Reference Voltage vs. Temperature
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5
NCV896530
TYPICAL CHARACTERISTICS CURVES
12.0
11.5
11.0
10.5
10.0
9.5
14
V
ENX
= 5 V
V
SYNC
= 5 V
12
10
8
6
4
9.0
2
8.5
8.0
−40 −20
0
0
20
40
60
80 100 120 140
−50
0
50
100
150
T , JUNCTION TEMPERATURE (C)
J
T , JUNCTION TEMPERATURE (C)
J
Figure 9. Enable Pulldown Current vs.
Temperature
Figure 10. Sync Pulldown Current vs.
Temperature
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
2.30
2.25
2.20
2.15
2.10
2.05
2.00
V
OUT
= 2.7 V
125C
25C
−40C
V
= 5 V,
IN
EN1 = EN2 = 1
2.5
3
3.5
V
4
4.5
5
5.5
6
−40
10
60
110
, INPUT VOLTAGE (V)
T , JUNCTION TEMPERATURE (C)
J
IN
Figure 12. Peak Current Limit vs. Input Voltage
Figure 11. Switching Frequency vs.
Temperature
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6
NCV896530
DC/DC OPERATION DESCRIPTION
PWM Operating Mode
When an over current event is detected the NCV896530
disables the outputs and attempts to re−enable the outputs
after the hiccup time. The part remains off for the hiccup
time and then goes through the power on reset procedure. If
the excessive load has been removed then the output stage
re−enables and operates normally; however, if the excessive
load is still present the cycle begins again. Internal heat
dissipation is kept to a minimum as current will only flow
during the reset time of the protection circuitry. The hiccup
mode is continuous until the excessive load is removed.
The output voltage of the device is regulated by
modulating the on−time pulse width of the main switch Q1
at a fixed 2.1 MHz frequency (Figure 13).
The switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor
(Q1) and switches the lower side transistor in either ON state
or in current source mode.
At the beginning of each cycle, the main switch Q1 is
turned ON by the rising edge of the internal oscillator clock.
The inductor current ramps up until the sum of the current
sense signal and compensation ramp becomes higher than
the error amplifier’s voltage. Once this has occurred, the
PWM comparator resets the flip−flop, Q1 is turned OFF
while the synchronous switch Q2 is turned in its current
source mode. Q2 replaces the external Schottky diode to
reduce the conduction loss and improve the efficiency. To
avoid overall power loss, a certain amount of dead time is
introduced to ensure Q1 is completely turned OFF before Q2
is being turned ON.
Low Dropout Operation
The NCV896530 offers a low input−to−output voltage
difference. The NCV896530 can operate at 100% duty cycle
on both channels.
In this mode the PMOS (Q1) remains completely ON. The
minimum input voltage to maintain regulation can be
calculated as:
ǒR
Ǔ
) ǒI
INDUCTOR) Ǔ
V
+ V
) R
DS(on)
IN(min)
OUT(max)
OUT
(eq. 1)
V : Output Voltage
OUT
I
: Max Output Current
OUT
R
R
(ON): P−Channel Switch R
DS
DS(on)
V
OUT
: Inductor Resistance (DCR)
INDUCTOR
Power On Reset
The Power On Reset (POR) is pulled low when one of the
converter is out of 90% of the regulation. When both outputs
are in the range of regulation. If only one channel is active,
POR stays low. When the inactive regulator becomes
enabled, POR is kept low until the output reaches its voltage
range. A pull−up resistor is needed to this open drain output.
The resistor may be connected to VIN or to an output voltage
of one regulator if the device supplied can not accept VIN on
the IO. POR is low when NCV896530 is off. Leave the POR
pin unconnected when not used.
I
LX
V
LX
Figure 13. PWM Switching Waveforms
Frequency Synchronization
(V = 3.6 V, V
= 1.2 V, I
= 600 mA, Temp = 25C)
IN
OUT
OUT
The NCV896530 can be synchronized with an external
clock signal by using the SYNC pin (1.8 MHz − 2.4 MHz).
During synchronization, the outputs are in phase.
Soft−Start
The NCV896530 uses soft start to limit the inrush current
when the device is initially powered up or enabled. Soft start
is implemented by gradually increasing the reference
voltage until it reaches the full reference voltage. During
startup, a pulsed current source charges the internal soft start
capacitor to provide gradually increasing reference voltage.
When the voltage across the capacitor ramps up to the
nominal reference voltage, the pulsed current source will be
switched off and the reference voltage will switch to the
regular reference voltage.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. If the junction
temperature exceeds T , the device shuts down. In this
SD
mode all power transistors and control circuits are turned
off. The device restarts in soft start after the temperature
drops below 130C min. This feature is provided to prevent
catastrophic failures from accidental device overheating.
Over Current Hiccup Protection
When the current through the inductor exceeds the current
limit the NCV896530 enters over current hiccup mode.
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NCV896530
Switching Frequency
effect on the control loop. If more than 100 mF is used on an
output small signal analysis should be done to make sure that
sufficient phase margin is maintained. The maximum
allowable due to soft start current limit is given by the
following equation:
When switcher 2 is enabled and switcher 1 is disabled, the
switching frequency is approximately 120 kHz higher than
when switcher 1 is enabled and switcher 2 is either enabled
or disabled.
I
t
start
OUT,startup
Conversion Ratio
(eq. 2)
C
+
max
The minimum conversion ratio is dictated by switching
frequency and the minimum on time. The minimum
achievable output is:
V
OUT
C
: Maximum output capacitance (F)
max
I
: Output current during soft start (A)
OUT,startup
V
+ 0.2 V
IN
OUT
t
: Soft-start time (s)
start
V : Regulated output voltage (V)
out
Maximum Output Capacitance
The maximum output capacitance is determined by the
amount the capacitor can be charged during soft start and the
DEVICE ORDERING INFORMATION
†
Device
Status
Part Marking
Package
Shipping
NCV896530MWATXG
Recommended
NCV89
6530A
DFN10
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NCV896530MWTXG
Not for new designs
NCV89
6530
DFN10
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE F
SCALE 2:1
DATE 16 DEC 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
(Note: Microdot may be in either location) not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03161D
DFN10, 3X3 MM, 0.5 MM PITCH
PAGE 1 OF 1
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