NFAM2065L4BT [ONSEMI]
Intelligent Power Module, SPM31, 650 V, 20 A (NTC option);
| 型号： | NFAM2065L4BT |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module, SPM31, 650 V, 20 A (NTC option) 电动机控制 |
| 文件： | 总10页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent Power Module (IPM)
650 V, 20 A
NFAM2065L4BT
General Description
The NFAM2065L4BT is a fully−integrated inverter power module
consisting of an independent High side gate driver, LVIC, six IGBT’s
and a temperature sensor (VTS or Thermistor(T)), suitable for driving
permanent magnet synchronous (PMSM) motors, brushless DC
(BLDC) motors and AC asynchronous motors. The IGBT’s are
configured in a three−phase bridge with separate emitter connections
for the lower legs for maximum flexibility in the choice of control
algorithm.
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The power stage has under−voltage lockout protection (UVP).
Internal boost diodes are provided for high side gate boost drive.
Features
• Three−phase 650 V, 20 A IGBT Module with Independent Drivers
• Active Logic Interface
• Built−in Under−voltage Protection (UVP)
DIP39 54.5 x 31.0
CASE MODGC
• Integrated Bootstrap Diodes and Resistors
• Separate Low−side IGBT Emitter Connections for Individual Current
Sensing of Each Phase
MARKING DIAGRAM
• Temperature Sensor (VTS or Thermistor (T))
• UL1557 Certified (File No.E339285)
• This is a Pb−Free Device
NFAM2065L4BT
ZZZATYWW
Typical Application
• Industrial Drives
• Industrial Pumps
• Industrial Fans
Device marking is on package top side
NFAM2065L4BT = Specific Device Code
ZZZ
A
T
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
• Industrial Automation
RTH VTH
P
U
V
W
VS(U)
VB(U)
Y
High Side
HVIC1
HS1
WW
= Work Week
VDD(UH)
HIN(U)
VS(V)
VB(V)
High Side
HVIC2
HS2
HS1
LS1
HS2
LS2
HS3
LS3
VDD(VH)
HIN(V)
ORDERING INFORMATION
VS(W)
VB(W)
High Side
HVIC3
HS
3
Shipping
VDD(WH)
HIN(W)
(Qty / Packing)
Package
Device
VTS
LIN(U)
90 / BOX
LS1
LS2
LS3
NFAM2065L4BT DIP39, 31.0x54.5
(Pb−Free)
LIN(V)
LIN(W)
VFO
Low Side
LVIC
with
CFOD
CIN
Protection
VSS
VDD(L)
NV
NU
NW
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
April, 2020 − Rev. 1
NFAM2065L4BT/D
NFAM2065L4BT
APPLICATION SCHEMATIC
5 V line
RTH (39)
VTH (38)
VB(U) (3)
VS(U) (1)
P (37)
CS
+
C1
VB
HOUT
HIN (U) (6)
HIN
VDD(UH) (4)
HVIC 1
VDD
VSS
U (36)
VS
VB(V) (9)
VS(V) (7)
VB
HOUT
HIN (V) (12)
HIN
VDD(VH) (10)
HVIC 2
VDD
VSS
V (35)
VS
Motor
VB(W) (15)
VS(W) (13)
MCU
VB
HOUT
HIN (W) (18)
HIN
VDD(WH) (16)
HVIC 3
VDD
VSS
W (34)
VS
VTS (20)
VTS
OUT(U)
LIN(U) (21)
LIN(V) (22)
LIN(W) (23)
LIN(U)
LIN(V)
LIN(W)
NU (33)
5 V line
LVIC
VFO (24)
OUT(V)
OUT(W)
VFO
CFOD (25)
CFOD
CIN
NV (32)
NW (31)
CIN (26)
15 V line
VDD(L) (28)
VDD
VSS (27)
VSS
Signal for short circuit trip
Phase current
Figure 2. Application Schematic − Adjustable Option
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2
NFAM2065L4BT
BLOCK DIAGRAM
RTH (39
* NTC Thermistor
VTH (38)
P (37)
VS(U) (1)
VB (U) (3)
VB
VDD (UH ) (4)
HIN (U) (6)
HOUT
VDD
HVIC 1
HIN
V S
VSS
U (36)
V (35)
W (34)
VS(V) (7)
VB(V)(9)
VB
VDD (VH) (10)
HIN (V) (12)
HOUT
VDD
HIN
HVIC 2
VS
VSS
VS(W) (13)
VB(W) (15)
VB
VDD (WH ) (16)
HIN (W) (18)
HOUT
VDD
HIN
HVIC 3
VS
VSS
OUT (U)
VTS
VTS (20)
LIN (U) (21)
LIN (V) (22)
LIN (W) (23)
VFO (24)
LIN(U)
LIN(V)
NU (33)
NV (32)
NW (31)
LIN(W)
VFO
OUT (V)
LVIC
CFOD
CIN
CFOD (25)
CIN (26)
VSS
VSS (27)
OUT (W)
VDD (L) (28)
VDD
Figure 3. Equivalent Block Diagram
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3
NFAM2065L4BT
PIN FUNCTION DESCRIPTION
Pin
1
Name
Description
VS(U)
−
High−Side Bias Voltage GND for U Phase IGBT Driving
Dummy
(2)
3
VB(U)
VDD(UH)
−
High−Side Bias Voltage for U Phase IGBT Driving
High−Side Bias Voltage for U Phase IC
Dummy
4
(5)
6
HIN(U)
VS(V)
−
Signal Input for High−Side U Phase
High−Side Bias Voltage GND for V Phase IGBT Driving
Dummy
7
(8)
9
VB(V)
VDD(VH)
−
High−Side Bias Voltage for V Phase IGBT Driving
High−Side Bias Voltage for V Phase IC
Dummy
10
(11)
12
13
(14)
15
16
(17)
18
(19)
20
21
22
23
24
25
26
27
28
(29)
(30)
31
32
33
34
35
36
37
38
39
HIN(V)
VS(W)
−
Signal Input for High−Side V Phase
High−Side Bias Voltage GND for W Phase IGBT Driving
Dummy
VB(W)
VDD(WH)
−
High−Side Bias Voltage for W Phase IGBT Driving
High−Side Bias Voltage for W Phase IC
Dummy
HIN(W)
−
Signal Input for High−Side W Phase
Dummy
VTS
LIN(U)
LIN(V)
LIN(W)
VFO
CFOD
CIN
Voltage Output for LVIC Temperature Sensing Unit
Signal Input for Low−Side U Phase
Signal Input for Low−Side V Phase
Signal Input for Low−Side W Phase
Fault Output
Capacitor for Fault Output Duration Selection
Input for Current Protection
VSS
VDD(L)
−
Low−Side Common Supply Ground
Low−Side Bias Voltage for IC and IGBTs Driving
Dummy
−
Dummy
NW
Negative DC−Link Input for U Phase
Negative DC−Link Input for V Phase
Negative DC−Link Input for W Phase
Output for U Phase
NV
NU
W
V
Output for V Phase
U
Output for W Phase
P
Positive DC−Link Input
VTH
RTH
Thermistor Bias Voltage (T) / Not connection
Series Resister for Thermistor (Temperature Detection) *optional for T
1. Pins of () are the dummy for internal connection. These pins should be no connection.
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4
NFAM2065L4BT
ABSOLUTE MAXIMUM RATINGS (T = 25°C) (Note 2)
C
Rating
Symbol
Conditions
Value
450
Unit
V
Supply Voltage
VPN
P − NU, NV, NW
Supply Voltage (Surge)
VPN(Surge)
VPN(PROT)
P − NU, NV, NW, (Note 3)
550
V
Self Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
VDD = VBS = 13.5 V ~ 16.5 V, Tj = 150°C,
Vces < 650 V, Non−Repetitive, < 2 us
400
V
Collector−Emitter Voltage
Vces
VRRM
Ic
650
650
V
V
A
A
V
V
V
Maximum Repetitive Revers Voltage
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
Control Supply Voltage
20
Icp
Under 1 ms Pulse Width
40
VDD
VBS
VIN
VDD(UH,VH,WH), VDD(L) − VSS
VB(U) − VS(U), VB(V) − VS(V), VB(W) − VS(W)
−0.3 to 20
−0.3 to 20
−0.3 to VDD
High−Side Control Bias Voltage
Input Signal Voltage
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) − VSS
Fault Output Supply Voltage
Fault Output Current
VFO
IFO
VCIN
Pc
VFO − VSS
−0.3 to VDD
2
V
mA
V
Sink Current at VFO pin
CIN − VSS
Current Sensing Input Voltage
Corrector Dissipation
−0.3 to VDD
96
Per One Chip
W
Operating Junction Temperature
Storage Temperature
Tj
−40 to +150
−40 to +125
−40 to +125
2500
°C
Tstg
Tc
°C
Module Case Operation Temperature
Isolation Voltage
°C
Viso
60 Hz, Sinusoidal, AC 1 minute,
V rms
Connection Pins to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
THERMAL CHARACTERISTICS
Rating
Symbol
Rth(j−c)Q
Rth(j−c)F
Conditions
Min
−
Typ
−
Max
1.3
Unit
°C/W
°C/W
Junction to Case Thermal
Resistance
Inverter IGBT Part (per 1/6 Module)
Inverter FWDi Part (per 1/6 Module)
−
−
2.4
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
RECOMMENDED OPERATING RANGES (Note 5)
Rating
Supply Voltage
Symbol
VPN
Conditions
P − NU, NV, NW
Min
−
Typ
300
15
Max
400
Unit
V
Gate Driver Supply Voltages
VDD
VDD(UH,VH,WH), VDD(L) − VSS
13.5
13.0
16.5
18.5
V
VBS
VB(U) − VS(U), VB(V) − VS(V),
VB(W) − VS(W)
15
V
Supply Voltage Variation
dVDD / dt
dVBS / dt
−1
−
1
V/ms
PWM Frequency
Dead Time
fPWM
DT
1
1.5
−
20
−
kHz
ms
Turn−off to Turn−on (external)
−
−
Allowable r.m.s. Current
Io
VPN = 300 V,
VDD = VD = 15 V,
P.F. = 0.8,
fPWM =
5 kHz
20.5
A rms
fPWM =
15 kHz
−
−
15.4
Tc ≤ 125°C, Tj ≤ 150°C,
(Note 5)
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5
NFAM2065L4BT
RECOMMENDED OPERATING RANGES (Note 5) (continued)
Rating
Symbol
Conditions
Min
Typ
Max
Unit
Allowable Input Pulse Width
PWIN (on)
200 V ≤ VPN ≤ 400 V,
13.5 V ≤ VDD ≤ 16.5 V,
13.0 V ≤ VBS ≤ 18.5 V,
−20°C ≤ Tc ≤ 100°C
1.0
−
−
ms
PWIN (off)
1.5
0.6
−
−
Package Mounting Torque
M3 Type Screw
0.7
0.9
Nm
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Allowable r.m.s Current depends on the actual conditions.
6. Flatness tolerance of the heatsink should be within −50 mm to +100 mm.
ELECTRICAL CHARACTERISTICS (Tc = 25°C, VDD = 15 V, VBS = 15 V, unless otherwise noted) (Note 7)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
INVERTER SECTION
Collector−Emitter Leakage
Current
Vce = Vces, Tj = 25°C
Ices
−
−
−
−
−
1
mA
mA
V
Vce = Vces, Tj = 150°C
10
Collector−Emitter Saturation
Voltage
VDD = VBS = 15 V, IN = 5 V
Ic = 20 A, Tj = 25°C
VCE(sat)
1.60
2.30
VDD = VBS = 15 V, IN = 5 V
−
1.80
−
V
Ic = 20 A, Tj = 150°C
FWDi Forward Voltage
IN = 0 V, If = 20 A, Tj = 25°C
IN = 0 V, If = 20 A, Tj = 150°C
VF
−
−
1.90
1.90
1.30
0.20
1.40
0.20
0.15
1.40
0.20
1.50
0.20
0.15
2.30
−
V
V
High Side
Switching Times
Switching Times
VPN = 300 V, VDD(H) = VDD(L) = 15 V
Ic = 20 A, Tj = 25°C, IN = 0 ⇔ 5 V
Inductive Load
ton
tc (on)
toff
0.80
−
1.90
0.60
2.00
0.70
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
−
tc (off)
trr
−
−
Low Side
VPN = 300 V, VDD(H) = VDD(L) = 15 V
Ic = 20 A, Tj = 25°C, IN = 0 ⇔ 5 V
Inductive Load
ton
0.80
−
2.00
0.60
2.10
0.70
−
tc (on)
toff
−
tc (off)
trr
−
−
DRIVER SECTION
Quiescent VDD Supply Current
VDD(UH,VH,WH) = 15 V,
HIN(U,V,W) = 0 V
VDD(UH) − VSS
VDD(VH) − VSS
VDD(WH) − VSS
IQDDH
−
−
0.30
mA
VDD(L) = 15 V,
LIN(U, V, W) = 0 V
VDD(L) − VSS
IQDDL
IPDDH
−
−
−
−
3.50
0.40
mA
mA
Operating VDD Supply Current
VDD(UH, VH, WH) = 15 V,
fPWM = 20 kHz, Duty = 50%,
VDD(UH) − VSS
VDD(VH) − VSS
Applied to one PWM Signal Input VDD(WH) − VSS
for High−Side
VDD(L) = 15 V,
VDD(L) − VSS
IPDDL
IQBS
−
−
−
−
6.00
0.30
mA
mA
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal Input
for Low−Side
Quiescent VBS Supply Current
VBS = 15 V
HIN(U, V, W) = 0 V
VB(U) − VS(U)
VB(V) − VS(V)
VB(W) − VS(W)
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NFAM2065L4BT
ELECTRICAL CHARACTERISTICS (Tc = 25°C, VDD = 15 V, VBS = 15 V, unless otherwise noted) (Note 7) (continued)
Parameter
DRIVER SECTION
Test Conditions
Symbol
Min
Typ
Max
Unit
Operating VBS Supply Current
VDD = VBS = 15 V,
fPWM = 20 kHz, Duty = 50%,
VB(U) − VS(U)
VB(V) − VS(V)
IPBS
−
−
5.00
mA
Applied to one PWM Signal Input VB(W) − VS(W)
for High−Side
ON Threshold Voltage
OFF Threshold Voltage
Short Circuit Trip Level
HIN(U, V, W) − VSS, LIN(U, V, W) − VSS
VIN(ON)
VIN(OF)
VCIN(ref)
UVDDD
UVDDR
UVBSD
UVBSR
VTS
−
−
2.6
−
V
V
V
V
V
V
V
V
0.8
−
0.48
−
VDD = 15 V, CIN−VSS
Detection Level
0.46
10.3
10.8
10.0
10.5
0.905
0.50
12.5
13.0
12.0
12.5
1.155
Supply Circuit Under−Voltage
Protection
Reset Level
−
Detection Level
−
Reset Level
−
Voltage Output for LVIC
Temperature Sensing Unit
VTS−VSS = 10 nF, Temp. = 25°C
1.030
Fault Output Voltage
VDD = 0 V, CIN = 0 V,
VFO Circuit: 10 kW to 5 V Pull−up
VFOH
VFOL
tFOD
4.9
−
−
−
−
0.95
−
V
V
VDD = 0 V, CIN = 1 V,
VFO Circuit: 10 kW to 5 V Pull−up
Fault−Output Pulse Width
CFOD = 22 nF
1.6
2.4
ms
BOOTSTRAP SECTION
Bootstrap Diode Forward Voltage If = 0.1 A
Built−in Limiting Resistance
VF
3.4
30
4.6
38
5.8
46
V
RBOOT
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
8. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
6
tFOD = 0.1 x 10 x CFOD (s).
9. Values based on design and/or characterization.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
LVIC Temperature (°C)
Figure 4. Temperature of LVIC versus VOT Characteristics
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7
NFAM2065L4BT
THERMISTOR CHARACTERISTIC
Parameter
Resistance
Symbol
Condition
Min
46.530
1.344
4009.5
−40
Typ
47
Max
47.47
1.471
4090.5
+125
Unit
kW
kW
K
R
Tc = 25°C
25
Resistance
R
Tc = 100°C
1.406
4050
−
125
B−Constant (25−50°C)
Temperature Range
−
B
−
−
°C
10000
1000
min
typ
max
100
10
1
−40 −30 −20 −10
0
10 20 30 40 50 60 70
Case Temperature
80 90 100 110 120 130
Figure 5. Thermistor Resistance versus Case Temperature
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
MINI DIP39, 31.0x54.5
CASE MODGC
ISSUE A
DATE 19 MAR 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXXX
ZZZATYWW
XXXXX = Specific Device Code
ZZZ
AT
Y
= Assembly Lot Code
= Assembly & Test Location
= Year
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G” or
microdot “G”, may or may not be present. Some products
may not follow the Generic Marking.
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON91300G
MINI DIP39, 31.0x54.5
PAGE 1 OF 1
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