NLSV1T240_12 [ONSEMI]
1-Bit Dual-Supply Inverting Level Translator; 1位双电源反相电平转换器
| 型号： | NLSV1T240_12 |
| 厂家： | 
ONSEMI |
| 描述： | 1-Bit Dual-Supply Inverting Level Translator |
| 文件： | 总6页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSV1T240
1-Bit Dual-Supply Inverting
Level Translator
The NLSV1T240 is a 1−bit configurable dual−supply voltage level
translator. The input A and output B ports are designed to track two
n
n
different power supply rails, V
supply rails are configurable from 0.9 V to 4.5 V allowing universal
low−voltage translation from the input A to the output B port.
and V
respectively. Both
CCA
CCB
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MARKING
n
n
DIAGRAM
Features
• Wide V
and V
Operating Range: 0.9 V to 4.5 V
CCA
CCB
3M
G
1
• High−Speed w/ Balanced Propagation Delay
UDFN6
MU SUFFIX
CASE 517AA
• Inputs and Outputs have OVT Protection to 4.5 V
• Non−preferential V
and V
Sequencing
CCA
CCB
• Outputs at 3−State until Active V is Reached
CC
3
= Specific Device Code
= Date Code
• Power−Off Protection
M
G
= Pb−Free Package
• Outputs Switch to 3−State with V
at GND
CCB
• Ultra−Small Packaging: 1.2 mm x 1.0 mm UDFN6
• This is a Pb−Free Device
PIN ASSIGNMENT
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
1
2
3
6
5
4
V
B
V
CCB
CCA
A
Important Information
• ESD Protection for All Pins:
Human Body Model (HBM) > 2000 V
GND
OE
(Top View)
V
CCA
V
CCB
ORDERING INFORMATION
B
A
†
Device
Package
Shipping
NLSV1T240MUTBG UDFN6 3000/Tape & Reel
OE
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
February, 2012 − Rev. 4
NLSV1T240/D
NLSV1T240
PIN ASSIGNMENT
PIN
TRUTH TABLE
FUNCTION
Inputs
Outputs
V
V
Input Port DC Power Supply
Output Port DC Power Supply
Ground
CCA
CCB
OE
L
A
L
B
H
L
GND
A
L
H
X
Input Port
H
3−State
B
Output Port
OE
Output Enable
MAXIMUM RATINGS
Symbol
Rating
Value
Condition
Unit
V
V
CCA
, V
CCB
DC Supply Voltage
−0.5 to +5.5
−0.5 to +5.5
−0.5 to +5.5
−0.5 to +5.5
−0.5 to +5.5
−0.5 to +5.5
−20
V
DC Input Voltage
Control Input
A
OE
B
V
I
V
C
O
V
V
DC Output Voltage
(Power Down)
(Active Mode)
V
= V
= 0
V
CCA
CCB
B
V
(Tri−State Mode)
B
V
I
DC Input Diode Current
DC Output Diode Current
V < GND
I
mA
mA
mA
mA
mA
°C
IK
I
−50
V < GND
O
OK
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
O
I
, I
100
CCA CCB
I
100
GND
T
−65 to +150
STG
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
, V
Parameter
Min
0.9
Max
4.5
4.5
4.5
4.5
Unit
V
V
CCA
Positive DC Supply Voltage
Bus Input Voltage
Control Input
CCB
V
I
GND
GND
GND
GND
GND
−40
0
V
V
C
OE
B
V
V
IO
Bus Output Voltage
(Power Down Mode)
(Active Mode)
V
B
V
CCB
V
(Tri−State Mode)
B
4.5
V
T
A
Operating Temperature Range
Input Transition Rise or Rate
+85
10
°C
nS
Dt / DV
V , from 30% to 70% of V ; V = 3.3 V 0.3 V
I
CC
CC
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2
NLSV1T240
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Min
Max
Symbol
Parameter
Test Conditions
V
CCA
(V)
V
CCB
(V)
Unit
V
Input HIGH Voltage
(A, OE)
0.9 – 4.5
V
3.6 – 4.5
2.7 – 3.6
2.3 – 2.7
1.4 − 2.3
0.9 – 1.4
3.6 – 4.5
2.7 – 3.6
2.3 – 2.7
1.4 − 2.3
0.9 – 1.4
0.9 – 4.5
0.9
2.2
−
IH
2.0
1.6
−
−
−
0.65 * V
CCA
CCA
0.9 * V
−
V
Input LOW Voltage
(A, OE)
0.9 – 4.5
V
V
−
−
−
−
−
0.8
IL
0.8
0.7
0.35 * V
CCA
CCA
0.1 * V
V
OH
Output HIGH Voltage
I
I
I
I
= −100 mA; V = V
0.9 – 4.5
0.9
V – 0.2
CCB
−
−
OH
OH
OH
OH
I
IL
= −0.5 mA; V = V
0.75 * V
1.05
1.25
2.0
1.8
2.2
1.7
2.4
2.2
−
I
IL
CCB
= −2 mA; V = V
1.4
1.4
−
I
IL
IL
= −6 mA; V = V
1.65
1.65
2.3
−
I
2.3
−
I
I
= −12 mA; V = V
2.3
2.3
−
OH
OH
I
IL
2.7
2.7
−
= −18 mA; V = V
2.3
2.3
−
I
IL
IL
3.0
3.0
−
I
I
I
I
I
I
= −24 mA; V = V
3.0
3.0
−
OH
OL
OL
OL
OL
OL
I
V
OL
Output LOW Voltage
V
= 100 mA; V = V
0.9 – 4.5
1.1
0.9 – 4.5
1.1
0.2
0.3
I
IH
= 0.5 mA; V = V
−
I
IH
= 2 mA; V = V
1.4
1.4
−
0.35
0.3
0.4
0.4
0.6
0.4
0.55
1.0
I
IH
IH
= 6 mA; V = V
1.65
1.65
2.3
−
I
= 12 mA; V = V
2.3
−
I
IH
2.7
2.7
−
I
OL
= 18 mA; V = V
2.3
2.3
−
I
IH
3.0
3.0
−
I
OL
= 24 mA; V = V
3.0
3.0
−
I
IH
I
Input Leakage Current
V = V
CCA
or GND
0.9 – 4.5
0.9 – 4.5
−1.0
mA
mA
I
I
I
Power−Off Leakage Current
OE = 0 V
0
0.9 – 4.5
0
−1.0
−1.0
1.0
1.0
OFF
CCA
CCB
0.9 – 4.5
I
I
Quiescent Supply Current
Quiescent Supply Current
Quiescent Supply Current
V = V
or GND;
CCA
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 − 4.5
0.9 − 4.5
0.9 – 4.5
−
−
−
−
1.0
1.0
2.0
mA
mA
mA
mA
I
CCA
CCA
CCA
I
O
= 0, V
= V
CCB
V = V
or GND;
= V
CCB
I
I
O
= 0, V
CCA
I
+ I
V = V
or GND;
= V
CCB
CCA
CCB
I
I
O
= 0, V
CCA
DI
Increase in I per Input Voltage, V = V
– 0.6 V;
or GND
4.5
3.6
4.5
3.6
10
5.0
CCA
CCB
OZ
CC
I
CCA
Other Inputs at V
or GND
CCA
V = V
I
CCA
DI
Increase in I per Input Voltage, V = V
– 0.6 V;
or GND
4.5
3.6
4.5
3.6
−
10
5.0
mA
mA
CC
I
CCA
Other Inputs at V
or GND
CCA
V = V
I
CCA
I
I/O Tri−State Output Leakage
Current
T = 25°C, OE = 0 V
0.9 – 4.5
0.9 – 4.5
−1.0
1.0
A
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3
NLSV1T240
TOTAL STATIC POWER CONSUMPTION (ICCA + ICCB
)
−405C to +855C
V
CCB
(V)
4.5
3.3
2.8
1.8
0.9
V
CCA
(V)
Min
Max
2
Min
Max
2
Min
Max
Min
Max
2
Min
Max
< 1.5
< 1.5
< 0.5
< 0.5
< 0.5
Unit
mA
4.5
2
3.3
2.8
1.8
0.9
2
2
2
2
mA
< 2
< 1
< 0.5
< 1
< 1
< 0.5
< 1
< 0.5
< 0.5
< 0.5
mA
< 0.5
< 0.5
mA
mA
NOTE: Connect ground before applying supply voltage V
or V
. This device is designed with the feature that the power−up
CCA
CCB
sequence of V
and V
will not damage the IC.
CCA
CCB
AC ELECTRICAL CHARACTERISTICS
−405C to +855C
V
CCB
(V)
4.5
3.3
2.8
1.8
1.2
Min
Max
Min
Max
1.8
Min
Max
2.0
Min
Max
2.1
Min
Max
2.3
Symbol
Parameter
V
CCA
(V)
Unit
t
t
,
Propagation
Delay,
4.5
1.6
1.7
nS
PLH
PHL
3.3
2.8
1.8
1.2
4.5
3.3
2.5
1.8
1.2
4.5
3.3
2.5
1.8
1.2
4.5
3.3
2.5
1.8
1.2
1.9
2.1
2.3
2.6
(Note 1)
A to B
1.9
2.1
2.3
2.5
2.8
2.1
2.4
2.5
2.7
3.0
2.4
2.7
2.8
3.0
3.3
t
t
,
Output
Enable,
2.6
3.8
4.0
4.1
4.3
nS
nS
nS
PZH
PZL
3.7
3.9
4.1
4.3
4.6
(Note 1)
OE to B
3.9
4.1
4.3
4.5
4.8
4.1
4.4
4.5
4.7
5.0
4.4
4.7
4.8
5.0
5.3
t
t
,
Output
Disable,
2.6
3.8
4.0
4.1
4.3
PHZ
PLZ
3.7
3.9
4.1
4.3
4.6
(Note 1)
OE to B
3.9
4.1
4.3
4.5
4.8
4.1
4.4
4.5
4.7
5.0
4.4
4.7
4.8
5.0
5.3
t
t
,
Output to
Output
Skew,
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
OSHL
OSLH
(Note 1)
Time
1. Propagation delays defined per Figure 2.
CAPACITANCE
Symbol
Parameter
Test Conditions
Typ (Note 2)
Unit
pF
C
Control Pin Input Capacitance
I/O Pin Input Capacitance
Power Dissipation Capacitance
V
CCA
V
CCA
V
CCA
= V
= 3.3 V, V = 0 V or V
3.5
5.0
5.0
IN
I/O
PD
CCB
CCB
CCB
I
CCA/B
CCA/B
C
C
= V
= V
= 3.3 V, V = 0 V or V
pF
I
= 3.3 V, V = 0 V or V
, f = 10 MHz
pF
I
CCA
2. Typical values are at T = +25°C.
A
3. C is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
PD
I
^ C x V x f where I = I
+ I
CCB
.
CC(operating)
PD
CC
IN
CC
CCA
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4
NLSV1T240
V
CC
V
CCO
x 2
OPEN
GND
R
L
Pulse
Generator
DUT
C
R
L
L
Figure 2. AC (Propagation Delay) Test Circuit
Test
, t
Switch
t
OPEN
PLH PHL
t
, t
V
CCO
x 2
PLZ PZL
t
, t
GND
PHZ PZH
C = 15 pF or equivalent (includes probe and jig capacitance)
L
R = 2 kW or equivalent
L
Z
OUT
of pulse generator = 50 W
V
IH
Input (A)
Vm
Vm
0 V
t
t
PHL
PLH
V
OH
Output (B)
Vm
Vm
V
OL
Waveform 1 − Propagation Delays
t
R
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F
W
V
IH
OE
Vm
Vm
n
0 V
t
t
PHZ
PZH
V
V
OH
Y
Output (B)
Output (B)
Vm
Vm
≈ 0 V
≈ V
t
t
PLZ
PZL
CC
V
V
X
OL
Waveform 2 − Output Enable and Disable Times
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns
t
R
F
W
Figure 3. AC (Propagation Delay) Test Circuit Waveforms
V
CC
3.0 V – 4.5 V
2.3 V − 2.7 V
1.65 V − 1.95 V
1.4 V − 1.6 V
0.9 V − 1.3 V
Symbol
V
V
V
CCA
V
CCB
/2
/2
V
CCA
V
CCB
/2
/2
V
CCA
V
CCB
/2
/2
V
CCA
V
CCB
/2
/2
V
CCA
V
CCB
/2
/2
mA
mB
V
V
x 0.1
x 0.9
V
x 0.1
x 0.9
V
x 0.1
x 0.9
V
x 0.1
x 0.9
V
x 0.1
x 0.9
X
OL
OL
OL
OL
OL
V
Y
V
OH
V
OH
V
OH
V
OH
V
OH
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5
NLSV1T240
PACKAGE DIMENSIONS
UDFN6 1.2 x 1.0, 0.4P
CASE 517AA
ISSUE C
EDGE OF PACKAGE
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
L1
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
E
DETAIL A
REFERENCE
Bottom View
MILLIMETERS
2X
DIM MIN
0.45
A1 0.00
MAX
0.55
0.05
(Optional)
A
0.10
C
MOLD CMPD
EXPOSED Cu
TOP VIEW
A3
b
D
E
0.127 REF
2X
0.15
0.25
0.10
C
C
1.20 BSC
1.00 BSC
0.40 BSC
A3
e
L
0.30
0.40
0.15
0.50
(A3)
L1 0.00
L2 0.40
0.10
0.08
A1
DETAIL B
Side View
(Optional)
A
MOUNTING FOOTPRINT*
SEATING
PLANE
10X
C
6X
0.42
SIDE VIEW
6X
0.22
C
A1
5X L
3
1
L2
6X b
0.40
PITCH
1.07
6
4
0.10
0.05
C
A B
e
DIMENSIONS: MILLIMETERS
C
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NLSV1T240/D
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