概述
规格参数
数据手册NLSX4302EBMUTCG 概述
两位，双电源电平转换器 其他接口集成电路
NLSX4302EBMUTCG 规格参数
| 是否无铅： | 不含铅 | 生命周期： | Active |
| 包装说明： | VQCCN, LCC8,.05X.06,16 | 针数： | 8 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 8 weeks | 风险等级： | 1.5 |
| 接口集成电路类型： | INTERFACE CIRCUIT | JESD-30 代码： | R-XQCC-N8 |
| 长度： | 1.4 mm | 湿度敏感等级： | 1 |
| 功能数量： | 2 | 端子数量： | 8 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | UNSPECIFIED | 封装代码： | VQCCN |
| 封装等效代码： | LCC8,.05X.06,16 | 封装形状： | RECTANGULAR |
| 封装形式： | CHIP CARRIER, VERY THIN PROFILE | 电源： | 1.8/5 V |
| 认证状态： | Not Qualified | 座面最大高度： | 0.55 mm |
| 子类别： | Other Interface ICs | 最大供电电压： | 5.5 V |
| 最小供电电压： | 1.5 V | 标称供电电压： | 3.3 V |
| 表面贴装： | YES | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Silver/Gold/Palladium (Ni/Ag/Au/Pd) | 端子形式： | NO LEAD |
| 端子节距： | 0.4 mm | 端子位置： | QUAD |
| 宽度： | 1.2 mm | Base Number Matches： | 1 |
NLSX4302EBMUTCG 数据手册
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PDF下载2-Bit 20 Mb/s Dual-Supply
Level Translator
NLSX4302E
The NLSX4302E is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The V I/O and V I/O ports are designed to track two different
CC
L
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power supply rails, V and V respectively. Both the V and V
CC
L
CC
L
supply rails are configurable from 1.5 V to 5.5 V. This allows voltage
logic signals on the V side to be translated into lower, higher or
MARKING
DIAGRAMS
L
equal value voltage logic signals on the V side, and vice−versa.
CC
UQFN8
MU SUFFIX
CASE 523AS
The NLSX4302E translator uses external pull−up resistors on the
I/O lines. The external pull−up resistors are used to pull up the I/O
EM
1
lines to either V or V . The NLSX4302E is an excellent match for
L
CC
2
open−drain applications such as the I C communication bus.
E
M
= Specific Device Code
= Date Code
Features
• V can be Less than, Greater than or Equal to V
L
CC
• Wide V Operating Range: 1.5 V to 5.5 V
CC
LOGIC DIAGRAM
Wide V Operating Range: 1.5 V to 5.5 V
L
V
L
V
CC
GND
• High−Speed with 20 Mb/s Guaranteed Date Rate
• Low Bit−to−Bit Skew
EN
• Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V
• Non−preferential Powerup Sequencing
I/O V 1
I/O V
1
2
L
CC
• Power−Off Protection
• Small Space Saving Package: 1.4 mm x 1.2 mm UQFN8 Package
• These Devices are Pb−Free and are RoHS Compliant
I/O V 2
I/O V
L
CC
Typical Applications
2
• I C, SMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
ORDERING INFORMATION
†
Device
Package
Shipping
Important Information
NLSX4302EBMUTCG UQFN8
3000/Tape &
Reel
• ESD Protection for All Pins
− Human Body Model (HBM) > 6000 V
− Machine Model (MM) > 400 V
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
August, 2021 − Rev. 1
NLSX4302E/D
NLSX4302E
Figure 1. Block Diagram (1 I/O Line)
V
L
1
2
3
4
I/O V 1
8
7
6
V
CC
L
I/O V 2
I/O V
I/O V
1
2
L
CC
GND
CC
5
EN
UQFN8
(Top Through View)
Figure 2. Pin−out Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
Supply Voltage
EN
L
Operating Mode
Hi−Z
V
CC
L
V
CC
V
V Supply Voltage
L
H
I/O Buses Connected
GND
EN
Ground
Output Enable, Referenced to V
L
I/O V
n
I/O Port, Referenced to V
I/O Port, Referenced to V
CC
CC
L
I/O V n
L
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2
NLSX4302E
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
High−side DC Supply Voltage
High−side DC Supply Voltage
−Referenced DC Input/Output Voltage
−0.3 to +7.0
−0.3 to +7.0
CC
L
V
V
I/O V
I/O V
V
CC
−0.3 to (V + 0.3)
V
CC
CC
V −Referenced DC Input/Output Voltage
L
−0.3 to (V + 0.3)
V
L
L
V
Enable Control Pin DC Input Voltage
−0.3 to +7.0
40
V
EN
I
Short−Circuit Duration (I/O V and I/O V to GND)
Continuous
mA
°C
I/O_SC
L
CC
T
STG
Storage Temperature
−65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
High−side Positive DC Supply Voltage
Min
1.5
Max
5.5
5.5
5.5
Unit
V
V
CC
V
L
High−side Positive DC Supply Voltage
1.5
V
V
EN
Enable Control Pin Voltage
GND
GND
GND
V
V
I/O Pin Voltage (Side referred to V
)
CC
V
CC
V
IO_VCC
V
IO_VL
I/O Pin Voltage (Side referred to V )
V
L
V
L
Dt/DV
Input Transition Rise and Fall Rate
I/O V − or I/O V − Ports, Push−Pull Driving
10
10
ns/V
L
L
Control Input
T
A
Operating Temperature Range
−40
+85
°C
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3
NLSX4302E
DC ELECTRICAL CHARACTERISTICS (V = 1.5 V to 5.5 V and V = 1.5 V to 5.5 V, unless otherwise specified) (Note 1)
L
CC
−405C to +855C
Symbol
Parameter
Test Conditions (Note 2)
V (V)
L
V
CC
(V)
Min
Typ
Max
Unit
V
IH_VL
I/O High Level I/O_VL
Data Inputs I/O_VL
1.65–5.50 1.65–5.50 V – 0.4
V
n
L
Control Input EN
1.65–5.50 1.65–5.50 V x 0.7
L
V
I/O High Level I/O_VCC Data Inputs I/O_VCC
1.65–5.50 1.65–5.50
1.65–5.50 1.65–5.50
1.65–5.50 1.65–5.50
1.65–5.50 1.65–5.50
1.65–5.50 1.65–5.50
V – 0.4
CC
V
V
IH_VCC
n
V
I/O Low Level I/O_VL
Data Inputs I/O_VL
0.4
IL_VL
n
Control Input EN
V x 0.3
L
V
I/O Low Level I/O_VCC
Data Inputs I/O_VCC
0.4
0.4
V
V
IL_VCC
n
V
OL
Low Level Output Volt-
age
V = 0.15 V, I = 6 mA
IL OL
I
Input Leakage Current
Control Input EN, V = V or GND 1.65–5.50 1.65–5.50
1
2
mA
mA
L
IN
L
I
Power−Off Leakage
Current
I/O_VL ,
V
IN
or V = 0 to 5.5 V
0
0
OFF
n
O
I/O_VCC
n
I/O_VL
0
5.50
0
n
I/O_VCC
5.50
5.50
n
I
Tristate Output Mode
Leakage Current
(Note 3)
I/O_VL ,
V
= 0 to 5.5 V,
5.50
2
mA
OZ
n
O
I/O_VCC
EN = V
n
IL
I/O_VL
V
= 0 to 5.5 V,
5.50
0
0
n
O
EN = Don’t Care
I/O_VCC
5.50
n
I
Quiescent Supply
Current, Active Mode
(Notes 4, 5)
V
V
V
V
V
V
O
= V or GND,
1.65–5.50 1.65–5.50
5.0
5.0
2.0
mA
mA
mA
CC
L
IN
CCI
I
= 0, EN = V
IH_VL
CC
L
I
Quiescent Supply
Current, Standby Mode
(Notes 4, 5)
V
O
= V
or GND,
1.65–5.50 1.65–5.50
CCZ
IN
CCI
I
= 0, EN = V
IL_VL
CC
L
I
Quiescent Supply
Current, Power−Off
(Notes 3, 5)
V
O
= 5.5 V or GND,
= 0, EN = Don’t
0
1.65–5.50
CC_OFF
IN
I
Care, I/O_VCC to
I/O_VL
1.65–5.50
1.65–5.50
0
0
0
V
CC
V
O
= 5.5 V or GND,
= 0, EN = Don’t
IN
I
Care, I/O_VL to
I/O_VCC
1.65–5.50
1. Typical values are for V = +1.8 V, V = +3.3 V and T = +25°C.
L
CC
A
2. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
3. “Don’t care” indicates any valid logic level.
4. V
is the power supply associated with the input side.
CCI
5. Reflects current per supply, V or V
.
L
CC
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4
NLSX4302E
DYNAMIC OUTPUT ELECTRICAL CHARACTERISTICS
OUTPUT RISE / FALL TIMES (Output Load: C = 50 pF, R = 2.2 kW, push/pull driver, T = −40°C to +85°C) (Note 6)
L
PU
A
V
CCO
(Note 7)
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Typ
6.4
10
Typ
5
Typ
6.5
8.6
Typ
10.7
9.5
Symbol
Parameter
Output Rise Time, I/O_VL , I/O_VCC
n
Unit
ns
t
t
RISE
FALL
n
Output Fall Time, I/O_VL , I/O_VCC
9.5
ns
n
n
6. Output rise and fall times guaranteed by design and are not production tested.
7. V is the V or V power supply associated with the output side.
CCO
L
CC
MAXIMUM DATA RATE (Output Load: C = 50 pF, R = 2.2 kW, push/pull driver, T = −40°C to +85°C) (Note 8)
L
PU
A
V
CC
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Min
50
Min
41
Min
31
Min
17
V
Parameter
Unit
MHz
MHz
MHz
MHz
L
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
34
35
36
23
I/O_VL ,to I/O_VCC or I/O_VCC to
n
n
n
n
I/O_VL
25
27
30
24
14
16
22
21
8. Maximum frequency guaranteed by design and is not production tested.
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5
NLSX4302E
AC ELECTRICAL CHARACTERISTICS (Output Load: C = 50 pF, R = 2.2 kW, push/pull driver, T = −40°C to +85°C) (Note 9)
L
PU
A
V
CC
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Symbol
V = 4.5 to 5.5 V
Parameter
Unit
L
t
I/O_VL to I/O_VCC ,
2.5
5
4.3
8.1
3
5
3
8
6.4
4
8.6
ns
ns
PLH
n
n
n
I/O_VCC to I/O_VL
n
t
I/O_VL to I/O_VCC ,
8
13
17.3
15
28.5
PHL
n
n
n
I/O_VCC to I/O_VL
n
t
t
OE to I/O_Vl , OE to I/O_VCC
14
24
19.6
31.4
0.3
16
25
20
32
22
24
26.5
31.8
0.8
33
28
44
36.2
1.9
ns
ns
ns
PZL
n
n
OE to I/O_Vl , OE to I/O_VCC
PLZ
n
n
t
I/O_VL to I/O_VCC ,
0.3
0.5
0.6
0.8
1.2
skew
n
n
n
(Note 10)
I/O_VCC to I/O_VL
n
V = 3.0 to 3.6 V
L
t
I/O_VL to I/O_VCC ,
2.5
7
4.7
3
6
5.4
3
8
6.5
5
9.3
27
ns
ns
PLH
n
n
n
I/O_VCC to I/O_VL
n
t
I/O_VL to I/O_VCC ,
14.2
10.1
14.6
15
PHL
n
n
n
I/O_VCC to I/O_VL
n
t
t
OE to I/O_Vl , OE to I/O_VCC
15
25
18.8
34.9
0.5
18
22
22.3
27.6
0.6
19
22
23.5
27.9
0.7
29
23
38.3
28.8
3.0
ns
ns
ns
PZL
n
n
OE to I/O_Vl , OE to I/O_VCC
PLZ
n
n
t
I/O_VL to I/O_VCC ,
0.4
0.5
0.6
2.5
skew
n
n
n
(Note 10)
I/O_VCC to I/O_VL
n
V = 2.3 to 2.7 V
L
t
I/O_VL to I/O_VCC ,
3
5.6
4
6
4
8
7.3
6
10.3
22.1
ns
ns
PLH
n
n
n
I/O_VCC to I/O_VL
n
t
I/O_VL to I/O_VCC ,
12
18.1
11
14.1
11.9
15
PHL
n
n
n
I/O_VCC to I/O_VL
n
t
t
OE to I/O_Vl , OE to I/O_VCC
16
28
23.7
33.8
0.7
17
26
21.5
31
1
25
25
30
30.8
0.6
31
25
36.6
30
ns
ns
ns
PZL
n
n
OE to I/O_Vl , OE to I/O_VCC
PLZ
n
n
t
I/O_VL to I/O_VCC ,
0.5
0.8
0.6
2.3
2.7
skew
n
n
n
(Note 10)
I/O_VCC to I/O_VL
n
V = 1.65 to 1.95 V
L
t
I/O_VL to I/O_VCC ,
5
9
5
9.2
6
9.2
7
12.7
19
ns
ns
PLH
n
n
n
I/O_VCC to I/O_VL
n
t
I/O_VL to I/O_VCC ,
19
28.3
15
25.5
12
17.3
14
PHL
n
n
n
I/O_VCC to I/O_VL
n
t
t
OE to I/O_Vl , OE to I/O_VCC
23
35
32.2
44
22
32
26.5
38.7
1.5
25
33
32
36.7
1.1
40
30
72
36.5
2.5
ns
ns
ns
PZL
n
n
OE to I/O_Vl , OE to I/O_VCC
PLZ
n
n
t
I/O_VL to I/O_VCC ,
0.5
1.1
1.4
0.8
2.0
skew
n
n
n
(Note 10)
I/O_VCC to I/O_VL
n
9. AC characteristics are guaranteed by design and are not production tested.
10.Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VL or I/O_VCC )
n
n
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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6
NLSX4302E
CAPACITANCE (T = 25°C)
A
Symbol
Parameter
Test Condition
Typical
Unit
pF
C
IN
C
IO
Input Capacitance, Control Pin (EN)
Input / Output Capacitance
V = V = GND
2
3
L
CC
V = V = 5 V,EN = GND, I/O_VL = I/O_VCC = 5 V
pF
L
CC
n
n
(I/O_VL , I/O_VCC )
n
n
C
PD
Power Dissipation Capacitance (Note 11)
V = V = 5 V,EN = 5 V, V = 5 V or GND, f = 400 KHz
17
pF
L
CC
IN
11. C is defined as the value of the internal equivalent capacitance per channel.
PD
TEST SETUP AND TIMING DEFINITIONS
Figure 3. AC Test Circuit
Figure 4. Propagation Delays and Tri-State Measurements
Figure 5. Definition of Rise and Fall Times
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7
NLSX4302E
Figure 6. Definition of Output Skew
Figure 7. Definition of Output Tri-State Times
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8
NLSX4302E
APPLICATIONS INFORMATION
Level Translator Architecture
when the transmitter is not transmitting data. Normal
translation operation occurs when the EN pin is equal to a
The NLSX4302E auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
logic high signal. The EN pin is referenced to the V supply
L
and has Overvoltage Tolerant (OVT) protection.
supply voltages, V and V , which set the logic levels on
L
CC
Power Supply Guidelines
The sequencing of the power supplies will not damage
the device during the power up operation. In addition, the
the input and output sides of the translator. When used to
transfer data from the V to the V ports, input signals
L
CC
referenced to the V supply are translated to output signals
L
I/O V and I/O V pins are in the high impedance state if
CC
L
with a logic level matched to V . In a similar manner, the
CC
either supply voltage is equal to 0 V. For optimal
performance, 0.01 mF to 0.1 mF decoupling capacitors
V
CC
to V translation shifts input signals with a logic level
L
compatible to V to an output signal matched to V .
CC
L
should be used on the V and V power supply pins.
L
CC
The NLSX4302E consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Each input/output channel requires external pullup
resistors.
Ceramic capacitors are a good design choice to filter and
bypass any noise signals on the voltage lines to the ground
plane of the PCB. The noise immunity will be maximized
by placing the capacitors as close as possible to the supply
and ground pins, along with minimizing the PCB
connection traces.
Enable Input (EN)
The NLSX4302E has an Enable pin (EN) that can be
used to minimize the power consumption of the device
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN8, 1.40x1.20, 0.40P
CASE 523AS
ISSUE B
SCALE 4:1
DATE 19 AUG 2021
GENERIC
MARKING DIAGRAM*
XXM
1
XX = Specific Device Code
M
= Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON58906E
UQFN8, 1.40x1.20, 0.40P
PAGE 1 OF 1
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NLSX4302EBMUTCG CAD模型
引脚图
封装焊盘图
NLSX4302EBMUTCG 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| NLSX4373 | ONSEMI | 2-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4373DMR2G | ONSEMI | 2-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4373DR2G | ONSEMI | 2-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4373MUTAG | ONSEMI | 2-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4378 | ONSEMI | 4-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4378ABFCT1G | ONSEMI | Level Translator, 4-Bit, 24 Mbps, Dual-Supply | 获取价格 |
|
| NLSX4378BFCT1G | ONSEMI | 4-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4378FCT1G | ONSEMI | 4-Bit 20 Mb/s Dual-Supply Level Translator | 获取价格 |
|
| NLSX4401 | ONSEMI | Dual-Supply Level Translator | 获取价格 |
|
| NLSX4401DFT2G | ONSEMI | 1-Bit 20 Mb/s Dual-SupplyLevel Translator | 获取价格 |
|
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