NLSX4378ABFCT1G [ONSEMI]
Level Translator, 4-Bit, 24 Mbps, Dual-Supply;
| 型号： | NLSX4378ABFCT1G |
| 厂家： | 
ONSEMI |
| 描述： | Level Translator, 4-Bit, 24 Mbps, Dual-Supply PC 驱动 逻辑集成电路 |
| 文件： | 总10页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSX4378A
4-Bit 24 Mb/s Dual-Supply
Level Translator
The NLSX4378A is a 4−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The V I/O and V I/O ports are designed to track two different
CC
L
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MARKING
power supply rails, V and V respectively. The V and V supply
CC
L
CC
L
rails are configurable from 1.65 V to 5.5 V. This allows voltage logic
signals on the V side to be translated into lower, higher or equal
L
DIAGRAM
value voltage logic signals on the V side, and vice−versa.
CC
The NLSX4378A translator has open−drain outputs with
integrated 10 kW pullup resistors on the I/O lines. The integrated
S4378AB
AYWW
G
mBump12
FC SUFFIX
CASE 499AU
pullup resistors are used to pullup the I/O lines to either V or V
.
L
CC
The NLSX4378A is an excellent match for open−drain applications
2
such as the I C communication bus.
A
Y
= Assembly Location
= Year
Features
WW = Work Week
G
= Pb−Free Package
• V can be Less than, Greater than or Equal to V
L
CC
• Wide V Operating Range: 1.65 V to 5.5 V
CC
LOGIC DIAGRAM
Wide V Operating Range: 1.65 V to 5.5 V
L
• High−Speed with 24 Mb/s Guaranteed Date Rate
• Low Bit−to−Bit Skew
V
L
V
CC
GND
EN
• Enable Input is Overvoltage Tolerant (OVT) to 5.5 V
• Nonpreferential Powerup Sequencing
I/O V 1
I/O V
1
2
3
4
L
CC
CC
CC
CC
• Integrated 10 kW Pullup Resistors
• ESD Protection: >7 kV HBM for all pins
• Small Space Saving Package − 2.02 x 1.54 mm mBump12
I/O V 2
I/O V
I/O V
I/O V
L
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
I/O V 3
L
Typical Applications
2
• I C, SMBus, PMBus
I/O V 4
L
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2018 − Rev. 0
NLSX4378A/D
NLSX4378A
V
L
V
CC
One−Shot
Block
One−Shot
Block
PU1
PU2
Gate
Bias
R
10 kW
R
Pullup
10 kW
Pullup
EN
EN
I/O V
I/O V
CC
L
N
Figure 1. Block Diagram (1 I/O Line)
PIN ASSIGNMENT
Pins
PIN LOCATION
Description
Pin
A1
A2
A3
A4
Pin Name
I/O V 1
V
V
Input Voltage
CC
L
CC
L
V
V Input Voltage
L
I/O V 2
L
GND
EN
Ground
I/O V 3
L
Output Enable
I/O VL4
I/O V
n
V
I/O Port, Referenced to V
B1
B2
B3
B4
C1
C2
C3
C4
V
CC
CC
CC
CC
I/O V n
V I/O Port, Referenced to V
L
V
L
L
L
EN
FUNCTION TABLE
GND
EN
L
Operating Mode
Hi−Z
I/O V
1
2
3
4
CC
CC
CC
CC
I/O V
I/O V
I/O V
H
I/O Buses Connected
mBump12
(2.02 x 1.54 mm)
A
B
C
1
I/O V 1
V
I/O V
I/O V
I/O V
1
2
L
CC
CC
2
3
4
I/O V 2
V
L
L
CC
I/O V 3
EN
3
4
L
CC
I/O V 4 GND I/O V
L
CC
(Bottom View)
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2
NLSX4378A
MAXIMUM RATINGS
Symbol
Parameter
Condition
Value
Unit
V
V
DC Supply Voltage
DC Supply Voltage
−0.3 to +7.0
−0.3 to +7.0
CC
L
V
V
I/O V
I/O V
V
−Referenced DC Input/Output Voltage
−0.3 to (V + 0.3)
V
CC
CC
CC
V −Referenced DC Input/Output Voltage
L
−0.3 to (V + 0.3)
V
L
L
V
Enable Control Pin DC Input Voltage
−0.3 to +7.0
40
V
EN
I
Short−Circuit Duration (I/O V and I/O V to GND)
Continuous
mA
°C
mA
V
I/O_SC
L
CC
T
STG
Storage Temperature
Latch−up Current
−65 to +150
100
I
LU
ESD Rating
Human Body Model
Charged Device Model
7000
2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
1.65
GND
GND
−55
Max
5.5
5.5
5.5
Unit
V
V
CC
DC Supply Voltage
V
L
DC Supply Voltage
V
V
EN
Enable Control Pin Voltage
I/O Pin Voltage
V
V
IO
V
or V
L
V
CC
T
A
Operating Temperature Range
+125
°C
Functionaloperation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
RecommendedOperating Ranges limits may affect device reliability.
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3
NLSX4378A
DC ELECTRICAL CHARACTERISTICS (V = 1.65 V to 5.5 V and V = 1.65 V to 5.5 V, unless otherwise specified)
CC
L
−405C to +855C
−555C to +1255C
Typ
(Notes 1, 2)
Min
Max
−
Min
V − 0.4
CC
Max
−
Symbol
Parameter
I/O V Input HIGH Voltage
Test Conditions
Unit
V
V
IHC
V
− 0.4
−
−
−
−
−
CC
CC
V
V
I/O V Input LOW Voltage
−
0.15
−
−
0.15
−
V
ILC
CC
I/O V Input HIGH Voltage
V − 0.4
L
V − 0.4
L
V
IHL
L
V
ILL
I/O V Input LOW Voltage
−
0.15
−
−
0.15
−
V
L
V
IH
Control Pin Input HIGH
Voltage
0.65 * V
0.65 * V
V
L
L
V
Control Pin Input LOW
Voltage
−
−
−
0.35 * V
−
−
0.35 * V
−
V
V
IL
L
L
V
OHC
I/O V Output HIGH Voltage I/O V Source Current = 0.8 * V
0.8 * V
−
CC
CC
CC
CC
20 mA
V
I/O V Output LOW Voltage
I/O V Sink Current =
−
−
0.4
−
0.4
−
V
OLC
OHL
CC
CC
1.0 mA, I/O_V ≤ 0.15 V
L
V
I/O V Output HIGH Voltage
I/O V Source Current =
0.8 * V
−
0.8 * V
L
V
L
L
L
20 mA
V
I/O V Output LOW Voltage
I/O V Sink Current =
−
−
−
−
−
−
−
−
0.4
2.0
1.0
1.0
1.0
1.0
−
−
−
−
−
−
−
−
0.4
3.0
3.0
1.5
1.5
1.0
−
V
OLL
L
L
1.0 mA, I/O_V ≤ 0.15 V
CC
I
V
CC
Supply Current
I/O V and I/O V
L
0.5
0.3
0.1
0.1
0.1
10
mA
mA
mA
mA
mA
kW
QVCC
CC
Unconnected, V = V
EN
L
I
V Supply Current
L
I/O V and I/O V
CC L
QVL
Unconnected, V = V
EN
L
I
V
CC
Tristate Output Mode
I/O V and I/O V
CC L
TS−VCC
Supply Current
Unconnected, V = GND
EN
I
V Tristate Output Mode
I/O V and I/O V
CC L
TS−VL
L
Supply Current
Unconnected, V = GND
EN
I
I/O Tristate Output Mode
Leakage Current
T = +25°C
A
OZ
R
Pullup Resistor I/O V and
T = +25°C
A
PU
L
V
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performancemay not be indicated by the Electrical Characteristics if operated under different conditions.
1. Typical values are for V = +2.8 V, V = +1.8 V and T = +25°C.
CC
L
A
2. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
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4
NLSX4378A
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, C
= 15 pF, driver output impedance v 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
−555C to +1255C
(Note 3)
(Note 3)
Min
Typ
Max
Min
Max
Symbol
V = 1.65 V, V = 5.5 V
Parameter
Test Conditions
Unit
L
CC
t
I/O V Risetime
15
30
30
10
20
20
5
15
30
30
10
20
20
5
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
24
24
V = 1.8 V, V = 2.8 V
L
CC
t
I/O V Risetime
15
15
25
10
15
15
5
15
15
25
10
15
15
5
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
24
24
24
24
V = 2.5 V, V = 3.6 V
L
CC
t
I/O V Risetime
15
10
15
10
15
15
5
15
10
15
10
15
15
5
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
24
V = 2.8 V, V = 1.8 V
L
CC
t
I/O V Risetime
25
10
15
15
15
15
5
25
10
15
15
15
15
5
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
24
3. Limits over the operating temperature range are guaranteed by design.
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5
NLSX4378A
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, C
= 15 pF, driver output impedance v 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
−555C to +1255C
(Note 3)
(Note 3)
Min
Typ
Max
Min
Max
Symbol
V = 3.6 V, V = 2.5 V
Parameter
Test Conditions
Unit
L
CC
t
I/O V Risetime
15
10
15
10
15
15
5
15
10
15
10
15
15
5
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
24
24
V = 5.5 V, V = 1.65 V
L
CC
t
I/O V Risetime
30
10
15
30
20
20
5
30
10
15
30
20
20
5
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
24
24
3. Limits over the operating temperature range are guaranteed by design.
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 4 and 5, C
= 15 pF, driver output impedance v 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
−555C to +1255C
(Note 4)
(Note 4)
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
+1.65 v V , V v +5.5 V
L
CC
t
I/O V Risetime
400
50
400
50
ns
ns
RVCC
CC
t
I/O V Falltime
CC
FVCC
t
I/O V Risetime
400
60
400
60
ns
RVL
L
t
I/O V Falltime
ns
FVL
L
t
t
Propagation Delay (Driving I/O V )
1000
1000
50
1000
1000
50
ns
PDVL−VCC
PDVCC−VL
L
Propagation Delay (Driving I/O V
Channel−to−Channel Skew
Maximum Data Rate
)
ns
CC
t
nS
Mb/s
SKEW
MDR
2
2
4. Limits over the operating temperature range are guaranteed by design.
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6
NLSX4378A
TEST SETUPS
NLSX4378A
NLSX4378A
V
L
V
CC
V
L
V
CC
EN
EN
I/O V
I/O V
L
I/O V
L
I/O V
CC
CC
Source
C
LOAD
C
LOAD
Source
R
LOAD
R
LOAD
Figure 2. Rail−to−Rail Driving I/O VL
Figure 3. Rail−to−Rail Driving I/O VCC
NLSX4378A
NLSX4378A
V
L
V
L
V
CC
V
CC
EN
EN
I/O V
CC
I/O V
L
I/O V
CC
V
CC
C
LOAD
C
LOAD
R
LOAD
R
LOAD
Figure 4. Open−Drain Driving I/O VL
Figure 5. Open−Drain Driving I/O VCC
t
v
I/O V
t
RISE/FALL
v 3 ns
RISE/FALL
I/O V
CC
L
3 ns
90%
50%
10%
90%
50%
10%
t
L
t
t
t
PD_VCC−VL
PD_VCC−VL
PD_VL−VCC
PD_VL−VCC
I/O V
I/O V
CC
90%
50%
10%
90%
50%
10%
t
t
R−VCC
t
t
R−VL
F−VCC
F−VL
Figure 6. Definition of Timing Specification Parameters
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7
NLSX4378A
APPLICATIONS INFORMATION
Level Translator Architecture
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 W.
The NLSX4378A auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
Enable Input (EN)
supply voltages, V and V , which set the logic levels on
L
CC
The NLSX4378A has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the input and output sides of the translator. When used to
transfer data from the V to the V ports, input signals
L
CC
referenced to the V supply are translated to output signals
L
the device and drives the I/O V and I/O V pins to a high
CC
L
with a logic level matched to V . In a similar manner, the
CC
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
V
CC
to V translation shifts input signals with a logic level
L
compatible to V to an output signal matched to V .
CC
L
is referenced to the V supply and has Overvoltage
L
The NLSX4378A consists of four bi−directional
channels that independently determine the direction of the
data flow without requiring a directional pin. The one−shot
circuits are used to detect the rising input signals. In
addition, the one shots decrease the rise time of the output
signal for low−to−high transitions.
Each input/output pin has an internal 10 kW pull−up
resistor. The magnitude of the pull−up resistors can be
reduced by connecting external resistors in parallel to the
internal 10 kW resistors.
Tolerant (OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage V can be
L
greater than, less than or equal to V . The sequencing of
CC
the power supplies will not damage the device during the
power up operation.
For optimal performance, 0.01 mF to 0.1 mF decoupling
capacitors should be used on the V and V power supply
L
CC
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the voltage lines to the
ground plane of the PCB. The noise immunity will be
maximized by placing the capacitors as close as possible to
the supply and ground pins, along with minimizing the
PCB connection traces.
Input Driver Requirements
The rise (t ) and fall (t ) timing parameters of the open
R
F
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (t ), skew
PD
(t
) and maximum data rate depend on the impedance
SKEW
of the device that is connected to the translator. The timing
ORDERING INFORMATION
†
Device
NLSX4378ABFCT1G
Package
mBump12
Shipping
3000 / Tape & Reel
(Backside Laminate Coating)
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
12 PIN FLIP−CHIP, 2.02x1.54, 0.5P
CASE 499AU−01
ISSUE O
DATE 19 MAR 2007
SCALE 4:1
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B
E
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
2X
MILLIMETERS
0.10
C
DIM MIN
MAX
0.66
0.27
0.39
0.34
A
A1
A2
b
−−−
0.21
0.33
0.29
2X
0.10
C
TOP VIEW
D
D1
E
E1
e
2.02 BSC
A
1.50 BSC
1.54 BSC
1.00 BSC
0.50 BSC
A2
0.10
C
C
A1
0.05
12X
SEATING
PLANE
C
NOTE 3
SIDE VIEW
D1
e/2
e
12X
b
C
B
A
0.05
0.03
C
C
A B
E1
1
2
3
4
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON24295D
12 PIN FLIP−CHIP, 2.02 X 1.54, 0.5P
PAGE 1 OF 1
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© Semiconductor Components Industries, LLC, 2019
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associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
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