NLV14011BDTR2G [ONSEMI]
B-Suffix Series CMOS Gates;
| 型号： | NLV14011BDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | B-Suffix Series CMOS Gates 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
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Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
MARKING DIAGRAMS
14
1
14
1
• Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
14
0xxB
ALYWG
G
140xxBG
AWLYWW
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
SOIC−14
TSSOP−14
• These Devices are Pb−Free and are RoHS Compliant
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
= Year
V
DD
DC Supply Voltage Range
WW, W = Work Week
G or G
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
= Pb−Free Package
(Note: Microdot may be in either location)
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
DEVICE INFORMATION
P
Power Dissipation, per Package
(Note 1)
500
mW
D
Device
MC14001B
MC14011B
Description
T
A
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
T
stg
T
Lead Temperature
(8−Second Soldering)
L
MC14023B
MC14025B
MC14071B
MC14073B
Triple 3−Input NAND Gate
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
V
ESD
ESD Withstand Voltage
Human Body Model
Machine Model
V
> 3000
> 300
N/A
Charged Device Model
MC14081B
MC14082B
Quad 2−Input AND Gate
Dual 4−Input AND Gate
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V ≤ (V or V ) ≤ V .
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2014 − Rev. 11
MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR
NAND
OR
AND
MC14001B
MC14011B
MC14071B
MC14081B
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Quad 2−Input OR Gate
Quad 2−Input AND Gate
1
3
2
1
3
2
1
3
2
1
3
2
5
4
6
5
4
6
5
4
6
5
4
6
8
8
8
8
10
10
10
10
9
9
9
9
12
13
12
11
13
12
13
12
11
13
11
11
MC14025B
MC14023B
MC14073B
MC14082B
Triple 3−Input NOR Gate
Triple 3−Input NAND Gate
Triple 3−Input AND Gate
Dual 4−Input AND Gate
1
2
8
1
2
8
1
2
8
2
9
9
9
3
1
4
5
9
3
4
5
3
4
5
3
4
5
6
6
6
10
13
11
12
13
11
12
13
11
12
13
11
12
10
10
10
NC = 6, 8
V
DD
= PIN 14
V
= PIN 7
FOR ALL DEVICES
SS
PIN ASSIGNMENTS
MC14023B
Triple 3−Input NAND Gate
MC14025B
Triple 3−Input NOR Gate
MC14001B
Quad 2−Input NOR Gate
MC14011B
Quad 2−Input NAND Gate
IN 1
IN 2
1
2
3
4
5
6
7
14
V
IN 1
IN 2
1
2
3
4
5
6
7
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
7
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
7
14
V
DD
A
A
DD
A
A
DD
A
A
B
B
DD
A
A
B
B
13 IN 2
13 IN 2
13 IN 3
12 IN 2
11 IN 1
13 IN 3
12 IN 2
11 IN 1
D
D
D
D
C
C
C
C
C
C
OUT
12 IN 1
OUT
A
12 IN 1
A
OUT
IN 1
IN 2
11 OUT
10 OUT
OUT
IN 1
IN 2
11 OUT
10 OUT
B
D
C
B
D
C
10 OUT
10 OUT
C
B
B
B
B
B
B
C
B
B
9
8
IN 2
IN 1
9
8
IN 2
IN 1
9
8
OUT
9
8
OUT
A
C
C
A
V
SS
V
SS
V
SS
IN 3
V
SS
IN 3
A
C
C
A
MC14071B
Quad 2−Input OR Gate
MC14073B
Triple 3−Input AND Gate
MC14081B
Quad 2−Input AND Gate
MC14082B
Dual 4−Input AND Gate
IN 1
IN 2
1
2
3
4
5
6
7
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
7
14
V
IN 1
1
2
3
4
5
6
7
14
V
OUT
1
2
3
4
5
6
7
14
13 OUT
B
V
A
DD
A
A
B
B
DD
A
A
DD
A
DD
13 IN 2
13 IN 3
12 IN 2
11 IN 1
IN 2
13 IN 2
12 IN 1
11 OUT
10 OUT
IN 1
IN 2
IN 3
IN 4
A
D
D
C
C
C
D
D
D
C
A
A
A
A
OUT
12 IN 1
OUT
12 IN 4
11 IN 3
10 IN 2
A
A
B
OUT
IN 1
IN 2
11 OUT
10 OUT
OUT
IN 1
IN 2
B
D
C
B
B
10 OUT
B
B
B
B
C
B
B
B
B
9
8
IN 2
IN 1
9
8
OUT
9
8
IN 2
C
NC
9
8
IN 1
NC
C
A
V
SS
V
SS
IN 3
V
SS
IN 1
V
SS
C
A
C
NC = NO CONNECTION
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2
MC14001B Series
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
Typ
125_C
V
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Vdc
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
–3.0
–0.64
–1.6
−
−
−
−
–2.4
–0.51
–1.3
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
–4.2
–3.4
–2.4
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
I
T
5.0
10
15
I = (0.3 mA/kHz) f + I /N
T DD
I = (0.6 mA/kHz) f + I /N
T
DD
Per Gate, C = 50 pF)
I = (0.9 mA/kHz) f + I /N
T
L
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
T
L
DD
SS
per package.
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3
MC14001B Series
B−SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
V
DD
Typ
Vdc
(Note 6)
Characteristic
Symbol
Min
Max
Unit
Output Rise Time, All B−Series Gates
t
ns
TLH
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
L
TLH
TLH
TLH
5.0
10
15
−
−
−
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/PF) C + 20 ns
L
Output Fall Time, All B−Series Gates
t
ns
ns
t
t
t
= (1.35 ns/pF) C + 33 ns
L
THL
THL
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/pF) C + 20 ns
L
Propagation Delay Time
t
, t
PLH PHL
MC14001B, MC14011B only
t
t
t
, t
= (0.90 ns/pF) C + 80 ns
= (0.36 ns/pF) C + 32 ns
L
5.0
10
15
−
−
−
125
50
40
250
100
80
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 27 ns
PLH PHL
L
All Other 2, 3, and 4 Input Gates
t
t
t
, t
= (0.90 ns/pF) C + 115 ns
= (0.36 ns/pF) C + 47 ns
L
5.0
10
15
−
−
−
160
65
50
300
130
100
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 37 ns
PLH PHL
L
8−Input Gates (MC14068B, MC14078B)
t
t
t
, t
= (0.90 ns/pF) C + 155 ns
= (0.36 ns/pF) C + 62 ns
L
5.0
10
15
−
−
−
200
80
60
350
150
110
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 47 ns
PLH PHL
L
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
14
V
DD
V
DD
90%
50%
10%
INPUT
INPUT
*
0 V
PULSE
OUTPUT
t
t
PLH
GENERATOR
PHL
90%
50%
10%
V
V
OH
C
L
OUTPUT
OL
INVERTING
t
t
TLH
THL
t
t
PHL
PLH
V
V
OH
7
V
SS
OUTPUT
90%
50%
10%
NON-INVERTING
*All unused inputs of AND, NAND gates must be connected to V
.
OL
DD
t
t
THL
TLH
All unused inputs of OR, NOR gates must be connected to V
.
SS
Figure 1. Switching Time Test Circuit and Waveforms
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4
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
MC14025B
One of Four Gates Shown
One of Three Gates Shown
V
DD
V
DD
14
V
DD
1, 3, 11
2, 4, 12
1, 6, 8, 13
2, 5, 9, 12
*
14
V
DD
3, 4, 10, 11
*
V
SS
9, 6, 10
V
SS
7
V
SS
V
DD
*Inverter omitted in MC14001B
8, 5, 13
7
V
SS
V
SS
*Inverter omitted in MC14025B
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14023B, MC14073B
MC14011B, MC14081B
One of Three Gates Shown
One of Four Gates Shown
V
DD
14
V
DD
*
3, 4, 10, 11
2, 5, 9, 12
2, 4, 12
1, 3, 11
14
V
DD
1, 6, 8, 13
V
7
*Inverter omitted in MC14011B
SS
V
SS
*
V
DD
9, 6, 10
8, 5, 13
7
*Inverter omitted in MC14023B
V
SS
V
SS
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5
MC14001B Series
TYPICAL B−SERIES GATE CHARACTERISTICS
N−CHANNEL DRAIN CURRENT (SINK)
P−CHANNEL DRAIN CURRENT (SOURCE)
- 10
5.0
4.0
3.0
- 9.0
- 8.0
- 7.0
- 6.0
- 5.0
- 4.0
T = - 55°C
A
T = - 55°C
A
- 40°C
- 40°C
+ 25°C
+ 25°C
+ 85°C
+ 85°C
+ 125°C
2.0
1.0
+ 125°C
- 3.0
- 2.0
- 1.0
0
0
0
1.0
2.0
3.0
4.0
5.0
0
- 1.0
- 2.0
V , DRAIN-TO-SOURCE VOLTAGE (Vdc)
DS
- 3.0
- 4.0
- 5.0
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 2. VGS = 5.0 Vdc
Figure 3. VGS = − 5.0 Vdc
20
18
16
14
12
10
8.0
- 50
- 45
- 40
- 35
- 30
- 25
- 20
T = - 55°C
A
- 40°C
+ 25°C
+ 85°C
T = - 55°C
A
- 40°C
+ 125°C
+ 25°C
+ 85°C
6.0
4.0
2.0
0
- 15
- 10
- 5.0
0
+ 125°C
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
0
- 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 4. VGS = 10 Vdc
Figure 5. VGS = − 10 Vdc
50
45
40
35
30
25
20
- 100
- 90
- 80
- 70
- 60
- 50
- 40
T = - 55°C
A
- 40°C
+ 25°C
T = - 55°C
A
- 40°C
+ 85°C
+ 125°C
+ 85°C
+ 25°C
+ 125°C
15
10
5.0
0
- 30
- 20
- 10
0
0
2.0 4.0 6.0 8.0 10
12
14
16
18
20
0
- 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 - 18 - 20
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 6. VGS = 15 Vdc
Figure 7. VGS = − 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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6
MC14001B Series
TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
10
8.0
6.0
4.0
3.0
2.0
1.0
0
SINGLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
MULTIPLE INPUT NAND, AND
4.0
2.0
0
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
16
DC NOISE MARGIN
SINGLE INPUT NAND, AND
14
12
10
MULTIPLE INPUT NOR, OR
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V and V for the output(s) to
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
IL
IH
be at a fixed voltage V are given in the Electrical
O
8.0
6.0
Characteristics table. V and V are presented graphically
IL
IH
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
4.0
2.0
0
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
Figure 10. VDD = 15 Vdc
V
out
V
DD
V
out
V
DD
V
O
V
O
V
O
V
O
V
V
V
V
DD
DD
0
0
in
in
V
IL
V
IH
V
IL
V
IH
V
SS
= 0 VOLTS DC
(a) Inverting Function
(b) Non−Inverting Function
Figure 11. DC Noise Immunity
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7
MC14001B Series
ORDERING INFORMATION
Device
†
Package
Shipping
MC14001BDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14001BDG*
MC14001BDR2G
NLV14001BDR2G*
MC14001BDTR2G
NLV14001BDTR2G*
MC14001BFELG
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
TSSOP−14
(Pb−Free)
SOEIAJ−14
(Pb−Free)
2000 Units / Tape & Reel
55 Units / Rail
MC14011BDG
SOIC−14
(Pb−Free)
NLV14011BDG*
MC14011BDR2G
NLV14011BDR2G*
MC14011BDTR2G
NLV14011BDTR2G*
MC14011BFG
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
TSSOP−14
(Pb−Free)
50 Units / Rail
SOEIAJ−14
(Pb−Free)
MC14011BFELG
2000 Units / Tape & Reel
MC14023BDG
SOIC−14
(Pb−Free)
55 Units / Rail
MC14023BDR2G
NLV14023BDR2G*
MC14023BFELG
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
2000 Units / Tape & Reel
SOEIAJ−14
(Pb−Free)
MC14025BDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14025BDG*
MC14025BDR2G
NLV14025BDR2G*
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC14071BDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14071BDG*
MC14071BDR2G
NLV14071BDR2G*
MC14071BDTG
MC14071BDTR2G
NLV14071BDTR2G*
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
96 Units per Rail
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
MC14073BDG
SOIC−14
(Pb−Free)
55 Units / Rail
MC14073BDR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
http://onsemi.com
8
MC14001B Series
ORDERING INFORMATION (continued)
Device
†
Package
Shipping
MC14081BDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14081BDG*
MC14081BDR2G
SOIC−14
(Pb−Free)
NLV14081BDR2G*
MC14081BDTR2G
NLV14081BDTR2G*
2500 Units / Tape & Reel
TSSOP−14
(Pb−Free)
MC14082BDG
55 Units / Rail
SOIC−14
(Pb−Free)
NLV14082BDG*
MC14082BDR2G
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
9
MC14001B Series
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
0.10 (0.004)
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
0
8
0
8
G
_
_
_
_
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
10
MC14001B Series
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC14001B/D
相关型号：
NLV14013BDTR2G
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, HALOGEN FREE AND ROHS COMPLIANT, TSSOP-14
ROCHESTER
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