NLV74HC14ADR2G [ONSEMI]
Hex Schmitt-Trigger Inverter;
| 型号： | NLV74HC14ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Hex Schmitt-Trigger Inverter 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC14A
Hex Schmitt-Trigger
Inverter
High−Performance Silicon−Gate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
http://onsemi.com
The HC14A is useful to “square up” slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds
applications in noisy environments.
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
Features
PIN ASSIGNMENT
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
V
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
CC
14
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 60 FETs or 15 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3 GND
14−Lead (Top View)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAMS
LOGIC DIAGRAM
14
14
HC
14A
HC14AG
1
3
5
2
4
6
A1
A2
A3
Y1
Y2
Y3
ALYWG
AWLYWW
G
1
1
TSSOP−14
SOIC−14 NB
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
Y = A
W, WW = Work Week
G or G
= Pb−Free Package
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
Pin 14 = V
CC
Pin 7 = GND
(Note: Microdot may be in either location)
11
13
FUNCTION TABLE
Inputs
A
Outputs
Y
L
H
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 14
MC74HC14A/D
MC74HC14A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to +7.0
CC
V
–0.5 to V + 0.5
V
in
CC
V
out
–0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
circuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature Range
–65 to +150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
0
Max
Unit
V
V
CC
6.0
V , V
in out
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
V
CC
V
T
A
–55
+125
_C
ns
t , t
Input Rise/Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
No Limit*
No Limit*
No Limit*
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*When V = 50% V , I > 1mA
in
CC CC
http://onsemi.com
2
MC74HC14A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
−55 to 25°C ≤85°C ≤125°C
Unit
V
max
min
max
min
Maximum Positive−Going Input
Threshold Voltage
(Figure 3)
V
= 0.1V
2.0
3.0
4.5
6.0
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
V
T+
out
|I | ≤ 20mA
out
V
Minimum Positive−Going Input
Threshold Voltage
(Figure 3)
V
out
= 0.1V
2.0
3.0
4.5
6.0
1.0
1.5
2.3
3.0
0.95
1.45
2.25
2.95
0.95
1.45
2.25
2.95
V
V
V
V
V
V
T+
|I | ≤ 20mA
out
V
Maximum Negative−Going Input
Threshold Voltage
(Figure 3)
V
out
= V − 0.1V
2.0
3.0
4.5
6.0
0.9
1.4
2.0
2.6
0.95
1.45
2.05
2.65
0.95
1.45
2.05
2.65
T−
CC
|I | ≤ 20mA
out
V
Minimum Negative−Going Input
Threshold Voltage
(Figure 3)
V
out
= V − 0.1V
2.0
3.0
4.5
6.0
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
T−
CC
|I | ≤ 20mA
out
V max
(Note 1)
Maximum Hysteresis Voltage
(Figure 3)
V
out
= 0.1V or V − 0.1V
2.0
3.0
4.5
6.0
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
H
CC
|I | ≤ 20mA
out
V min
(Note 1)
Minimum Hysteresis Voltage
(Figure 3)
V
out
= 0.1V or V − 0.1V
2.0
3.0
4.5
6.0
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
H
CC
|I | ≤ 20mA
out
V
Minimum High−Level Output
Voltage
V
in
≤ V min
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
T−
|I | ≤ 20mA
out
V
in
≤ V min
|I | ≤ 2.4mA
out
|I | ≤ 5.2mA
out
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
T−
out
|I | ≤ 4.0mA
V
OL
Maximum Low−Level Output
Voltage
V
≥ V max
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
T+
|I | ≤ 20mA
out
V
in
≥ V max
|I | ≤ 2.4mA
out
|I | ≤ 5.2mA
out
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
T+
out
|I | ≤ 4.0mA
I
Maximum Input Leakage
Current
V
V
= V or GND
6.0
0.1
1.0
1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
6.0
1.0
10
40
CC
in
CC
I
= 0mA
out
1. V min > (V min) − (V max); V max = (V max) − (V min).
H
T+
T−
H
T+
T−
AC CHARACTERISTICS (C = 50pF, Input t = t = 6ns)
L
r
f
Guaranteed Limit
V
CC
Symbol
Parameter
V
−55 to 25°C
≤85°C
≤125°C
Unit
t
t
,
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
ns
PLH
PHL
19
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
THL
19
C
Maximum Input Capacitance
10
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
22
C
Power Dissipation Capacitance (Per Inverter)*
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
http://onsemi.com
3
MC74HC14A
t
f
t
r
V
CC
90%
50%
10%
INPUT A
GND
t
t
PLH
PHL
90%
50%
10%
OUTPUT Y
t
t
THL
TLH
Figure 1. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 2. Test Circuit
4
3
2
1
(V
T+
)
V typ
H
(V
T-
)
2
3
4
5
6
V
CC
, POWER SUPPLY VOLTAGE (VOLTS)
V typ = (V typ) - (V typ)
T-
H
T+
Figure 3. Typical Input Threshold, VT+, VT− versus Power Supply Voltage
http://onsemi.com
4
MC74HC14A
A
Y
(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times
(b) A Schmitt-Trigger Offers Maximum Noise Immunity
V
CC
V
CC
V
H
V
H
V
V
V
V
T+
T+
V
in
V
in
T-
T-
GND
GND
V
V
OH
OL
OH
OL
V
out
V
out
V
V
Figure 4. Typical Schmitt−Trigger Applications
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC14ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
MC74HC14ADR2G
MC74HC14ADTG
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
MC74HC14ADTR2G
NLV74HC14ADG*
NLV74HC14ADR2G*
NLV74HC14ADTG*
NLV74HC14ADTR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
55 Units / Rail
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
96 Units / Rail
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
http://onsemi.com
5
MC74HC14A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
0.10 (0.004)
L
M
6.40 BSC
0.252 BSC
SEATING
−T−
H
G
0
8
0
8
DETAIL E
_
_
_
_
D
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MC74HC14A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C
A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74HC14A/D
相关型号：
©2020 ICPDF网 联系我们和版权申明