NSVMMBT6517LT1G [ONSEMI]
高压 NPN 双极晶体管;
| 型号： | NSVMMBT6517LT1G |
| 厂家： | 
ONSEMI |
| 描述： | 高压 NPN 双极晶体管 高压 小信号双极晶体管 |
| 文件： | 总8页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MMBT6517LT1/D
SEMICONDUCTOR TECHNICAL DATA
NPN Silicon
Motorola Preferred Device
COLLECTOR
3
1
BASE
3
2
EMITTER
1
MAXIMUM RATINGS
2
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Emitter–Base Voltage
Symbol
Value
Unit
Vdc
V
CEO
350
350
5.0
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
V
Vdc
CBO
EBO
V
Vdc
Base Current
I
250
500
mAdc
mAdc
B
C
Collector Current — Continuous
THERMAL CHARACTERISTICS
Characteristic
I
Symbol
Max
Unit
(1)
Total Device Dissipation FR–5 Board
P
225
mW
D
T
= 25°C
A
Derate above 25°C
1.8
556
300
mW/°C
°C/W
mW
Thermal Resistance, Junction to Ambient
Total Device Dissipation
R
JA
D
P
(2)
Alumina Substrate,
T
A
= 25°C
Derate above 25°C
2.4
417
mW/°C
°C/W
°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
R
JA
T , T
J stg
–55 to +150
MMBT6517LT1 = 1Z
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Max
Unit
Collector–Emitter Breakdown Voltage
(I = 1.0 mAdc)
C
V
V
Vdc
Vdc
(BR)CEO
350
350
6.0
—
—
—
—
50
50
Collector–Base Breakdown Voltage
(I = 100 Adc)
C
(BR)CBO
Emitter–Base Breakdown Voltage
(I = 10 Adc)
E
V
Vdc
(BR)EBO
Collector Cutoff Current
I
nAdc
nAdc
CBO
(V
CB
= 250 Vdc)
Emitter Cutoff Current
(V = 5.0 Vdc)
I
EBO
—
EB
1. FR–5 = 1.0
0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
ON CHARACTERISTICS
Symbol
Min
Max
Unit
DC Current Gain
h
FE
—
(I = 1.0 mAdc, V
= 10 Vdc)
= 10 Vdc)
= 10 Vdc)
= 10 Vdc)
20
30
30
20
15
—
—
200
200
—
C
CE
CE
CE
CE
(I = 10 mAdc, V
C
(I = 30 mAdc, V
C
(I = 50 mAdc, V
C
(I = 100 mAdc, V
CE
= 10 Vdc)
C
Collector–Emitter Saturation Voltage (3)
(I = 10 mAdc, I = 1.0 mAdc)
V
V
Vdc
CE(sat)
—
—
—
—
0.30
0.35
0.50
1.0
C
B
(I = 20 mAdc, I = 2.0 mAdc)
C
C
B
B
B
(I = 30 mAdc, I = 3.0 mAdc)
(I = 50 mAdc, I = 5.0 mAdc)
C
Base–Emitter Saturation Voltage
(I = 10 mAdc, I = 1.0 mAdc)
Vdc
Vdc
BE(sat)
—
—
—
0.75
0.85
0.90
C
C
B
B
B
(I = 20 mAdc, I = 2.0 mAdc)
(I = 30 mAdc, I = 3.0 mAdc)
C
Base–Emitter On Voltage
(I = 100 mAdc, V = 10 Vdc)
V
BE(on)
—
2.0
C
CE
SMALL–SIGNAL CHARACTERISTICS
Current Gain — Bandwidth Product
f
C
C
MHz
pF
T
(I = 10 mAdc, V
C CE
= 20 Vdc, f = 20 MHz)
40
—
—
200
6.0
80
Collector–Base Capacitance
(V = 20 Vdc, f = 1.0 MHz)
cb
eb
CB
Emitter–Base Capacitance
(V = 0.5 Vdc, f = 1.0 MHz)
pF
EB
3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2.0%.
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
200
100
T
= 125°C
V
= 10 V
J
CE
70
50
100
70
25°C
50
T
= 25°C
= 20 V
J
30
20
V
CE
f = 20 MHz
–55°C
30
20
10
1.0
10
2.0 3.0
5.0 7.0 10
20
30
50 70 100
1.0
2.0 3.0
5.0 7.0 10
I , COLLECTOR CURRENT (mA)
C
20
30
50 70 100
I
, COLLECTOR CURRENT (mA)
C
Figure 1. DC Current Gain
Figure 2. Current–Gain — Bandwidth Product
1.4
1.2
2.5
2.0
T
= 25°C
I
J
C
10
I
B
1.5
1.0
1.0
25°C to 125°C
0.5
0
0.8
0.6
0.4
V
@ I /I = 10
C B
R
for V
VC CE(sat)
BE(sat)
θ
–55°C to 25°C
V
@ V = 10 V
CE
BE(on)
–0.5
–1.0
–1.5
–2.0
–2.5
–55°C to 125°C
0.2
R
for V
VB BE
θ
V
@ I /I = 10
C B
CE(sat)
V
@ I /I = 5.0
C B
50 70 100
CE(sat)
20 30
0
1.0
2.0 3.0
5.0 7.0 10
1.0
2.0
3.0
I
5.0 7.0 10
20
30
50 70 100
I
, COLLECTOR CURRENT (mA)
C
, COLLECTOR CURRENT (mA)
C
Figure 3. “On” Voltages
Figure 4. Temperature Coefficients
100
70
50
T
= 25°C
J
C
eb
30
20
10
7.0
5.0
C
cb
3.0
2.0
1.0
0.2
0.5
1.0
2.0
5.0
10
20
50 100 200
V
, REVERSE VOLTAGE (VOLTS)
R
Figure 5. Capacitance
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
10 k
7.0 k
5.0 k
1.0 k
700
V
I
= 100 V
CE(off)
/I = 5.0
t
500
s
t
@ V = 2.0 V
BE(off)
C B
d
T
= 25°C
3.0 k
2.0 k
J
300
200
t
V
I
= 100 V
/I = 5.0
r
CE(off)
C B
= I
1.0 k
700
500
t
100
f
I
T
B1 B2
70
50
= 25°C
J
300
200
30
20
100
10
1.0
1.0
2.0 3.0
5.0 7.0 10
20
30
50 70 100
2.0 3.0
5.0 7.0 10
20
30
50 70 100
I
, COLLECTOR CURRENT (mA)
I
, COLLECTOR CURRENT (mA)
C
C
Figure 7. Turn–Off Time
Figure 6. Turn–On Time
+V
CC
2.2 k
V
ADJUSTED
CC
FOR V
20 k
= 100 V
CE(off)
1.0 k
+10.8 V
50
Ω SAMPLING SCOPE
50
1/2MSD7000
–9.2 V
100
1.0%
PULSE WIDTH
t , t 5.0 ns
DUTY CYCLE
≈
µs
≤
f
r
APPROXIMATELY
–1.35 V
≤
(ADJUST FOR V
(BE)off
= 2.0 V)
FOR PNP TEST CIRCUIT,
REVERSE ALL VOLTAGE POLARITIES
Figure 8. Switching Time Test Circuit
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
SINGLE PULSE
SINGLE PULSE
0.05
0.1
0.1
0.07
0.05
Z
Z
= r(t)
= r(t)
•
•
R
T
T
– T = P
Z
θJC(t)
θJA(t)
θ
θ
JC(t)
JA(t)
θ
JC
JA
J(pk)
J(pk)
C
(pk)
(pk)
0.03
0.02
R
– T = P
Z
θ
A
0.01
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0 k
2.0 k
5.0 k
10 k
t, TIME (ms)
Figure 9. Thermal Response
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
FIGURE A
t
P
P
P
P
P
t
1
1/f
DUTY CYCLE
PEAK PULSE POWER = P
t
1
t
f
1
t
P
P
Design Note: Use of Transient Thermal Resistance Data
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
SOLDERING PRECAUTIONS
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
by T
, the maximum rated junction temperature of the
, the thermal resistance from the device junction to
J(max)
die, R
θJA
ambient, and the operating temperature, T . Using the
A
values provided on the data sheet for the SOT–23 package,
P
can be calculated as follows:
D
•
•
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
T
– T
A
J(max)
P
=
D
R
θJA
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
A
calculate the power dissipation of the device which in this
case is 225 milliwatts.
•
•
•
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
150°C – 25°C
556°C/W
P
=
= 225 milliwatts
D
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad . Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
•
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
3
S
B
1
2
INCHES
MIN MAX
MILLIMETERS
DIM
A
B
C
D
G
H
J
MIN
2.80
1.20
0.89
0.37
1.78
0.013
0.085
0.45
0.89
2.10
0.45
MAX
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.60
1.02
2.50
0.60
V
G
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
C
K
L
S
H
J
D
V
K
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
Motorola Small–Signal Transistors, FETs and Diodes Device Data
7
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MMBT6517LT1/D
◊
相关型号：
©2020 ICPDF网 联系我们和版权申明