NTB35N15T4G [ONSEMI]
NâChannel EnhancementâMode D2PAK; NA ????通道Enhancementâ ????模式D2PAK
| 型号： | NTB35N15T4G |
| 厂家： | 
ONSEMI |
| 描述： | NâChannel EnhancementâMode D2PAK |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTB35N15
Power MOSFET
37 Amps, 150 Volts
N−Channel Enhancement−Mode D2PAK
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Features
• Source−to−DrainDiode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
37 AMPERES, 150 VOLTS
50 mꢀ @ VGS = 10 V
• I
and R
Specified at Elevated Temperature
DSS
DS(on)
N−Channel
2
• Mounting Information Provided for the D PAK Package
• Pb−Free Packages are Available
D
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Drain−to−Source Voltage
Symbol Value Unit
V
150
150
Vdc
Vdc
Vdc
4
DSS
DGR
Drain
Drain−to−Source Voltage (R = 1.0 Mꢀ)
V
V
GS
4
Gate−to−Source Voltage
− Continuous
1
2
V
"20
"40
35N15G
AYWW
GS
− Non−Repetitive (t v10 ms)
p
3
GSM
2
Drain Current − Continuous @ T = 25°C
I
I
37
23
111
Adc
D PAK
CASE 418B
STYLE 2
A
D
− Continuous @ T = 100°C
A
D
− Pulsed (Note 2)
1
2
3
I
DM
Gate Drain Source
Total Power Dissipation @ T = 25°C
P
178
1.43
2.0
W
W/°C
W
A
D
Derate above 25°C
Total Power Dissipation @ T = 25°C (Note 1)
A
35N15
A
Y
= Device Code
= Assembly Location
= Year
Operating and Storage Temperature Range
T , T
J
−55 to
+150
°C
stg
WW
G
= Work Week
= Pb−Free Package
Single Pulse Drain−to−Source Avalanche
E
700
mJ
AS
Energy − Starting T = 25°C
J
(V = 100 Vdc, V = 10 Vdc,
DD
GS
I
= 21.6 A, L = 3.0 mH, R = 25 ꢀ)
L(pk)
G
ORDERING INFORMATION
Thermal Resistance
− Junction−to−Case
°C/W
†
Device
Package
Shipping
R
R
R
0.7
62.5
50
ꢁ
JC
JA
JA
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
ꢁ
ꢁ
2
NTB35N15
D PAK
50 Units/Rail
50 Units/Rail
2
NTB35N15G
D PAK
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
260
°C
L
(Pb−Free)
2
NTB35N15T4
D PAK
800 Tape & Reel
800 Tape & Reel
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
2
NTB35N15T4G
D PAK
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1. When surface mounted to an FR4 board using the minimum recommended
2
pad size, (Cu. Area 0.412 in ).
2. Pulse Test: Pulse Width = 10 ꢂ s, Duty Cycle = 2%.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 5
NTB35N15/D
NTB35N15
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
Vdc
(BR)DSS
(V = 0 Vdc, I = 250 ꢂ Adc)
Temperature Coefficient (Positive)
150
−
−
240
−
−
GS
D
mV/°C
ꢂ Adc
Zero Gate Voltage Drain Current
I
I
DSS
(V = 0 Vdc, V = 150 Vdc, T = 25°C)
−
−
−
−
5.0
50
GS
DS
J
(V = 0 Vdc, V = 150 Vdc, T = 125°C)
GS
DS
J
Gate−Body Leakage Current (V
=
20 Vdc, V = 0)
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS
Gate Threshold Voltage
V
GS(th)
DS(on)
DS(on)
V
= V
I = 250 ꢂ Adc)
GS, D
2.0
−
2.9
−8.56
4.0
−
DS
Temperature Coefficient (Negative)
mV/°C
Static Drain−to−Source On−State Resistance
R
V
ꢀ
(V = 10 Vdc, I = 18.5 Adc)
−
−
0.042
−
0.050
0.120
GS
D
(V = 10 Vdc, I = 18.5 Adc, T = 125°C)
GS
D
J
Drain−to−Source On−Voltage
(V = 10 Vdc, I = 18.5 Adc)
Vdc
−
−
1.55
26
1.78
−
GS
D
Forward Transconductance (V = 10 Vdc, I = 18.5 Adc)
g
FS
mhos
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
(V = 25 Vdc, V = 0 Vdc,
C
−
−
−
2275
450
90
3200
650
pF
ns
DS
GS
iss
f = 1.0 MHz)
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
rss
175
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
Rise Time
(V = 120 Vdc, I = 37 Adc,
t
d(on)
−
−
−
−
−
−
−
20
125
90
35
225
175
210
100
−
DD
D
V
= 10 Vdc,
GS
t
r
R
G
= 9.1 ꢀ)
Turn−Off Delay Time
Fall Time
t
d(off)
t
120
70
f
Total Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
(V = 120 Vdc, I = 37 Adc,
Q
nC
DS
D
tot
gs
gd
V
= 10 Vdc)
GS
Q
Q
14
32
−
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage
(I = 37 Adc, V = 0 Vdc)
V
−
−
1.00
0.88
1.5
−
Vdc
ns
S
GS
SD
(I = 37 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
(I = 37 Adc, V = 0 Vdc,
t
rr
−
−
−
−
170
112
58
−
−
−
−
S
GS
dI /dt = 100 A/ꢂ s)
S
t
a
t
b
Reverse Recovery Stored Charge
Q
1.14
ꢂ
C
RR
3. Pulse Test: Pulse Width = 300 ꢂ s max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
NTB35N15
70
70
60
T = 25°C
V
= 10 V
J
V
≥ 10 V
GS
DS
60
50
40
30
20
V
= 5.5 V
GS
V
= 9 V
GS
50
40
30
20
V
= 8 V
GS
V
= 7 V
GS
V
= 5 V
GS
T = 100°C
J
V
= 6 V
GS
V
= 4.5 V
= 4 V
T = 25°C
J
GS
10
0
10
0
V
T = −55°C
J
GS
0
1
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.1
0.055
0.05
T = 25°C
J
V
= 10 V
GS
0.08
T = 100°C
J
V
= 10 V
GS
0.06
0.04
0.045
0.04
V
= 15 V
GS
T = 25°C
J
0.02
0
0.035
0.03
T = −55°C
J
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.5
2.25
2.0
10,000
1000
V
= 0 V
GS
T = 150°C
J
I
V
= 18.5 A
D
= 10 V
GS
1.75
1.5
1.25
1.0
100
10
T = 100°C
J
0.75
0.5
0.25
0
−50 −25
0
25
50
75
100 125
150
30 40 50 60 70 80 90 100 110 120 130 140150
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (°C)
J
V
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTB35N15
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (ꢃt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
6000
V
= 0 V
V
= 0 V
GS
DS
T = 25°C
J
5000
4000
3000
C
iss
C
rss
C
iss
2000
1000
0
C
oss
C
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTB35N15
1000
12
10
8
120
100
V
I
= 75 V
DD
GS
Q
= 37 A
T
D
V
= 10 V
V
DS
t
f
80
60
40
20
0
V
t
GS
d(off)
Q
Q
t
1
2
r
6
100
4
t
d(on)
2
I
= 37 A
T = 25°C
D
J
10
0
0
10
20
30
40
50
60
70
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
40
V
= 0 V
GS
35
30
25
20
15
T = 25°C
J
10
5
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ꢂ s. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C ꢁ JC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTB35N15
SAFE OPERATING AREA
1000
700
600
V
= 20 V
SINGLE PULSE
I
D
= 21.6 A
GS
T
= 25°C
C
100
10
10 ꢂ s
500
400
300
200
100
0
100 ꢂ s
1 ms
10 ms
dc
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1.0
10
100
1000
25
50
75
100
125
150
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
0.05
R (t) = r(t) R
ꢁ ꢁ
JC JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
t
READ TIME AT t
1
1
0.01
t
2
T
− T = P
R (t)
ꢁ
JC
J(pk)
C
(pk)
DUTY CYCLE, D = t /t
1
2
SINGLE PULSE
0.0001
0.01
0.00001
0.001
0.01
t, TIME (ꢂ s)
0.1
1.0
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
NTB35N15
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
A
4.83
0.89
1.40
8.89
S
1
2
3
2.54 BSC
−T−
SEATING
PLANE
K
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
W
J
G
K
L
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
H
M
N
P
R
S
V
D 3 PL
M
M
0.13 (0.005)
T B
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
VARIABLE
CONFIGURATION
ZONE
2. DRAIN
3. SOURCE
4. DRAIN
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTB35N15
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTB35N15/D
相关型号：
NTB4302G
74A, 30V, 0.0093ohm, N-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 418AA-01, D2PAK-3
ROCHESTER
NTB4302T4G
74A, 30V, 0.0093ohm, N-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 418AA-01, D2PAK-3
ROCHESTER
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