NTP75N03RG [ONSEMI]
功率 MOSFET，25 V，75A，8mΩ，单 N 沟道，D2PAK;
| 型号： | NTP75N03RG |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，25 V，75A，8mΩ，单 N 沟道，D2PAK 局域网 开关 脉冲 晶体管 功率场效应晶体管 |
| 文件： | 总8页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTB75N03R, NTP75N03R
Power MOSFET
75 Amps, 25 Volts
N−Channel D2PAK, TO−220
Features
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• Planar HD3e Process for Fast Switching Performance
75 AMPERES
25 VOLTS
RDS(on) = 5.6 mΩ (Typ)
• Low R
to Minimize Conduction Loss
DS(on)
• Low C to Minimize Driver Loss
iss
• Low Gate Charge
MAXIMUM RATINGS (T = 25°C Unless otherwise specified)
J
4
Parameter
Drain−to−Source Voltage
Symbol Value Unit
4
V
25
V
dc
V
dc
DSS
1
2
Gate−to−Source Voltage − Continuous
V
±20
GS
3
Thermal Resistance − Junction−to−Case
R
P
1.68
74.4
°C/W
W
q
JC
2
D PAK
TO−220AB
CASE 221A
STYLE 5
Total Power Dissipation @ T = 25°C
C
D
CASE 418AA
STYLE 2
Drain Current
− Continuous @ T = 25°C
I
75
225
A
A
C
D
1
− Single Pulse (t = 10 ms)
I
2
p
DM
3
Thermal Resistance − Junction−to−Ambient
(Note 1)
R
60
°C/W
MARKING DIAGRAMS
& PIN ASSIGNMENTS
q
JA
Total Power Dissipation @ T = 25°C
P
2.08
12.6
W
A
A
D
4
Drain Current − Continuous @ T = 25°C
I
D
A
4
Drain
Drain
Thermal Resistance − Junction−to−Ambient
(Note 2)
R
100
°C/W
q
JA
Total Power Dissipation @ T = 25°C
P
1.25
9.7
W
A
A
D
Drain Current − Continuous @ T = 25°C
I
D
A
75N03R
YWW
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
T , T
−55 to
150
°C
J
stg
P75N03R
YWW
E
AS
71.7
mJ
2
1
Gate
3
Energy − Starting T = 25°C
1
Gate
3
J
Drain
(V = 30 V , V = 10 V , I = 12 A ,
Source
DD
dc
GS
dc
L
pk
Source
L = 1 mH, R = 25 W)
G
2
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
T
L
260
°C
75N03
Y
= Device Code
= Year
Drain
WW
= Work Week
1. When surface mounted to an FR4 board using 1 inch pad size,
2
(Cu Area 1.127 in ).
2. When surface mounted to an FR4 board using minimum recommended pad
2
size, (Cu Area 0.412 in ).
ORDERING INFORMATION
†
Device
Package
Shipping
NTP75N03R
NTB75N03R
NTB75N03RT4
TO−220AB
50 Units/Rail
50 Units/Rail
2
D PAK
2
D PAK
800/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
October, 2003 − Rev. 2
NTB75N03R/D
NTB75N03R, NTP75N03R
ELECTRICAL CHARACTERISTICS (T = 25°C Unless otherwise specified)
J
Characteristics
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
V
V
dc
(br)DSS
(V = 0 V , I = 250 mA )
dc
25
−
28
20.5
−
−
GS
dc
D
Temperature Coefficient (Positive)
mV/°C
Zero Gate Voltage Drain Current
I
mA
dc
DSS
(V = 20 V , V = 0 V )
dc
−
−
−
−
1.0
10
DS
dc
GS
(V = 20 V , V = 0 V , T = 150°C)
DS
dc
GS
dc
J
Gate−Body Leakage Current
(V = ±20 V , V = 0 V )
dc
I
nA
dc
GSS
−
−
±100
GS
dc
DS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
V
dc
GS(th)
(V = V , I = 250 mA )
1.0
−
1.5
4.0
2.0
−
DS
GS
D
dc
Threshold Temperature Coefficient (Negative)
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 3)
R
DS(on)
(V = 4.5 V , I = 20 A )
dc
−
−
8.1
5.6
13
8.0
GS
dc
D
(V = 10 V , I = 20 A )
GS
dc
D
dc
Forward Transconductance (Note 3)
(V = 10 V , I = 15 A
g
Mhos
pF
FS
)
dc
−
27
−
DS
dc
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
1333
600
−
−
−
iss
(V = 20 V , V = 0 V,
DS
dc
GS
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
C
oss
f = 1 MHz)
C
218
rss
t
−
−
−
−
−
−
−
6.9
1.3
−
−
−
−
−
−
−
ns
d(on)
t
r
(V = 10 V , V = 10 V ,
dc
GS
dc
DD
I
D
= 30 A , R = 3 W)
dc G
Turn−Off Delay Time
Fall Time
t
18.4
5.5
d(off)
t
f
Gate Charge
Q
Q
Q
13.2
3.3
nC
T
1
2
(V = 5 V , I = 30 A ,
dc
GS
dc
D
V
DS
= 10 V ) (Note 3)
dc
6.2
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
SD
V
dc
(I = 20 A , V = 0 V ) (Note 3)
−
−
0.86
0.73
1.2
−
S
dc
GS
dc
(I = 20 A , V = 0 V , T = 125°C)
S
dc
GS
dc
J
Reverse Recovery Time
t
−
−
−
−
15.6
13.8
−
−
−
−
ns
rr
t
a
(I = 35 A , V = 0 V ,
dc
dI /dt = 100 A/ms) (Note 3)
S
S
dc
GS
t
1.78
b
Reverse Recovery Stored Charge
Q
0.004
mC
RR
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTB75N03R, NTP75N03R
140
120
100
80
140
10 V
5 V
4.5 V
4 V
V
DS
≥ 10 V
120
100
80
8 V
6 V
3.5 V
60
60
T = 25°C
J
3 V
40
40
T = 125°C
J
20
0
20
0
V
GS
= 2.5 V
T = −55°C
J
0
2
4
6
8
10
0
1
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.022
0.018
0.014
0.010
0.022
0.018
0.014
0.010
V
GS
= 10 V
V
GS
= 4.5 V
T = 150°C
J
T = 125°C
J
T = 150°C
J
T = 25°C
J
T = 125°C
J
0.006
0.002
0.006
0.002
T = 25°C
J
T = −55°C
J
T = −55°C
J
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120 140
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
100,000
10,000
1.8
1.6
1.4
1.2
1.0
V
GS
= 0 V
I
V
= 30 A
D
= 10 V
GS
T = 150°C
J
T = 125°C
J
1000
100
0.8
0.6
−50 −25
0
25
50
75
100
125 150
0
5
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
10
15
20
25
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTB75N03R, NTP75N03R
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
2400
T = 25°C
J
C
iss
2000
1600
1200
800
C
rss
C
iss
C
oss
400
0
C
rss
V
5
= 0 V V = 0 V
GS
DS
10
0
5
10
15
20
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTB75N03R, NTP75N03R
8
6
4
1000
V
GS
100
Q
T
Q
Q
2
1
t
d(off)
10
1
t
d(on)
2
0
V
= 10 V
= 35 A
= 10 V
DS
t
t
f
I
= 35 A
I
D
D
T = 25°C
V
GS
J
r
0
4
8
12
16
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
70
V
GS
= 0 V
60
50
40
30
20
T = 150°C
J
10
0
T = 25°C
J
0
0.2
0.4
0.6
0.8
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
exceed (T
− T )/(R ).
currents below rated continuous I can safely be assumed to
J(MAX)
C
θJC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
equal the values indicated.
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5
NTB75N03R, NTP75N03R
SAFE OPERATING AREA
1000
100
V
= 20 V
GS
SINGLE PULSE
= 25°C
T
C
10 µs
100 µs
10
1 ms
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
1
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1
D = 0.5
0.2
0.1
P
(pk)
R
(t) = r(t) R
θ
JC
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.05
t
1
1
0.01
t
2
T
J(pk)
− T = P
R
θ
(t)
JC
C
(pk)
DUTY CYCLE, D = t /t
SINGLE PULSE
1
2
0.1
0.0001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 12. Thermal Response
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6
NTB75N03R, NTP75N03R
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
−B−
W
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
G
J
K
M
S
V
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.92
1.40
−−−
A
S
1
2
3
0.310
0.100 BSC
0.018 0.025
−−−
2.54 BSC
0.46
2.29
7.11
0.64
2.79
−−−
−T−
SEATING
PLANE
K
0.090
0.110
W
0.280
−−−
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
J
G
STYLE 2:
PIN 1. GATE
D 3 PL
M
M
T B
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
VARIABLE
CONFIGURATION
ZONE
U
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
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7
NTB75N03R, NTP75N03R
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
B
F
T
S
4
1
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
−−−
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
2
3
U
H
G
H
J
K
L
L
R
N
Q
R
S
T
V
J
G
D
U
V
Z
N
0.080
2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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NTB75N03R/D
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