NUP4106 [ONSEMI]
Low Capacitance Surface Mount TVS for High-Speed Data Interfaces; 低电容表面贴装TVS用于高速数据接口
| 型号： | NUP4106 |
| 厂家： | 
ONSEMI |
| 描述： | Low Capacitance Surface Mount TVS for High-Speed Data Interfaces |
| 文件： | 总7页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUP4106
Low Capacitance Surface
Mount TVS for High-Speed
Data Interfaces
The NUP4106 transient voltage suppressor is designed to protect
equipment attached to high speed communication lines from ESD and
lightning.
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Features
• SO−8 Package
SO−8 LOW CAPACITANCE
VOLTAGE SUPPRESSOR
500 WATTS PEAK POWER
3.3 VOLTS
• Peak Power − 500 W 8 x 20 mS
• ESD Rating:
IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact)
• UL Flammability Rating of 94 V−0
PIN CONFIGURATION
AND SCHEMATIC
• This is a Pb−Free Device
Typical Applications
I/O 1
REF 1
REF 1
I/O 2
1
2
3
4
8
7
6
5
GND
I/O 4
I/O 3
GND
• High Speed Communication Line Protection
• T1/E1 Secondary Protection
• T3/E3 Secondary Protection
• Analog Video Protection
• Base Stations
2
• I C Bus Protection
SOIC−8
CASE 751
PLASTIC
8
MAXIMUM RATINGS
1
Rating
Symbol
Value
Unit
Peak Power Dissipation
P
pk
500
W
8 x 20 mS @ T = 25°C (Note 1)
MARKING DIAGRAM
A
Junction and Storage Temperature Range T , T
−55 to +150
°C
°C
J
stg
8
Lead Solder Temperature −
T
L
260
P4106
AYWWG
G
Maximum 10 Seconds Duration
IEC 61000−4−2
Contact
Air
ESD
8
15
kV
1
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Non−repetitive current pulse 8 x 20 mS exponential decay waveform
Pin 2/3 to Pin 5/8
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
Package
Shipping
NUP4106DR2G
SO−8
2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
February, 2009 − Rev. 0
NUP4106/D
NUP4106
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Min
5.0
N/A
N/A
N/A
N/A
−
Typ
−
Max
−
Unit
V
Reverse Breakdown Voltage @ I = 1.0 mA
V
BR
t
Reverse Leakage Current @ V
= 3.3 V
I
R
−
5.0
7.0
10
15
15
−
mA
V
RWN
Maximum Clamping Voltage @ I = 1.0 A, 8 x 20 mS
V
−
PP
C
C
C
Maximum Clamping Voltage @ I = 10 A, 8 x 20 mS
V
V
−
V
PP
Maximum Clamping Voltage @ I = 25 A, 8 x 20 mS
−
V
PP
Between I/O Pins and Ground @ V = 0 V, 1.0 MHz
Capacitance
Capacitance
8.0
4.0
pF
pF
R
Between I/O Pins @ V = 0 Volts, 1.0 MHz
−
R
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
F
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
PP
V
C
PP
V
C
V
V
V
Working Peak Reverse Voltage
BR RWM
RWM
V
I
V
F
R
T
I
R
Maximum Reverse Leakage Current @ V
I
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
T
I
F
Forward Current
I
PP
V
F
Forward Voltage @ I
F
Uni−Directional TVS
P
Peak Power Dissipation
Capacitance @ V = 0 and f = 1.0 MHz
pk
C
R
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
TYPICAL CHARACTERISTICS
14
12
100
90
80
70
60
50
40
30
20
t
r
PEAK VALUE I
@ 8 ms
RSM
PULSE WIDTH (t ) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
P
10
8
HALF VALUE I
/2 @ 20 ms
RSM
6
4
t
P
2
0
10
0
0
20
40
t, TIME (ms)
60
80
0
10
20
30
40
50
PEAK PULSE CURRENT (A)
Figure 1. 8 x 20 ms Pulse Waveform
Figure 2. Clamping Voltage vs. Peak Pulse Current
(8 x 20 ms Waveform)
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2
NUP4106
APPLICATIONS INFORMATION
The NUP4106 is a low capacitance TVS diode array
Option 2
designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the NUP4106 offers surge rated, low capacitance
steering diodes and a TVS diode integrated in a single
package (SO−8). If a transient condition occurs, the steering
diodes will drive the transient to the positive rail of the
power supply or to ground. The TVS device protects the
power line against overvoltage conditions avoiding damage
to the power supply and other downstream components.
Protection of four data lines with bias and power supply
isolation resistor.
I/O 1
I/O 2
V
CC
1
8
10 K
2
3
4
7
6
5
I/O 3
I/O 4
NUP4106 Configuration Options
The NUP4106 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or
Figure 4.
The NUP4106 can be isolated from the power supply by
connecting a series resistor between pins 2 and 3 and V
A 10 kW resistor is recommended for this application. This
will maintain a bias on the internal TVS and steering diodes,
reducing their capacitance.
.
CC
V
CC
+ Vf). The diodes will force the transient current to
bypass the sensitive circuit.
Data lines are connected at pins 1, 4, 6 and 7. The negative
reference is connected at pins 5 and 8. These pins must be
connected directly to ground using a ground plane to
minimize the PCB’s ground inductance. It is very important
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
Option 3
Protection of four data lines using the internal TVS diode
as reference.
I/O 1
I/O 2
Option 1
Protection of four data lines and the power supply using
1
2
3
4
8
7
V
as reference.
CC
NC
NC
I/O 1
I/O 2
6
5
1
2
3
4
8
7
I/O 3
I/O 4
V
CC
Figure 5.
6
5
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal TVS can be used as the reference. For
these applications, pins 2 and 3 are not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the TVS plus one diode drop (Vc=Vf + VTVS).
I/O 3
I/O 4
Figure 3.
For this configuration, connect pins 2 and 3 directly to the
positive supply rail (V ). The data lines are referenced to
CC
the supply voltage. The internal TVS diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
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3
NUP4106
ESD Protection of Power Supply Lines
L diESD/dt factor. A relatively small trace inductance can result
in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board layout.
Taking care to minimize the effects of parasitic inductance
will provide significant benefits in transient immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD events
across datalines and the supply rail. Discrete diodes with good
transient power capability will have larger die and therefore
higher capacitance. This capacitance becomes problematic as
transmission frequencies increase. Reducing capacitance
generally requires reducing die size. These small die will have
higher forward voltage characteristics at typical ESD
transient current levels. This voltage combined with the
smaller die can result in device failure.
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes reduces
their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
Power
Supply
I
ESDpos
V
CC
I
ESDpos
D1
D2
Protected
Device
I
Data Line
ESDneg
VF + V
CC
I
ESDneg
The ON Semiconductor NUP4106 was developed to
overcome the disadvantages encountered when using discrete
diodes for ESD protection. This device integrates a TVS
diode within a network of steering diodes.
−VF
Figure 6.
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a negative
ESD condition occurs. For slower transient conditions, this
system may be approximated as follows:
D1
D3
D5
D7
For positive pulse conditions:
D2
D4
D6
D8
Vc = V + Vf
CC
D1
For negative pulse conditions:
Vc = −Vf
D2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect of
parasitic inductance must be considered. A pictorial
representation of this is shown below.
0
Figure 8. NUP4106 Equivalent Circuit
During an ESD condition, the ESD current will be driven
to ground through the TVS diode as shown below.
Power
Supply
I
ESDpos
Power
Supply
V
CC
I
ESDpos
V
D1
D2
CC
I
Protected
Device
ESDneg
I
ESDpos
D1
D2
Data Line
Protected
Device
V
I
= V + Vf + (L diESD/dt)
CC
C
Data Line
ESDneg
V
C
= −Vf − (L diESD/dt)
Figure 7.
Figure 9.
An approximation of the clamping voltage for these fast
transients would be:
The resulting clamping voltage on the protected IC will
be:
For positive pulse conditions:
Vc = VFD1 + VTVS.
Vc = V + Vf + (L diESD/dt)
CC
The clamping voltage of the TVS diode is provided in
Figure 2 and depends on the magnitude of the ESD current.
The steering diodes are fast switching devices with unique
forward voltage and low capacitance characteristics.
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
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4
NUP4106
TYPICAL APPLICATIONS
UPSTREAM
USB PORT
V
BUS
V
BUS
V
BUS
D+
D−
V
D+
BUS
R
R
T
DOWNSTREAM
USB PORT
T
D−
V
BUS
V
BUS
USB
Controller
NUP4106
GND
GND
C
C
T
T
V
BUS
V
BUS
NUP2201MR6
R
R
T
DOWNSTREAM
USB PORT
D+
T
D−
GND
C
C
T
T
Figure 10. ESD Protection for USB Port
RJ45
Connector
TX+
TX+
TX−
TX−
Coupling
PHY
Ethernet
(10/100)
Transformers
RX+
RX+
RX−
RX−
NUP4106
V
CC
GND
N/C
N/C
Figure 11. Protection for Ethernet 10/100 (Differential Mode)
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5
NUP4106
R1
RTIP
R3
R2
RRING
T1
V
CC
T1/E1
TRANSCEIVER
NUP4106
R4
R5
TTIP
TRING
T2
Figure 12. TI/E1 Interface Protection
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6
NUP4106
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NUP4106/D
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