NVD360N65S3T4G [ONSEMI]
Single N-Channel Power MOSFET SUPERFET® III, Easy Drive, 650 V , 10 A, 360 mΩ, DPAK;型号: | NVD360N65S3T4G |
厂家: | ONSEMI |
描述: | Single N-Channel Power MOSFET SUPERFET® III, Easy Drive, 650 V , 10 A, 360 mΩ, DPAK |
文件: | 总10页 (文件大小:314K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
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associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
MOSFET – Power, N-Channel,
SUPERFET) III, Easy Drive
650 V, 360 mW, 10 A
NVD360N65S3
Features
• Ultra Low Gate Charge & Low Effective Output Capacitance
www.onsemi.com
• Lower FOM (R
x Q
& R
x E
)
DS(on) max.
g typ.
DS(on) max.
OSS
• 100% Avalanche Tested
• AEC−Q101 Qualified and PPAP Capable
V
R
MAX
I MAX
D
DSS
DS(ON)
• These Devices are Pb−Free and are RoHS Compliant
650 V
360 mW @ 10 V
10 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Parameter
Drain−to−Source Voltage
Symbol
Value
650
30
Unit
V
D
V
DSS
V
GSS
V
GSS
Gate−to−Source Voltage
Gate−to−Source Voltage
− DC
V
− AC (f > 1 Hz)
30
V
G
Drain Current
− Continuous (T = 25°C)
I
I
10
A
C
D
S
Drain Current
− Continuous (T = 100°C)
6
A
C
D
POWER MOSFET
Drain Current
− Pulsed (Note 3)
I
25
A
DM
Power Dissipation
Power Dissipation
(T = 25°C)
P
P
83
W
C
D
4
− Derate Above 25°C
0.67
W/°C
°C
D
Operating Junction and Storage Temperature
Range
T , T
−55 to
+150
J
STG
2
1
3
Single Pulsed Avalanche Energy (Note 4)
Repetitive Avalanche Energy (Note 3)
MOSFET dv/dt
E
E
40
0.83
100
20
mJ
mJ
DPAK
CASE 369C
AS
AR
dv/dt
dv/dt
V/ns
V/ns
°C
MARKING DIAGRAM
Peak Diode Recovery dv/dt (Note 5)
Max. Lead Temperature for Soldering Purposes
(1/8″ from case for 5 s)
T
300
L
AYWW
V36
0N65S3
THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
A
Y
WW
= Assembly Location
= Year
= Work Week
Thermal Resistance, Junction−to−Case,
Max. (Notes 1, 2)
R
1.5
°C/W
q
JC
V360N65S3 = Specific Device Code
Thermal Resistance, Junction−to−Ambient,
Max. (Notes 1, 2, 6)
R
52
q
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
†
Device
NVD360N65S3
Package
Shipping
1. The entire application environment impacts the thermal resistance values shown.
They are not constants and are only valid for the particular conditions noted.
2. Assembled to an infinite heatsink with perfect heat transfer from the case
(assumes 0 K/W thermal interface).
DPAK3
(Pb−Free)
2500 / Tape &
Reel
3. Repetitive rating: pulse−width limited by maximum junction temperature.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
4. I = 2.1 A, R = 25 W, starting T = 25°C.
AS
G
J
5. I = 5 A, di/dt ≤ 200 A/ms, V ≤ 400 V, starting T = 25°C.
SD
DD
J
2
6. Device on 1 in pad 2 oz copper pad on 1.5 x 1.5 in. board of FR−4 material.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
December, 2020 − Rev. 0
NVD360N65S3/D
NVD360N65S3
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
BV
BV
V
= 0 V, I = 1 mA, T = 25°C
650
700
V
V
DSS
GS
D
J
V
GS
= 0 V, I = 1 mA, T = 150°C
D J
DSS
Breakdown Voltage Temperature
Coefficient
DBV
/
I
D
= 1 mA, Referenced to 25_C
650
mV/_C
DSS
J
DT
Zero Gate Voltage Drain Current
I
V
GS
= 0 V, V = 650 V
1
mA
DSS
DS
V
= 520 V, T = 125_C
0.33
DS
C
Gate−to−Body Leakage Current
ON CHARACTERISTICS
Gate Threshold Voltage
I
V
=
30 V, V = 0 V
100
4.5
360
nA
GSS
GS
DS
V
GS(th)
V
V
= V , I = 0.2 mA
2.5
V
mV/_C
mW
S
GS
DS
D
Threshold Temperature Coefficient
Static Drain−to−Source On Resistance
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance
DV
/DT
= V , I = 0.2 mA
−8.8
314
6
GS(th)
J
GS
DS
D
R
V
V
= 10 V, I = 5 A
D
DS(on)
GS
DS
g
= 20 V, I = 5 A
D
FS
C
756
17.4
1.53
179
29.3
16.8
2.8
4.6
7
pF
iss
Output Capacitance
C
oss
V
= 0 V, V = 400 V, f = 1 MHz
DS
GS
Reverse Transfer Capacitance
Effective Output Capacitance
Energy Related Output Capacitance
Total Gate Charge at 10 V
Threshold Gate Charge
C
rss
oss(eff.)
C
V
V
= 0 V to 400 V, V = 0 V
pF
pF
nC
DS
GS
C
Q
= 0 V to 400 V, V = 0 V
GS
oss(er.)
G(TOT)
DS
Q
G(TH)
V
= 10 V, V = 400 V, I = 5 A
DS D
GS
(Note 7)
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
Equivalent Series Resistance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Q
GS
Q
GD
ESR
f = 1 MHz
1
W
t
13.6
9.44
33.9
11.2
ns
ns
ns
ns
d(on)
V
GS
= 10 V, V = 400 V,
DD
Turn-On Rise Time
t
r
I
D
= 5 A, R = 4.7 W
g
Turn-Off Delay Time
t
(Note 7)
d(off)
Turn-Off Fall Time
t
f
SOURCE−DRAIN DIODE CHARACTERISTICS
Maximum Continuous Source−to−
I
10
25
A
A
S
V
V
= 0 V
= 0 V
GS
Drain Diode Forward Current
Maximum Pulsed Source−to−Drain
Diode Forward Current
I
SM
GS
Source−to−Drain Diode Forward
Voltage
V
SD
1.2
V
V
GS
= 0 V, I = 5 A
SD
Reverse Recovery Time
Charge Time
t
197
18
ns
rr
t
a
b
V
GS
= 0 V, dI /dt = 100 A/ms,
F
I
= 5 A
SD
Discharge Time
t
10
Reverse Recovery Charge
Q
2089
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Essentially independent of operating temperature typical characteristics.
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2
NVD360N65S3
TYPICAL CHARACTERISTICS
50
10
VGS
=
10.0V
V
GS
=10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
8.0V
7.0V
6.5V
6.0V
5.5V
10
1
1
*Notes:
1. 250
ms Pulse Test
= 25oC
250 ms Pulse Test
= 150°C
2. TC
T
C
0.1
0.1
0.2
1
10
20
0.1
1
10
V
DS
, Drain−Source Voltage (V)
VDS, Drain−Source Voltage[V]
Figure 1. On−Region Characteristics 255C
Figure 2. On−Region Characteristics 1505C
50
*Notes:
1. V = 20V
1400
1200
1000
800
600
400
200
0
DS
I
= 5 A
D
2. 250 s Pulse Test
m
10
1
150oC
T = 150°C
J
25oC
o
−55 C
T = 25°C
J
0.1
2
3
4
5
6
7
8
9
5.0
6.5
8.0
9.5
VGS, Gate−Source Voltage[V]
V
, GATE TO SOURCE VOLTAGE (V)
GS
Figure 4. RDS(on) vs. Gate Voltage
Figure 3. Transfer Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.6
0.5
0.4
0.3
0.2
0.1
*Note: TC = 25oC
*Notes:
1. V = 10V
GS
2. ID = 5A
VGS = 10V
VGS = 20V
−50
0
50
100
150
0
5
10
15
20
25
TJ, Junction Temperature [oC]
ID, Drain Current [A]
Figure 6. On−Resistance Variation
Figure 5. On−Resistance Variation vs.
vs. Temperature
Drain Current and Gate Voltage
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3
NVD360N65S3
TYPICAL CHARACTERISTICS
1E−04
1E−05
1E−06
1E−07
1E−08
100000
10000
1000
100
T = 150°C
J
Ciss
T = 125°C
J
Coss
T = 100°C
J
*Note:
1. V = 0V
GS
10
2. f = 1MHz
C
C
C
= C
+ C (C = shorted)
gs gd ds
iss
1E−09
1E−10
1
Crss
= C
+ C
gd
oss
rss
ds
gd
= C
0.1
0.1
1
10
100
1000
50
150
250
350
450
550
650
V
DS
, Reverse Voltage (V)
VDS, Drain−Source Voltage [V]
Figure 7. Drain−to−Source Leakage
Figure 8. Capacitance Characteristics
Current vs. Voltage
10
8
100
10
1
*Note: ID = 5A
*Notes:
1. VGS
= 0V
m
s Pulse Test
2. 250
VDS = 130V
150o
C
VDS = 400V
6
25oC
4
0.1
−55oC
2
0.01
0
0.001
0
5
10
15
20
0.0
0.5
1.0
1.5
Qg, Total Gate Charge [nC]
VSD, Body Diode Forward Voltage [V]
Figure 9. Gate Charge Characteristics
Figure 10. Body Diode Forward Voltage
Variation vs. Source Current and
Temperature
1.2
1.1
1.0
0.9
0.8
100
*Notes:
1. V = 0V
GS
2. ID = 10mA
ms
10
10
1
100 ms
1ms
10ms
DC
Operation in This Area
is Limited by R
DS(on)
*Notes:
1. TC = 25oC
0.1
2. T = 150o
3. Single Pulse
C
J
0.01
−50
0
50
100
150
1
10
100
1000
TJ, Junction Temperature [oC]
VDS, Drain−Source Voltage [V]
Figure 12. Breakdown Voltage Variation
vs. Temperature
Figure 11. Maximum Safe Operating Area
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4
NVD360N65S3
TYPICAL CHARACTERISTICS
5
4
3
2
1
0
1.2
I
= 0.2 mA
D
1
0.8
0.6
0
130
260
390
520
650
−80
−40
0
40
80
120
160
VDS, Drain to Source Voltage [V]
T , Ambient Temperature (5C)
A
Figure 13. EOSS vs. Drain to Source Voltage
Figure 14. Normalized Gate
Threshold Voltage vs. Temperature
2
DUTY CYCLE−DESCENDING ORDER
1
D = 0.5
0.2
0.1
P
DM
0.1
0.05
0.02
0.01
t 1
t
2
0.01
0.001
NOTES:
Z
(t) = r (t) x R
q
JC
q
JC
R
= 1.5 5C/W
q
JC
Peak T = P
x Z
q
(t) + T
JC C
SINGLE PULSE
J
DM
Duty Cycle, D = t / t
1
2
−3
−2
10−5
10−4
10
10
t, RECTANGULAR PULSE DURATION (sec)
10−1
100
101
102
Figure 15. Transient Thermal Response Curve
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5
NVD360N65S3
V
GS
R
Q
g
L
V
DS
Q
Q
gs
gd
V
GS
DUT
I
G
= Const.
Charge
Figure 16. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
t
d(off)
t
r
t
f
d(on)
t
on
t
off
Figure 17. Resistive Switching Test Circuit & Waveforms
L
2
1
2
EAS
+
@ LIAS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
DUT
V
DD
V
GS
V
DS
(t)
t
p
Time
t
p
Figure 18. Unclamped Inductive Switching Test Circuit & Waveforms
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6
NVD360N65S3
+
DUT
V
DS
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
D +
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 19. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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7
NVD360N65S3
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
A
D
E
C
A
b3
B
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
c2
4
2
L3
L4
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
b2 0.028 0.045
b3 0.180 0.215
MILLIMETERS
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
A
SIDE VIEW
b
b
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2 0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
PLANE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
C
0.020 BSC
L3 0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW
STYLE 1:
STYLE 2:
PIN 1. GATE
2. DRAIN
STYLE 3:
STYLE 4:
PIN 1. CATHODE
2. ANODE
STYLE 5:
PIN 1. GATE
PIN 1. BASE
PIN 1. ANODE
2. CATHODE
3. ANODE
2. COLLECTOR
2. ANODE
3. CATHODE
4. ANODE
3. EMITTER
3. SOURCE
4. DRAIN
3. GATE
4. ANODE
4. COLLECTOR
4. CATHODE
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
STYLE 8:
STYLE 9:
PIN 1. ANODE
2. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
PIN 1. GATE
PIN 1. N/C
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
3. ANODE
3. RESISTOR ADJUST
4. CATHODE
3. CATHODE
4. ANODE
4. COLLECTOR
4. CATHODE
SOLDERING FOOTPRINT*
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
NVD360N65S3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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