NVMFD5853NLT1G [ONSEMI]
Power MOSFET 40 V, 10 m, 34 A, Dual N.Channel Logic Level, Dual SO.8FL; 功率MOSFET的40 V，10 M +， 34 A，双N.Channel逻辑电平，双SO.8FL
| 型号： | NVMFD5853NLT1G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 40 V, 10 m, 34 A, Dual N.Channel Logic Level, Dual SO.8FL |
| 文件： | 总6页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFD5853NL,
NVMFD5853NLWF
Power MOSFET
40 V, 10 mW, 34 A, Dual N−Channel Logic
Level, Dual SO−8FL
Features
http://onsemi.com
• Small Footprint (5x6 mm) for Compact Designs
• Low R
to Minimize Conduction Losses
DS(on)
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
• Low Capacitance to Minimize Driver Losses
• NVMFD5853NLWF − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
• This is a Pb−Free Device
10 mW @ 10 V
15 mW @ 4.5 V
40 V
34 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Dual N−Channel
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
D1
D2
V
DSS
Gate−to−Source Voltage
V
"20
34
V
GS
Continuous Drain Cur-
T
= 25°C
I
A
mb
D
rent R
(Notes 1,
G1
G2
Y
J−mb
T = 100°C
mb
24
2, 3, 4)
Steady
State
Power Dissipation
T
mb
= 25°C
P
24
12
12
W
A
D
S1
S2
R
(Notes 1, 2, 3)
Y
J−mb
T
mb
= 100°C
Continuous Drain Cur-
T = 25°C
I
MARKING DIAGRAM
A
D
rent R
& 4)
(Notes 1, 3
q
JA
D1 D1
T = 100°C
A
8.5
Steady
State
1
S1
G1
S2
G2
D1
D1
D2
D2
Power Dissipation
(Notes 1 & 3)
T = 25°C
P
3.0
1.5
165
W
A
D
DFN8 5x6
(SO8FL)
CASE 506BT
5853xx
AYWZZ
R
q
JA
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
D2 D2
Operating Junction and Storage Temperature
T , T
−55 to
°C
J
stg
175
5853NL = Specific Device Code
for NVMFD5853NL
5853LW = Specific Device Code
for NVMFD5853NLWF
Source Current (Body Diode)
I
S
34
40
A
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (T = 25°C, V = 10 V, I = 28.3 A,
J
GS
L(pk)
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
L = 0.1 mH, R = 25 W)
G
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
†
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Device
Package
Shipping
Parameter
Symbol
Value
Unit
NVMFD5853NLT1G
DFN8
(Pb−Free)
1500 / Tape &
Reel
Junction−to−Mounting Board (top) − Steady
R
6.2
Y
J−mb
State (Notes 2, 3)
NVMFD5853NLWFT1G
DFN8
(Pb−Free)
1500 / Tape &
Reel
Junction−to−Ambient − Steady State (Note 3)
51
°C/W
R
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Junction−to−Ambient − Steady State (min foot-
q
JA
162
print)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second are higher but are dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2013 − Rev. 3
NVMFD5853NL/D
NVMFD5853NL, NVMFD5853NLWF
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
40
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
37.1
mV/°C
(BR)DSS
T = 25°C
1.0
100
100
Zero Gate Voltage Drain Current
I
mA
J
DSS
V
= 0 V,
GS
DS
V
= 40 V
= 0 V, V =
GS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
20 V
nA
GSS
DS
V
V
= V , I = 250 mA
1.4
2.4
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/T
5.9
mV/°C
GS(TH)
J
V
= 10 V, I = 15 A
8.4
12.7
22
10
15
Drain−to−Source On Resistance
R
mW
GS
D
DS(on)
V
GS
= 4.5 V, I = 15 A
D
Forward Transconductance
g
FS
V
= 5 V, I = 5 A
S
DS
D
CHARGES AND CAPACITANCES
Input Capacitance
C
C
1100
152
100
12.8
1.0
pF
nC
iss
Output Capacitance
V
= 0 V, f = 1.0 MHz, V = 25 V
DS
oss
GS
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
G(TH)
V
GS
= 4.5 V, V = 32 V,
DS
I
= 15 A
D
Q
3.7
GS
GD
Q
7.0
Q
V
= 10 V, V = 32 V, I = 15 A
23
nC
ns
G(TOT)
GS
DS
D
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
t
10
53
17
30
9.0
23
22
4.3
d(on)
t
r
V
= 4.5 V, V = 20 V,
DS
GS
D
I
= 15 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
t
t
t
d(off)
t
f
Turn−On Delay Time
Rise Time
ns
d(on)
t
r
V
= 10 V, V = 20 V,
GS
D
DS
I
= 15 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
d(off)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
T = 25°C
0.84
0.69
20
1.1
Forward Diode Voltage
V
V
J
SD
V
S
= 0 V,
GS
I
= 20 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
12
a
V
= 0 V, d /d = 100 A/ms,
IS t
GS
I
S
= 15 A
Discharge Time
8.1
b
Reverse Recovery Charge
Q
12.1
nC
RR
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5853NL, NVMFD5853NLWF
TYPICAL CHARACTERISTICS
70
70
60
50
40
30
20
10
0
T = 25°C
10 V
4.5 V
J
V
DS
≥ 10 V
60
50
40
30
20
10
0
4.2 V
7.5 V
3.8 V
3.4 V
3.0 V
T = 25°C
J
T = −55°C
J
T = 125°C
J
0.0
1.0
2.0
3.0
4.0
5.0
2.0
2.5
3.0
3.5
4.0
4.5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.030
0.025
0.020
0.015
0.010
0.005
0.0200
0.0175
0.0150
0.0125
0.0100
0.0075
0.0050
T = 25°C
I
= 15 A
J
D
T = 25°C
J
V
= 4.5 V
= 10 V
15
GS
V
GS
2
3
4
5
6
7
8
9
10
0
5
10
20
25
30
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
10000
1000
100
V
GS
= 0 V
I
V
= 15 A
D
T = 150°C
= 10 V
J
GS
T = 125°C
J
−50 −25
0
25
50
75
100 125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD5853NL, NVMFD5853NLWF
TYPICAL CHARACTERISTICS
1500
1250
1000
750
500
250
0
10
Q
T
V
= 0 V
GS
T = 25°C
J
C
iss
8
6
4
2
0
Q
Q
gd
gs
C
oss
T = 25°C
J
V
I
= 32 V
= 15 A
DS
C
rss
D
0
10
20
30
40
0
5
10
15
20
25
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
100
10
70
60
50
40
30
20
10
0
V
= 0 V
GS
V
= 20 V
= 15 A
= 4.5 V
DS
T = 25°C
J
I
D
V
GS
t
r
t
f
t
d(on)
t
d(off)
1
1
10
R , GATE RESISTANCE (W)
100
0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
10 ms
100 ms
V
= 10 V
GS
1 ms
Single Pulse
= 25°C
1
T
C
R
Limit
10 ms
dc
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NVMFD5853NL, NVMFD5853NLWF
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 50%
20%
10%
5%
2%
1
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
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5
NVMFD5853NL, NVMFD5853NLWF
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
E1
4X
h
PIN ONE
IDENTIFIER
MILLIMETERS
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
2
3
4
−−−
TOP VIEW
D
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
DETAIL B
D1
D2
D3
E
E1
E2
e
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
ALTERNATE
CONSTRUCTION
DETAIL A
A
5.70
3.90
6.10
4.40
C
SOLDERING FOOTPRINT*
4.15
1.27 BSC
SEATING
PLANE
NOTE 6
C
NOTE 4
4.56
SIDE VIEW
DETAIL A
G
h
K
K1
L
M
N
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.55
−−−
−−−
−−−
0.61
3.50
2.00
0.65
2X
2.08
2X
0.56
12
8X
0.75
_
D2
D3
−−−
−−−
0.71
3.75
2.20
4X L
K
e
1
4
4X
1.40
6.59
DETAIL B
4.84
2.30
3.70
4X
b1
N
E2
M
0.70
8
5
4X
G
b
8X
0.10
0.05
C
C
A
B
K1
4X
1.27
1.00
NOTE 3
PITCH
BOTTOM VIEW
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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NVMFD5853NL/D
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