NVMFS6B14N [ONSEMI]
Single N-Channel Power MOSFET;
| 型号： | NVMFS6B14N |
| 厂家： | 
ONSEMI |
| 描述： | Single N-Channel Power MOSFET |
| 文件： | 总6页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFS6B03N
Power MOSFET
100 V, 4.8 mW, 145 A, Single N−Channel
Features
• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
• Low Q and Capacitance to Minimize Driver Losses
DS(on)
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G
• NVMFS6B03NWF − Wettable Flank Option for Enhanced Optical
Inspection
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
100 V
4.8 mW @ 10 V
145 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
100
16
Unit
V
D (5,6)
V
DSS
Gate−to−Source Voltage
Continuous Drain Cur-
V
GS
V
T
= 25°C
I
D
145
A
C
G (4)
rent R
3)
(Notes 1, 2,
q
JC
T
C
= 100°C
102
Steady
State
Power Dissipation
(Notes 1, 2)
T
C
= 25°C
P
D
198
99
W
A
S (1,2,3)
N−CHANNEL MOSFET
R
q
JC
T
C
= 100°C
Continuous Drain Cur-
T = 25°C
A
I
D
20
rent R
3)
(Notes 1, 2,
q
JA
T = 100°C
A
14
Steady
State
MARKING
DIAGRAM
Power Dissipation
(Notes 1 & 2)
T = 25°C
A
P
D
3.9
2.0
520
W
R
q
D
JA
T = 100°C
A
1
S
S
S
G
D
D
Pulsed Drain Current
T = 25°C, t = 10 ms
A
I
DM
A
p
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
XXXXXX
AYWZZ
Operating Junction and Storage Temperature
T , T
−55 to
+ 175
°C
J
stg
D
Source Current (Body Diode)
I
S
160
180
A
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
Energy (T = 25°C, V = 50 V, V = 10 V,
J
DD
GS
I
= 60 A, L = 0.1 mH, R = 25 W)
L(pk)
G
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State
R
0.76
38
°C/W
q
JC
JA
Junction−to−Ambient − Steady State (Note 2)
R
q
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2015 − Rev. 0
NVMFS6B03N/D
NVMFS6B03N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
100
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
67.3
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
V
= 0 V,
= 80 V
T = 25°C
10
DSS
GS
DS
J
mA
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 16 V
nA
GSS
DS
GS
GS
V
V
= V , I = 250 mA
2.0
4.0
4.8
V
GS(TH)
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
J
−8.1
3.8
mV/°C
mW
GS(TH)
R
V
GS
= 10 V
I = 20 A
D
DS(on)
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
4200
760
31
ISS
Output Capacitance
C
V
V
= 0 V, f = 1 MHz, V = 50 V
pF
nC
OSS
RSS
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
C
Q
58
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
6.2
19
G(TH)
Q
= 10 V, V = 80 V; I = 50 A
GS
GD
GP
GS
DS
D
Q
V
17
5.4
1.0
V
Gate Resistance
R
T = 25°C
J
W
G
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
16
46
29
11
d(ON)
Rise Time
t
r
V
= 4.5 V, V = 80 V,
DS
GS
ns
V
I
D
= 50 A, R = 1.0 W
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
= 0 V,
= 50 A
T = 25°C
0.9
0.8
67
1.2
SD
GS
J
I
S
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
35
ns
a
V
= 0 V, dIS/dt = 100 A/ms,
GS
I
S
= 25 A
Discharge Time
t
b
31
Reverse Recovery Charge
Q
120
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS6B03N
TYPICAL CHARACTERISTICS
140
120
100
80
140
V
GS
= 6 V to 10 V
120
100
80
V
DS
≤ 10 V
5.5 V
5.0 V
60
60
40
40
T = 125°C
J
4.5 V
4.0 V
T = 25°C
20
0
20
0
J
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
11
10
9
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
T = 25°C
J
I
= 20 A
D
T = 25°C
J
V
= 6.0 V
GS
8
7
6
5
V
= 10 V
30
GS
4
3
3.5
3.0
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10
, GATE VOLTAGE (V)
10
15
20
25
35
40
45
50
V
GS
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100K
10K
1K
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
I
V
= 20 A
D
T = 150°C
J
= 10 V
GS
T = 125°C
J
100
T = 25°C
J
10
1
0.6
0.4
−50 −25
0
25
50
75
100 125 150 175
10 20
30
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
40
50
60
70
80
90 100
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFS6B03N
TYPICAL CHARACTERISTICS
10,000
1000
100
12
10
C
iss
Q
Q
T
C
oss
C
rss
8
Q
gd
gs
6
4
V
GS
= 0 V
10
1
T = 25°C
f = 1 MHz
T = 25°C
DS
J
J
V
2
0
= 50 V
I
D
= 50 A
5
1
10
, DRAIN−TO−SOURCE VOLTAGE (V)
100
0
10 15 20 25 30 35 40 45 50 55 60
V
DS
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
200
180
160
140
120
100
80
1000
100
V
= 50 V
= 50 A
= 10 V
DS
t
T = 25°C
J
d(off)
I
D
V
GS
t
d(on)
t
r
10
1
t
f
60
40
20
0
1
10
R , GATE RESISTANCE (W)
100
0.3 0.4 0.5 0.6
0.7
0.8 0.9 1.0 1.1 1.2
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
V
≤ 10 V
GS
Single Pulse
T
C
= 25°C
100
10
1
500 ms
1 ms
10 ms
R
Limit
0.1
DS(on)
Thermal Limit
Package Limit
0.01
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NVMFS6B03N
TYPICAL CHARACTERISTICS
140
120
100
80
100
25°C
10
100°C
60
40
20
0
1
0
20
40
60
80
100
120
140
100E−6
1E−3
T , TIME IN AVALANCHE (sec)
AV
10E−3
I , DRAIN CURRENT (A)
D
Figure 12. GFS vs. ID
Figure 13. IPEAK vs. TAV
100
50% Duty Cycle
20%
10%
5%
2%
1%
10
1
0.1
2
NTMFS6B03N, 650 mm , 2 oz, Cu Single Layer Pad
Single Pulse
0.01
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 14. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFS6B03NT1G
6B03N
DFN5
(Pb−Free)
1500 / Tape & Reel
1500 / Tape & Reel
5000 / Tape & Reel
5000 / Tape & Reel
NVMFS6B03NWFT1G
NVMFS6B03NT3G
6B03WF
6B03
DFN5
(Pb−Free, Wettable Flanks)
DFN5
(Pb−Free)
NVMFS6B03NWFT3G
6B03WF
DFN5
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS6B03N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2 X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
RECOMMENDED
SOLDERING FOOTPRINT*
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
2X
SIDE VIEW
DETAIL A
0.495
4.560
2X
5. DRAIN
1.530
8X b
A B
0.10
0.05
C
c
e/2
e
L
3.200
1
4
4.530
K
1.330
2X
E2
0.905
PIN 5
(EXPOSED PAD)
M
L1
1
0.965
4X
D2
BOTTOM VIEW
1.000
G
1.270
PITCH
4X
0.750
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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PUBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
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NVMFS6B03N/D
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