SN74LS169N [ONSEMI]

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS; BCD DECADE /模数16二进制同步双向计数器


型号：	SN74LS169N
厂家：	ONSEMI
描述：	BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS BCD DECADE /模数16二进制同步双向计数器计数器触发器逻辑集成电路光电二极管 CD
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SN54/74LS168

SN54/74LS169

BCD DECADE/MODULO

16 BINARY SYNCHRONOUS

BI-DIRECTIONAL COUNTERS

BCD DECADE/MODULO

16 BINARY SYNCHRONOUS

BI-DIRECTIONAL COUNTERS

The SN54/74LS168 and SN54/74LS169 are fully synchronous 4-stage

up/down counters featuring a preset capability for programmable operation,

carry lookahead for easy cascading and a U/D input to control the direction

of counting. The SN54/74LS168 counts in a BCD decade (8, 4, 2, 1)

sequence, while the SN54/74LS169 operates in a Modulo 16 binary

sequence. All state changes, whether in counting or parallel loading, are

initiated by the LOW-to-HIGH transition of the clock.

LOW POWER SCHOTTKY

• Low Power Dissipation 100 mW Typical

• High-Speed Count Frequency 30 MHz Typical

• Fully Synchronous Operation

• Full Carry Lookahead for Easy Cascading

• Single Up/Down Control Input

J SUFFIX

CERAMIC

CASE 620-09

• Positive Edge-Trigger Operation

• Input Clamp Diodes Limit High-Speed Termination Effects

N SUFFIX

PLASTIC

CASE 648-08

CONNECTION DIAGRAM DIP (TOP VIEW)

CET

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

D SUFFIX

SOIC

CASE 751B-03

ORDERING INFORMATION

U/D

CEP GND

SN54LSXXXJ

Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

PIN NAMES

LOADING (Note a)

HIGH

LOW

CEP

CET

U/D

Count Enable Parallel (Active LOW) Input

Count Enable Trickle (Active LOW) Input

Clock Pulse (Active positive going edge) Input

Parallel Enable (Active LOW) Input

Up-Down Count Control Input

Parallel Data Inputs

Flip-Flop Outputs

Terminal Count (Active LOW) Output

0.5 U.L.

1.0 U.L.

0.5 U.L.

0.25 U.L.

0.5 U.L.

0.25 U.L.

LOGIC SYMBOL

U/D

P –P

Q –Q

10 U.L. 5 (2.5) U.L.

CEP

CET

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. Temperature Ranges.

2 3

14 13 12 11

= PIN 16

GND = PIN 8

FAST AND LS TTL DATA

5-1

SN54/74LS168 • SN54/74LS169

STATE DIAGRAMS

SN54/74LS168

UP/DOWN DECADE COUNTER

SN54/74LS169

Count Up

Count Down

SN54/74LS168

UP: TC = Q

DOWN: TC = Q

SN54/74LS169

UP: TC = Q

DOWN: TC = Q

(U/D)

LOGIC DIAGRAMS

SN54/74LS168

CEP

CET

U/D

FAST AND LS TTL DATA

5-2

SN54/74LS168 • SN54/74LS169

LOGIC DIAGRAMS (continued)

SN54/74LS169

CEP

CET

U/D

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

Supply Voltage

4.5

4.75

5.0

5.5

5.25

Operating Ambient Temperature Range

–55

125

°C

Output Current — High

Output Current — Low

54, 74

–0.4

4.0

8.0

FAST AND LS TTL DATA

5-3

SN54/74LS168 • SN54/74LS169

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Min

Typ

Max

Symbol

Parameter

Input HIGH Voltage

Unit

Test Conditions

Guaranteed Input HIGH Voltage for

All Inputs

2.0

0.7

0.8

Guaranteed Input LOW Voltage for

All Inputs

Input LOW Voltage

Input Clamp Diode Voltage

Output HIGH Voltage

–0.65

3.5

–1.5

= MIN, I = –18 mA

2.5

2.7

= MIN, I

= MAX, V = V

or V per Truth Table

3.5

= V

= V or V

MIN,

54, 74

0.25

0.35

0.4

0.5

= 4.0 mA

= 8.0 mA

Output LOW Voltage

per Truth Table

Input HIGH Current

Other Inputs

CET Input

µA

= MAX, V = 2.7 V

Other Input

CET Input

0.1

0.2

= MAX, V = 7.0 V

Input LOW Current

Other Input

CET Input

–0.4

–0.8

= MAX, V = 0.4 V

Short Circuit Current (Note 1)

Power Supply Current

–20

–100

= MAX

Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.

FUNCTIONAL DESCRIPTION

The SN54/74LS168 and SN54/74LS169 use edge-

triggered D-type flip-flops that have no constraints on

changing the control or data input signals in either state of the

Clock. The only requirement is that the various inputs attain

thedesiredstateatleastaset-uptimebeforetherisingedgeof

the clock and remain valid for the recommended hold time

thereafter.

The Terminal Count (TC) output is normally HIGH and goes

LOW, providedthatCETisLOW, whenacounterreacheszero

in the COUNT DOWN mode or reaches 15 (9 for the

SN54/74LS168) in the COUNT UP mode. The TC output state

is not a function of the Count Enable Parallel (CEP) input level.

The TC output of the SN54/74LS168 decade counter can also

be LOW in the illegal states 11, 13 and 15, which can occur

when power is turned on or via parallel loading. If illegal state

occurs, the SN54/74LS168 will return to the legitimate

sequence within two counts. Since the TC signal is derived by

decoding the flip-flop states, there exists the possibility of

decoding spikes on TC. For this reason the use of TC as a

clock signal is not recommended.

The parallel load operation takes precedence over the other

operations, as indicated in the Mode Select Table. When PE is

LOW, the data on the P –P inputs enters the flip-flops on the

next rising edge of the Clock. In order for counting to occur,

both CEP and CET must be LOW and PE must be HIGH. The

U/D input then determines the direction of counting.

MODE SELECT TABLE

CEP

CET

U/D

Action on Rising Clock Edge

Load (Pn → Qn)

Count Up (increment)

Count Down (decrement)

No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

FAST AND LS TTL DATA

5-4

SN54/74LS168 • SN54/74LS169

AC CHARACTERISTICS (T = 25°C, V

= 5.0 V)

Limits

Typ

Symbol

Parameter

Unit

Test Conditions

Min

Max

Maximum Clock Frequency

MHz

MAX

Propagation Delay,

Clock to TC

PLH

PHL

Propagation Delay,

Clock to any Q

PLH

PHL

= 5.0 V

= 15 pF

Propagation Delay,

CET to TC

PLH

PHL

Propagation Delay,

U/D to TC

PLH

PHL

AC SETUP REQUIREMENTS (T = 25°C)

Limits

Typ

Symbol

Parameter

Clock Pulse Width

Unit

Test Conditions

Min

Max

Setup Time,

Data or Enable

Setup Time

= 5.0 V

Setup Time

U/D

Hold Time

Any Input

FAST AND LS TTL DATA

5-5

SN54/74LS168 • SN54/74LS169

AC WAVEFORMS

1/f

max

1.3 V

CET

1.3 V

PLH

PHL

PLH

1.3 V

PHL

1.3 V

Q OR TC

1.3 V

Figure 1. Clock to Output Delays,

Count Frequency, and Clock Pulse Width

Figure 2. Count Enable Trickle Input

To Terminal Count Output Delays

1.3 V

t (L)

t (H)

t (H) = 0

t (L) = 0

1.3 V

•

• P 1.3 V

1.3 V

PLH

PHL

1.3 V

•

Figure 3. Clock to Terminal Delays

Figure 4. Setup Time (t ) and Hold (t )

for Parallel Data Inputs

1.3 V

t (H)

s(L)

t (L) = 0

t (H) = 0

SR OR PE 1.3 V

1.3 V

U/D

1.3 V

PLH

PHL

1.3 V

t (H)

t (L)

t (H) = 0

t (L) = 0

Figure 6. Up-Down Input to

Terminal Count Output Delays

CEP 1.3 V

t (H)

1.3 V

t (L)

t (H) = 0

t (L) = 0

CET 1.3 V

1.3 V

The shaded areas indicate when the

input is permitted to change for

predictable output performance.

Figure 5. Setup Time and Hold Time for

Count Enable and Parallel Enable Inputs,

and Up-Down Control Inputs

FAST AND LS TTL DATA

5-6

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