SN74LS377 [ONSEMI]
LOW POWER SCHOTTKY; 小功率肖特基
ONSEMI 
The SN74LS377 is an 8-bit register built using advanced Low
Power Schottky technology. This register consists of eight D-type
flip-flops with a buffered common clock and a buffered common
clock enable.
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• 8-Bit High Speed Parallel Registers
LOW
POWER
SCHOTTKY
• Positive Edge-Triggered D-Type Flip Flops
• Fully Buffered Common Clock and Enable Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
20
T
A
Operating Ambient
Temperature Range
°C
1
I
Output Current – High
Output Current – Low
–0.4
8.0
mA
mA
OH
PLASTIC
N SUFFIX
CASE 738
I
OL
20
1
SOIC
DW SUFFIX
CASE 751D
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS377N
1440 Units/Box
SN74LS377DW
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS377/D
SN74LS377
CONNECTION DIAGRAM DIP (TOP VIEW)
V
Q
D
D
Q
Q
D
D
Q
4
CP
11
CC
7
7
6
6
5
5
4
20 19 18 17 16 15 14 13 12
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
9
10
7
E
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND
(Note a)
LOADING
HIGH
LOW
PIN NAMES
E
Enable (Active LOW) Input
Data Inputs
Clock (Active HIGH Going Edge) Input
True Outputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
D – D
0
3
CP
Q – Q
Q – Q
0
3
Complemented Outputs
5 U.L.
0
3
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
E
ENABLE
1
CP
CLOCK
11
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
2
5
6
9
12
15
16
19
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2
SN74LS377
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Unit
Test Conditions
Min
Typ
Max
Guaranteed Input HIGH Voltage for
All Inputs
V
V
Input HIGH Voltage
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
Input LOW Voltage
V
IL
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
2.7
= MIN, I = MAX, V = V
OH IN IH
OH
CC
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
0.5
V
V
I
= 4.0 mA
= 8.0 mA
CC
OL
OL
V
Output LOW Voltage
Input HIGH Current
= V or V
IH
OL
IN
IL
I
per Truth Table
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
28
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
OS
CC
= MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, I is measured after a momentary GND, then 4.5 V is applied to clock.
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Symbol
Parameter
Min
Max
Unit
Test Conditions
= 5.0 V
f
Maximum Clock Frequency
30
40
MHz
MAX
V
CC
t
t
Propagation Delay,
Clock to Output
17
18
27
27
PLH
PHL
C = 15 pF
L
ns
AC SETUP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Symbol
Parameter
Min
20
Max
Unit
ns
Test Conditions
t
Any Pulse Width
W
s
t
t
t
Data Setup Time
20
ns
Inactive — State
Active — State
10
ns
V
CC
= 5.0 V
Enable Setup
Time
s
25
ns
Any Hold Time
5.0
ns
h
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
HOLD TIME (t ) — is defined as the minimum time
h
following the clock transition from LOW-to-HIGH that the
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3
SN74LS377
TRUTH TABLE
E
CP
D
Q
Q
n
n
n
H
X
No
No
Change Change
L
L
H
L
H
L
L
H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
AC WAVEFORM
1/f
max
t
W
1.3 V
1.3 V
CP
t
t
s(L)
h(H)
s(H)
t
t
h(L)
1.3 V
1.3 V
D OR E
Q
*
t
t
PHL
PLH
1.3 V
1.3 V
*The shaded areas indicate when the input is permitted to
change for predictable output performance.
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4
SN74LS377
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
1.27 BSC
M
0.070
1.27
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
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5
SN74LS377
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
20
11
10
E
1
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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6
SN74LS377
Notes
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7
SN74LS377
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SN74LS377/D
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