STK541UC62A-E [ONSEMI]
Intelligent Power Module (IPM), 600 V, 10 A;
| 型号： | STK541UC62A-E |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), 600 V, 10 A |
| 文件： | 总15页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK541UC62A-E
Advance Information
Intelligent Power Module
(IPM) 600ꢀV, 10 A
The STK541UC62A−E is a fully−integrated inverter power stage
consisting of a high−voltage driver, six IGBT’s and a thermistor,
suitable for driving permanent magnet synchronous (PMSM) motors,
brushless−DC (BLDC) motors and AC asynchronous motors. The
IGBT’s are configured in a 3−phase bridge.
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The power stage has a full range of protection functions including
cross−conduction protection, external shutdown and under−voltage
lockout functions. Output stage uses IGBT/FRD technology and
implements Under Voltage Protection (UVP) and Over Current
Protection with a Fault Detection output flag. Internal Boost diodes
are provided for high side gate boost drive.
SIP23 62x21.8
CASE 127VB
Features
MARKING DIAGRAM
• Three−Phase 10 A / 600 V IGBT Module With Integrated Drivers
• Typical Values (Upper Side at 10 A): V (sat) = 1.4 V, V = 1.3 V
• 62.0 mm x 21.8 mm Single In−line Package
• Cross−Conduction Protection
• Integrated Bootstrap Diodes and Resistors
• These Devices are Pb−Free and are RoHS Compliant
CE
F
STK541UC62A = Specific Device Code
Certification
A
B
C
D
= Year
= Month
= Production Plant
= Ordering Number
• UL1557 (File Number: E339285)
Typical Applications
Device Marking in on Package Underside
• Industrial Pumps
• Industrial Fans
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 13 of this data sheet.
• Industrial Automation
• Heat Pumps, Home Appliances
HS1
HS2
HS3
HS1
HIN1
IC Driver
LS1
LIN1
Pre driver
HS2
HIN2
+
LS2
LIN2
Level Shifter
LS1
LS2
LS3
HS3
HIN3
with
protection
Circuits
LS3
LIN3
Figure 1. Functional Diagram
1
© Semiconductor Components Industries, LLC, 2017
Publication Order Number:
December, 2018 − Rev. 1
STK541UC62A−E/D
STK541UC62A−E
STK541UC62A
VB1 (7)
VCC
+
+
+
CB1
CB2
CB3
P (10)
U,VS1 (8)
VB2 (4)
CS1
CS2
+
V,V2 (5)
VB3 (1)
N (12)
W,VS3 (2)
HIN1 (15)
HIN2 (16)
HIN3 (17)
LIN1 (18)
LIN2 (19)
LIN3 (20)
U, VS1 (8)
V, VS2 (5)
W, VS3 (2)
Control
Circuit
(5V)
ISO (16)
VTH (13)
Motor
FLTEN (21)
RTH
RP
VD4=15V
VDD (14)
VSS (23)
CD4
Figure 2. Application Schematic
Function Description
4. The “ISO” terminal (Pin 22) is current monitor
terminal. When the pull−down resister is used,
please select it more than 5.6 kW
5. As protection of IPM to the unusual current by a
short circuit etc. it recommends installing shunt
resistors and an over−current protection circuit
outside. Moreover, for safety, a fuse on Vcc line is
recommended.
6. Disconnection of terminals U, V, or W during
normal motor operation will cause damage to IPM,
use caution with this connection.
7. When input pulse width is less than 1 ms, an output
may not react to the pulse. (Both ON signal and
OFF signal)
1. It is essential that wiring length between terminals
in the snubber circuit be kept as short as possible
to reduce the effect of surge voltages.
Recommended value of “CS” is in the range of 0.1
to 10 mF.
2. The “FLTEN” terminal (Pin 21) is I/O terminal;
Fault output / Enable input. It is used to indicate an
internal fault condition of the module and also can
be used to disable the module operation.
3. Inside the IPM, a thermistor used as the
temperature monitor for internal substrate is
connected between VSS terminal and TH terminal
therefore, an external pull up resistor connected
between the TH terminal and an external power
supply should be used.
This data shows the example of the application circuit,
does not guarantee a design as the mass production set.
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2
STK541UC62A−E
P (10)
VB3 (1)
W,VS3 (2)
VB2 (4)
V,VS2 (5)
VB1 (7)
U,VS1 (8)
BD
BD BD
RB
Shunt
Resistor
N (12)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1 (15)
HIN2 (16)
HIN3 (17)
LIN1 (18)
LIN2 (19)
LIN3 (20)
Logic
Logic
Logic
Thermistor
VTH (13)
ISO (22)
FLTEN (21)
Latch
Latch time is about 9ms.
(Automatic Reset)
Over−Current
VDD (14)
VSS (23)
VDD−UnderVoltage
Figure 3. Simplified Block Diagram
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STK541UC62A−E
Table 1. PIN FUNCTION DESCRIPTION
Pin #
Label
Description
1
VB3
W, VS3
VB2
High Side Floating Supply Voltage 3
Output 3 − High Side Floating Supply Offset Voltage
High Side Floating Supply Voltage 2
Output 2 − High Side Floating Supply Offset Voltage
High Side Floating Supply Voltage 1
Output 1 − High Side Floating Supply Offset Voltage
Positive Bus Input Voltage
2
4
5
V, VS2
VB1
7
8
U, VS1
P
10
12
N
Negative Bus Input Voltage
13
VTH
VDD
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
FLTEN
ISO
Temperature Feedback
14
+15 V Main Supply
15
Logic Input High Side Gate Driver − Phase U
Logic Input High Side Gate Driver − Phase V
Logic Input High Side Gate Driver − Phase W
Logic Input Low Side Gate Driver − Phase U
Logic Input Low Side Gate Driver − Phase V
Logic Input Low Side Gate Driver − Phase W
Fault output and Enable
16
17
18
19
20
21
22
Current monitor output
23
VSS
Negative Main Supply
1. Pins 3, 6, 9, 11 are not present.
Table 2. ABSOLUTE MAXIMUM RATINGS at T = 25_C, (Note 2)
C
Symbol
Parameter
Min
Max
Unit
Supply voltage
VCC
VCE
P to N, surge < 500 V (Notes 3)
P to U, V, W or U, V, W, to N
P,N,U,V,W terminal current
450
600
10
V
V
A
Collector−emitter voltage
Output current
Io
P,N,U,V,W terminal current,
5
20
20
A
A
V
Tc = 100_C
Output peak current
Iop
P,N,U,V,W terminal current, P.W. = 1ms
VB1 to U, VB2 to V, VB3 to W, VDD to
VSS (Notes 4)
Pre−driver voltage
VD1,2,3,4
Input signal voltage
VIN
VFLTEN
Pd
HIN1, 2, 3, LIN1, 2, 3
FLTEN terminal
−0.3 to 7
−0.3 to VDD
22
V
V
FLTEN terminal voltage
Maximum power dissipation
Junction temperature
Storage temperature
Operating case temperature
Tightening torque
IGBT per 1 channel
IGBT, FRD, Pre−Driver IC
W
Tj
150
_C
Tstg
Tc
−40 to +125
−40 to +100
0.9
_C
IPM case
_C
A screw part (Notes 5)
50 Hz sine wave AC 1 minute (Notes 6)
Nm
VRMS
Withstand voltage
Vis
2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. Surge voltage developed by the switching operation due to the wiring inductance between P and N terminal.
4. VD1=VB1 to U, VD2=VB2 to V, VD3=VB3 to W, VD4=VDD to VSS terminal voltage.
5. Flatness of the heat−sink should be less than −50 mm to +100 mm.
6. Test conditions : AC2500V, 1 second
7. Reference voltage is “VSS” terminal voltage unless otherwise specified.
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4
STK541UC62A−E
Table 3. RECOMMENDED OPERATING RANGES (at T = 25°C)
C
Characteristic
Symbol
Conditions
Min
0
Typ
280
15
15
−
Max
450
17.5
16.5
0.3
5.0
20
Unit
Supply voltage
V
CC
P to N
VB1 to U, VB2 to V, VB3 to W
V to V (Note 8)
DD
V
VD1, 2, 3
12.5
13.5
0
V
V
Pre−driver supply voltage
VD4
SS
ON−state input voltage
OFF−state input voltage
PWM frequency
VIN(ON)
VIN(OFF)
fPWM
DT
HIN1,HIN2,HIN3,
LIN1,LIN2,LIN3
V
3.0
1.0
2.0
1.0
0.6
−
kHz
ms
Dead time
Turn−off to turn−on (external)
ON and OFF
−
−
−
Allowable input pulse width
Package mounting torque
PWIN
−
ms
¡M3’ type screw
0.9
Nm
8. Pre−drive power supply (VD4 = 15 1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
Table 4. ELECTRICAL CHARACTERISTICS T = 25°C, VD1, VD2, VD3, VD4 = 15 V (Note 9)
C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Power output section
Collector−emitter leakage
current
V
CE
= 600 V
I
−
−
100
mA
CE
Bootstrap diode reverse current VR(BD) = 600 V
IR(BD)
−
−
−
−
−
−
−
−
−
−
−
−
100
2.3
2.6
−
mA
V
V
V
V
V
V
V
V
Upper side
1.4
1.7
1.3
1.6
1.3
1.6
1.2
1.5
−
Ic = 10 A, Tj = 25_C
Lower side (Note 9)
Upper side
Collector to emitter saturation
voltage
V
CE
(sat)
Ic = 5A, Tj = 100_C
Lower side (Note 9)
Upper side
−
2.2
2.5
−
IF = 10 A, Tj = 25_C
Diode forward voltage
Lower side (Note 9)
Upper side
VF
IF = 5 A, Tj = 100_C
Lower side (Note 9)
−
IGBT
qj−c(T)
qj−c(D)
5.5
6.5
Junction to case thermal
resistance
_C/W
FRD
−
Switching Character
t ON
t OFF
Eon
Eoff
Etot
Eon
Eoff
Etot
Erec
Trr
0.2
−
0.4
0.5
200
130
330
240
160
400
17
1.1
1.2
−
ms
ms
mJ
mJ
mJ
mJ
mJ
mJ
mJ
ns
Io = 10 A
Switching time
Inductive load
Turn−on switching loss
−
Ic=5 A, P = 300 V,
DD
Tc = 25_C
Turn−off switching loss
Total switching loss
V
= 15 V, L = 3.9 mH
−
−
−
−
Turn−on switching loss
Turn−off switching loss
Total switching loss
−
−
Ic = 5 A, P = 300 V,
DD
Tc = 100_C
V
= 15 V, L = 3.9 mH
−
−
−
−
Diode reverse recovery energy
Diode reverse recovery time
−
−
I = 5 A, P = 400 V, V = 15 V,
L = 0.5 mH, Tc = 100_C
F
DD
−
62
−
Reverse bias safe operating
area
Io = 20_, VCE = 450 V
RBSOA
SCSOA
Full Square
Short circuit safe operating area VCE = 400 V, Tc=100_C
Control (Pre−driver) section
4.0
−
−
ms
VD1,2,3 = 15 V
−
−
0.08
1.6
0.4
4.0
Pre−driver power dissipation
ID
mA
VD4 = 15 V
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STK541UC62A−E
Table 4. ELECTRICAL CHARACTERISTICS T = 25°C, VD1, VD2, VD3, VD4 = 15 V (Note 9)
C
High level Input voltage
Low level Input voltage
Vin H
Vin L
2.5
−
−
V
V
−
0.8
HIN1,HIN2,HIN3,
LIN1,LIN2,LIN3 to VSS
Input threshold voltage
hysteresis
Vinth(hys)
0.5
0.8
−
V
Logic 1 input leakage current
Logic 0 input leakage current
FLTEN terminal sink current
FLTEN clearance delay time
VIN = +3.3V
I
I
76
97
−
118
150
2.0
9.0
160
203
−
mA
mA
mA
ms
V
IN+
VIN = 0 V
IN−
FAULT:ON / VFLTEN = 0.1 V
From time fault condition clear
VEN rising
IoSD
FLTCLR
VEN+
VEN−
6.0
2.5
−
12.0
−
FLTEN Threshold
VEN falling
−
0.8
V
V
and V supply
V
V
CC
BS
CCUV+
BSUV+
10.5
10.3
11.1
11.7
11.5
V
V
undervoltage protection reset
V
CC
and V supply
V
V
BS
CCUV−
BSUV−
10.9
undervoltage protection set
V
and V supply
V
V
CC
BS
CCUVH
BSUVH
0.14
0.30
0.2
V
V
undervoltage hysteresis
Output level for current monitor Io = 10 A
ISO
0.33
0.36
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Reference voltage is “VSS” terminal voltage unless otherwise specified.
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STK541UC62A−E
APPLICATIONS INFORMATION
Input / Output Timing Chart
VBS undervoltage protection reset signal
OFF
HIN1,2,3
ON
LIN1,2,3
VDD
VDD undervoltage protection reset voltage
*2
VBS undervoltage protection reset voltage
*3
VB1,2,3
*4
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−IS−D−−o−p−e−r−ation current level−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
N terminal
(BUS line)
Current
FLTEN terminal
Voltage
(at pulled−up)
ON
*1
*1
Upper
U, V, W
OFF
Lower
U ,V, W
Automatically reset after protection
(typ.9ms)
Figure 4. Input/Output Timing Chart
NOTES:
1. Shows the prevention of shoot−thru via control logic, however, more dead time must be added to account for
switching delay externally.
2. When VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the
operation will resume immediately.
3. When the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off.
The outputs return to normal operation immediately after the upper side gate voltage rises.
4. In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation
resumes in typ. 9ms after the over current condition is removed.
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STK541UC62A−E
Table 5. LOGIC LEVEL TABLE
INPUT
OUTPUT
Low side IGBT
HIN
H
LIN
L
OCP
OFF
OFF
OFF
OFF
ON
High side IGBT
U,V,W
FLTEN
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
P
N
L
H
OFF
OFF
OFF
OFF
L
L
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
H
H
X
X
Table 6. THERMISTOR CHARACTERISTICS
Parameter
Symbol
Condition
Min
99
Typ
100
5.38
4250
−
Max
Unit
R
Tc = 25℃
101
5.66
4335
+125
kW
kW
K
25
Resistance
R
Tc = 100℃
5.12
4160
−40
100
B−Constant (25 to 50℃)
B
Temperature Range
°C
Case Temperature(Tc)−Thermal resistance(RTH)
10000
1000
100
10
min
typ
max
1
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Case temperature, Tc−degC
Figure 5. Thermistor Resistance versus Case Temperature
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STK541UC62A−E
Case Temperature(Tc)−TH terminal voltage(VTH)
6.0
5.0
4.0
3.0
2.0
1.0
0.0
min
typ
max
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Case temperature, Tc−degC
Figure 6. Thermistor Voltage versus Case Temperature Condition: Pull−up resistor = 4.7 kphm,
Pull−up voltage of TH = 5 V
Fault Output
Once activated by a fault condition the FAULT signal
The FLTEN terminal is an open drain output requiring a
pull−up resistor. If the pull−up voltage is 5 V, use a pull−up
resistor with a value of 6.8 kW or higher. If the pull−up
voltage is 15 V, use a pull−up resistor with a value of 20 kW
or higher. The FAULT output is triggered if there is a VDD
under voltage or an overcurrent condition.
The terminal has a function of enable output, this pin is
used to enable or shut down the built−in driver. If the voltage
on the FLTEN pin rises above the ENABLE ON−state
voltage, the output drivers are enabled. If the voltage on the
FLTEN pin falls below the ENABLE OFF−state voltage, the
drivers are disabled.
output returns to inactive (and is pulled high by the external
resistor) when the fault condition is over and the fault clear
time (FLTCLR) has passed. This implies that the system
microcontroller needs to disable all input signals to the
module by driving them low upon detection of a fault
condition. An additional fuse is recommended to protect
against system level or abnormal over−current fault
conditions.
Capacitors on High Voltage and VDD supplies
Both the high voltage and V
supplies require an
DD
electrolytic capacitor and an additional high frequency
capacitor.
Under Voltage Lockout Protection.
Minimum input pulse width
When input pulse width is less than 1.0 ms, an output may
not react to the pulse. (Both ON signal and OFF signal)
If VDD goes below the VDD supply under voltage
lockout falling threshold, the FAULT output is switched on.
The FAULT output stays on until VDD rises above the VDD
supply under voltage lockout rising threshold. After VDD
has risen above the threshold to enable normal operation, the
driver waits to receive an input signal on the LIN input
before enabling the driver for the HIN signal.
Calculation of bootstrap capacitor value
The bootstrap capacitor value CB is calculated using the
following approach. The following parameters influence the
choice of bootstrap capacitor:
• VBS : Bootstrap power supply.
15 V is recommended.
• QG : Total gate charge of IGBT at VBS = 15 V.
89nC
Overcurrent Protection
Over current protection is implemented by measuring the
voltage across a shunt resistor to negative supply terminal.
In case of an OCP fault the gate drivers are shut down
internally and the external Fault signal becomes active
(low).
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STK541UC62A−E
If the low side IGBT is held on for a long period of time
(more than one second for example), the bootstrap voltage
on the high side MOSFET will slowly discharge.
• UVLO : Falling threshold for UVLO.
Specified as 12 V.
• ID
: High side drive consumption current.
Specified as 400 mA
MAX
100
10
• t
: Maximum ON pulse width of high side
ONMAX
IGBT.
Capacitance calculation formula
1
CB = (QG + IDMAX * tONMAX) / (VBS − UVLO)
CB is recommended to be approximately 3 times the value
calculated above. The recommended value of CB is in the
range of 1 to 47 mF, however, the value needs to be verified
prior to production. When not using the bootstrap circuit,
each high side driver power supply requires an external
independent power supply.
0,1
0,01
0,1
1
10
tONMAX [ms]
100
1000
The internal bootstrap circuit uses a MOSFET. The turn
on time of this MOSFET is synchronized with the turn on of
the low side IGBT. The bootstrap capacitor is charged by
turning on the low side IGBT.
Figure 7. Bootstrap capacitance versus tONMAX
Table 7. MOUNTING INSTRUCTIONS
Item
Recommended Condition
Pitch
56.0 0.1 mm (Please refer to Package Outline Diagram)
Diameter : M3
Screw head types: pan head, truss head, binding head
Screw
Plane washer
Washer
The size is D : 7 mm, d : 3.2 mm and t : 0.5 mm JIS B 1256
Material: Aluminum or Copper
Warpage (the surface that contacts IPM) : −50 to +100 mm
Heat sink
Screw holes must be countersunk
No contamination on the heat sink surface that contacts IPM
Final tightening : 0.6 to 0.9 Nm
Torque
Grease
Temporary tightening : 20 to 30 % of final tightening
Silicone grease
Thickness : 100 to 200 mm
Uniformly apply silicone grease to whole back
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STK541UC62A−E
Figure 8. Module Mounting Details: Components; Washer Drawing; Need for Even
Spreading of Thermal Grease
• V (sat) (Test by pulse)
CE
• I
CE
ICE
U+
10
V+
10
W+
10
U−
V−
W−
M
1
A
VD3=15V
VD2=15V
VD1=15V
V4D=15V
M
N
8
5
2
2
4
8
5
2
12
12
12
VCE
6
7
U(DB) V(DB) W(DB)
8
7
4
1
M
N
14
23
23
23
N
23
U+, V+, W+ : High side phase
U−, V−, W− : Low side phase
Figure 9. Test Circuit for ICE
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STK541UC62A−E
• V (sat) (Test by pulse)
CE
M
1
VD3=15V
2
4
U+
10
V+
10
W+
10
U−
V−
W−
VD2=15V
VD1=15V
VD4=15V
M
N
8
5
2
5
7
V
VCE
(sat)
IC
8
5
2
12
18
12
19
12
8
m
15
16
17
14
m
N
Figure 10. Test Circuit for VCE (sat)
• V (Test by pulse)
F
M
U+
V+
10
W+
10
U−
V−
W−
M
N
10
8
8
5
2
V
IF
VF
5
2
12
12
12
N
Figure 11. Test Circuit for VCE (sat)
• ID
M
A
VD1
VD2
VD3
VD4
14
M
N
7
8
4
5
1
2
VD*
23
N
Figure 12. Test Circuit for ID
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STK541UC62A−E
• Switching time (The circuit is a representative example of the low side U phase)
10
8
1
VS3=15V
2
4
Input signal
(0 to 5V)
VS2=15V
VCC
5
7
VS1=15V
Input signal
VDD=15V
90%
8
18
14
Io
10%
12
23
A
tOFF
tON
Figure 13. Switching Time Test Circuit
Table 8. ORDERING INFORMATION
Device
Marking
STK541UC62A
Package
Shipping
8 Unit / Tube
SIP23 62x21.8
(Pb−Free)
STK541UC62A−E
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP23 56x21.8
CASE 127BV
ISSUE O
DATE 30 APR 2012
missing pin：3,6,9,11
56.0
R 1.7
9DF 00
S IP 1
23
1
not e1
2.0
2.0
+0 . 2
0.6
−0.05
3.2
22×2.0＝44.0
6.7
46.2
50.0
62.0
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DOCUMENT NUMBER:
DESCRIPTION:
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SIP23 56X21.8
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