STK544UC63K-E [ONSEMI]
Intelligent Power Module (IPM), 600 V, 10 A;
| 型号： | STK544UC63K-E |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), 600 V, 10 A 局域网 电动机控制 |
| 文件： | 总13页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK544UC63K-E
Intelligent Power Module
(IPM), 600 V, 10 A
The STK544UC63K−E is a fully-integrated inverter power stage
consisting of a high-voltage driver, six IGBT’s and a thermistor,
suitable for driving permanent magnet synchronous (PMSM) motors,
brushless-DC (BLDC) motors and AC asynchronous motors. The
IGBT’s are configured in a 3-phase bridge with separate emitter
connections for the lower legs for maximum flexibility in the choice of
control algorithm. The power stage has a full range of protection
functions including cross-conduction protection, external shutdown
and under-voltage lockout functions. An internal comparator and
reference connected to the over-current protection circuit allows the
designer to set the over-current protection level.
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Features
SIP23 62x21.8
CASE 127FC
• Three-phase 10 A/600 V IGBT Module with Integrated Drivers
• Built-in Under Voltage Protection
• Cross-conduction Protection
• ITRIP Input to Shut Down All IGBTs
MARKING DIAGRAM
• Integrated Bootstrap Diodes and Resistors
• Thermistor for Substrate Temperature Measurement
• UL1557 Certification (File Number: E339285)
• These Devices are Pb-Free and are RoHS Compliant
STK544UC63K
ZZZATYWW
STK544UC63K = Specific Device Code
Typical Applications
ZZZ
A
T
Y
WW
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
• Industrial Drives
• Industrial Pumps
• Industrial Fans
= Work Week
• Industrial Automation
Device marking is on package top side
ORDERING INFORMATION
Shipping
(Qty/Packing)
Device
STK544UC63K−E
Package
SIP23
80/Box
HIN(U)
LIN(U)
HIN(V)
LIN(V)
HIN(W)
LIN(W)
HS1
LS1
HS2
LS2
HS3
LS3
62x21.8FP−4
(Pb−Free)
HS1
LS1
HS2
LS2
HS3
LS3
Three channel
half−bridge
driver
with
protection
circuits
Figure 1. Functional Diagram
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May, 2019 − Rev. 0
STK544UC63K−E/D
STK544UC63K−E
STK544UC63K
VCC
P: 10
RC filtering for
HINx and LINx
not shown.
+
C1
CS
Recommended
in noisy
environments.
HV Ground
RSU
RSV
RSW
NU: 12
NV: 13
NW: 14
From HV
Power
Source
HIN(U): 15
HIN(V): 16
HIN(W): 17
LIN(U): 18
LIN(V): 19
LIN(W): 20
To current
senser
VB(U): 7
+
+
+
VS(U), U: 8
VB(V): 4
Controller
T/ITRIP: 21
Motor
RP
VDD = 15 V
from
external
regulator
VS(V), V: 5
VB(W): 1
VDD: 22
VSS: 23
CD4
+
VS(W), W: 2
LV Ground
Star connection to HV Ground
Figure 2. Application Schematic
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2
STK544UC63K−E
RBS
RBS
RBS
VB(U) (7)
VB(V) (4)
VB(W) (1)
BD BD BD
RBC
P (10)
VDD (22)
GND (23)
VS(W), W (2)
VS(V), V (5)
VS(U), U (8)
NU (12)
NV (13)
NW (14)
Level
Shifter
Level
Shifter
Level
Shifter
HIN(U) (15)
HIN(V) (16)
HIN(W) (17)
LIN(U) (18)
LIN(V) (19)
LIN(W) (20)
Logic
Logic
Logic
VDD
undervoltage
shutdown
VDD
Thermistor
T/ITRIP (21)
Over current
protection
Internal Voltage
reference
Figure 3. Simplified Block Diagram
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3
STK544UC63K−E
PIN DESCRIPTION
Pin No.
1
Name
Description
VB(W)
VS(W), W
VB(V)
VS(V), V
VB(U)
VS(U), U
P
High Side Floating Supply Voltage for W phase
Internally connected to W phase high side driver ground. W phase output
High Side Floating Supply voltage for V phase
Internally connected to V phase high side driver ground. V phase output
High Side Floating Supply voltage for U phase
Internally connected to U phase high side driver ground. U phase output
Positive Bus Input Voltage
2
4
5
7
8
10
12
13
14
15
16
17
18
19
20
21
22
23
NU
Low Side Emitter Connection − Phase U
NV
Low Side Emitter Connection − Phase V
NW
Low Side Emitter Connection − Phase W
HIN(U)
HIN(V)
HIN(W)
LIN(U)
LIN(V)
LIN(W)
T/ITRIP
VDD
Logic Input High Side Gate Driver − Phase U
Logic Input High Side Gate Driver − Phase V
Logic Input High Side Gate Driver − Phase W
Logic Input Low Side Gate Driver − Phase U
Logic Input Low Side Gate Driver − Phase V
Logic Input Low Side Gate Driver − Phase W
Temperature Monitor and Shut−down pin
+15 V Main Supply
VSS
Negative Main Supply
1. Pins 3, 6, 9 and 11 are not present
ABSOLUTE MAXIMUM RATINGS (at Tc = 25°C) (Note 2)
Symbol Rating
Supply voltage
Conditions
Value
Unit
V
V
CC
V
CE
P to NU, NV, NW, surge < 500 V (Note 3)
P to U, V, W; U to NU; V to NV; W to NW
P, U, V, W, NU, NV, NW terminal current
P, U, V, W, NU, NV, NW terminal current, Tc = 100°C
P, U, V, W, NU, NV, NW terminal current, pulse width 1 ms
IGBT per 1 channel
450
Collector-emitter voltage
Output current
600
V
Io
10
A
5
A
Iop
Pd
Output peak current
20
20
A
Maximum power dissipation
Gate driver supply voltage
W
V
V
BS
VB(U) to VS(U), VB(V) to VS(V), VB(W) to VS(W), VDD to
VSS (Note 4)
−0.3 to +20.0
VIN
VITRIP
Tj
Input signal voltage
ITRIP terminal voltage
Junction temperature
Storage temperature
Operating case temperature
Tightening torque
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V), LIN(W)
−0.3 to +7.0
VSS to +5.0
150
V
V
T/ITRIP terminal
IGBT, FRD
°C
Tstg
Tc
−40 to +125
−40 to +100
0.9
°C
IPM case temperature
°C
MT
Case mounting screws
Nm
Vrms
Vis
Isolation voltage
50 Hz sine wave AC 1 minute (Note 5)
2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
4. VBS = VB(U) to VS(U), VB(V) to VS(V), VB(W) to VS(W).
5. Test conditions: AC2500V, 1 s.
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4
STK544UC63K−E
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Conditions
Min
0
Typ
280
15
Max
450
Unit
V
V
CC
Supply voltage
P to NU, NV, NW
VBS
Gate driver supply voltage
VB(U) to VS(U), VB(V) to VS(V),
VB(W) to VS(W)
13.0
17.5
V
V
VDD to VSS
14.0
0
15
−
16.5
0.3
5.0
20
−
V
V
DD
VIN(ON)
ON-state input voltage
OFF-state input voltage
PWM frequency
HIN(U), HIN(V), HIN(W), LIN(U),
LIN(V), LIN(W)
VIN(OFF)
3.0
1
−
V
f
−
kHz
ms
ms
Nm
PWM
DT
Dead time
Turn-off to Turn-on (external)
ON and OFF
0.5
1
−
PWIN
Allowable input pulse width
Tightening torque
−
−
‘M3’ type screw
0.6
−
0.9
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (Tc = 25°C, V
(V , V ) = 15 V unless otherwise noted)
BS DD
BIAS
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
POWER OUTPUT SECTION
I
Collector-emitter leakage current
V
= 600 V
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.1
2.7
−
mA
mA
V
CE
CE
IR(BD) Bootstrap diode reverse current
VR(DB) = 600 V
−
V
(SAT) Collector to emitter saturation voltage
IC = 10 A, Tj = 25°C
IC = 5 A, Tj = 100°C
IF = 10 A, Tj = 25°C
IF = 5 A, Tj = 100°C
IF = 0.1 A
2.1
1.7
2.2
1.7
2.0
2
CE
V
VF
Diode forward voltage
2.8
−
V
V
VF(BD) Bootstrap diode forward voltage
−
V
R
Bootstrap circuit resistance
Resistor value for common boot charge line
Resistor value for separate boot charge line
IGBT
−
W
BC
BS
R
10
4.9
8.5
−
W
Junction to case thermal resistance
6.2
°C/W
qj−c(T)
q−c(D)
FRD
10.6 °C/W
DRIVER SECTION
ID
ID
Gate driver consumption current
V
V
= 15 V (Note 6), per driver
= 15 V, total
−
−
0.08
2.0
−
0.4
4.0
−
mA
mA
V
BS
DD
VIN H
VIN L
High level Input voltage
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) to VSS
2.5
−
Low level Input voltage
−
0.8
160
203
4.67
1.4
−
V
I
I
Logic 0 input leakage current
Logic 1 input leakage current
ITRIP threshold voltage
76
97
3.67
0.8
−
118
150
4.17
1.1
0.9
9
mA
mA
V
IN+
IN−
V
T/ITRIP to VSS
ITRIP
ITRIP
t
ITRIP to shutdown propagation delay
ITRIP blanking time
ms
ms
ms
ms
V
t
ITRIPBL
FLTCLR FAULT clearance delay time
Automatic reset after protection
6
12
DT
Dead time (Internal dead time injected by driver)
V and V supply undervoltage positive
DD
220
10.5
300
11.1
380
11.7
V
V
CCUV+
BSUV+
BS
going input threshold
V
V
and V supply undervoltage negative
10.3
10.9
11.5
V
CCUV−
BSUV−
DD
BS
V
going input threshold
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5
STK544UC63K−E
ELECTRICAL CHARACTERISTICS (Tc = 25°C, V
(V , V ) = 15 V unless otherwise noted)
BIAS
BS
DD
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
V
and V supply undervoltage Iockout
0.14
0.2
−
V
CCUVH
BSUVH
DD
BS
V
hysteresis
SWITCHING CHARACTER
t
Switching time
IC = 10 A, Tj = 25°C
IC = 5 A, Tj = 25°C
−
−
−
−
−
−
−
−
−
−
0.35
0.45
89
0.7
0.8
−
ms
ms
mJ
mJ
mJ
mJ
mJ
mJ
mJ
ns
ON
t
OFF
E
Turn-on switching loss
Turn-off switching loss
Total switching loss
ON
E
OFF
E
TOT
74
−
163
−
E
Turn-on switching loss
Turn-off switching loss
Total switching loss
IC = 5 A, Tj = 100°C
IC = 5 A, Tj = 100°C
125
−
ON
OFF
TOT
REC
E
E
82
−
207
−
E
Diode reverse recovery energy
Diode reverse recovery time
40
−
t
150
−
RR
RBSOA Reverse bias safe operating area
SCSOA Short circuit safe operating area
IC = 20 A, V = 450 V
Full Square
−
CE
V
CE
= 400 V, Tj = 150°C
5
−
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. VBS = VBU to U, VBV to V, VBW to W
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6
STK544UC63K−E
TYPICAL CHARACTERISTICS INV SECTION
20
15
10
5
20
15
Tj = 25°C
10
Tj = 100°C
Tj = 100°C
5
Tj = 25°C
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
−
VF, FORWARD VOLTAGE (V)
VCE , COLLECTOR EMITTER VOLTAGE (V)
Figure 4. VCE versus IC for Different Temperatures
Figure 5. VF versus IF for Different Temperatures
(VDD = 15 V)
1.5
0.4
V
CC
V
DD
= 300 V
= 15 V
V
CC
V
DD
= 300 V
= 15 V
1.2
0.9
0.6
0.3
0.0
0.3
0.2
0.1
0.0
Tj = 100°C
Tj = 100°C
Tj = 25°C
Tj = 25°C
0
5
10
15
20
0
5
10
15
20
IC, COLLECTOR CURRENT (A)
IC , COLLECTOR CURRENT (A)
Figure 6. EON versus IC for Different Temperatures
Figure 7. EOFF versus IC for Different Temperatures
1.0
0.8
0.6
0.4
0.2
0.0
0.000001 0.00001 0.0001 0.001
0.01
0.1
1
−
ON PULSE WIDTH (S)
Figure 8. Thermal Impedance Plot
Figure 9. Turn-on Waveform Tj = 100°C, VCC = 300 V
Figure 10. Turn-off Waveform Tj = 100°C, VCC = 300 V
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7
STK544UC63K−E
APPLICATIONS INFORMATION
Input/Output Timing Chart
VBS undervoltage protection reset signal
HIN
LIN
VDD undervoltage protection reset voltage (Note 8)
VBS undervoltage protection reset voltage (Note 9)
VDD
VB(U), VB(V),
VB(W)
Voltage ≥ 4.67 V
Note 10
Voltage < 3.67 V
T/ITRIP
Cross-conduction prevention period (Note 7)
Upper IGBT
Gate Drive
Lower IGBT
Gate Drive
FAULT clearance delay time (typ 9 ms)
Figure 11. Input/Output Timing Chart
NOTES:
7. This section of the timing diagram shows the effect of cross-conduction prevention.
8. This section of the timing diagram shows that when the voltage on V decreases sufficiently all gate output signals will go low, switching
DD
off all six IGBTs. When the voltage on V rises sufficiently, normal operation will resume.
DD
9. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output U (V, W) is
switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume.
10.This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after
the over-current condition is removed.
Input/Output Logic Table
Table 1. INPUT/OUTPUT LOGIC TABLE
INPUT
OUTPUT
Low Side IGBT
OFF
HIN
L
LIN
H
T/ITRIP
High Side IGBT
U, V, W
P
L
L
L
L
H
ON
H
L
OFF
OFF
OFF
OFF
ON
NU, NV, NW
High Impedance
High Impedance
High Impedance
H
H
OFF
L
L
OFF
X
X
OFF
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STK544UC63K−E
Thermistor Characteristics
Table 2. THERMISTOR CHARACTERISTICS
Symbol
Parameter
Resistance
Condition
Tth = 25°C
Tth = 125°C
Min
99
Typ
100
2.52
4250
−
Max
101
Unit
kW
kW
K
R
25
R
2.40
−4207
−40
2.65
4293
+125
125
B
B-Constant (25 to 50°C)
Temperature Range
°C
Thermistor Temperature (Tth) − Thermistor Resistance (RTH)
10000
1000
100
10
min
typ
max
1
−40 −30 −20 −10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Tth, Thermistor Temperature (5C)
Figure 12. Thermistor Resistance versus Thermistor Temperature
Thermistor Temperature (Tth) − T/ITRIP to GND Voltage Characteristics (Vsense)
4.0
3.5
3.0
2.5
2.0
1.5
min
1.0
typ
0.5
max
0.0
−40 −30 −20 −10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Tth, Thermistor Temperature (5C)
Figure 13. Thermistor Voltage versus Thermistor Temperature
Conditions: RP = 4.3 kW 1% Pull-down and VDD = 15.0 V (See below)
15 V
VDD (22)
Thermistor
Driver IC
9.1 kW
T/ITRIP (21)
18 kW
4.3 kW
2.4 kW
47 pF
VSS (23)
Figure 14. Sample Application Circuit for Temperature Monitoring
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9
STK544UC63K−E
TEST CIRCUITS
• I
CE, IR(DB)
U+
V+
10
5
W+
10
2
U−
8
V−
5
W−
7
ICE, IR
VBS = 15 V
A
10
8
2
A
B
A
8
4
B
12
13
14
VBS = 15 V
VCE, VR
5
1
U+,V+,W+: High side phase
U−,V−,W−: Low side phase
VBS = 15 V
2
22
VDD = 15 V
U(DB)
V(DB)
4
W(DB)
23, 12, 13, 14
A
B
7
1
23
23
23
Figure 15. Test Circuit for ICE
• V (sat) (Test by pulse)
CE
U+
10
8
V+
10
5
W+
10
2
U−
8
V−
5
W−
7
VBS = 15 V
VBS = 15 V
VBS = 15 V
VDD = 15 V
A
A
B
C
2
8
12
18
13
19
14
20
4
5
15
16
17
IC
V
1
VCE(sat)
2
22
B
C
23, 12, 13, 14
Figure 16. Test Circuit for VCE(SAT)
• VF (Test by pulse)
U+
10
8
V+
10
5
W+
10
2
U−
8
V−
5
W−
2
A
B
A
12
13
14
IF
V
U(DB)
7
V(DB)
4
W(DB)
B
A
B
1
22
22
22
Figure 17. Test Circuit for VF
• ID
VBS U+
VBS V+
VBS W+
V
DD
ID
A
7
8
4
5
1
2
22
A
A
B
B
23
VD*
Figure 18. Test Circuit for ID
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10
STK544UC63K−E
• Switching time (The circuit is a representative example of
the lower side U phase.)
U+
10
12
8
V+
10
13
5
W+
10
14
2
U−
10
12
10
8
V−
10
13
10
5
W−
10
14
10
2
7
VBS = 15 V
VBS = 15 V
VBS = 15 V
VDD = 15 V
A
B
C
D
E
A
C
8
4
5
1
CS
V
CC
12
15
13
16
14
17
18
19
20
D
B
2
22
Input Signal
(0 to 5 V)
E
23, 12, 13, 14
Io
90%
Figure 19. Test Circuit for Switching Time
lo
10%
tON
tOFF
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP23, 62x21.8 FP−4
CASE 127FC
ISSUE O
DATE 07 JAN 2019
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXXXXXXXXXXXXX
ZZZATYWW
AT
Y
= Assembly & Test Location
= Year
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON01973H
SIP23, 62x21.8 FP−4
PAGE 1 OF 1
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