STK554U392A-E [ONSEMI]
智能功率模块 (IPM)，600V，15A;
| 型号： | STK554U392A-E |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块 (IPM)，600V，15A |
| 文件： | 总16页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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STK554U392A-E
Intelligent Power Module (IPM)
600 V, 15 A
Overview
This “Inverter IPM” is highly integrated device containing all High
Voltage (HV) control from HV-DC to 3-phase outputs in a single small SIP
module. Output stage uses IGBT / FRD technology and implements Under
Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault
Detection output flag. Internal Boost diodes are provided for high side gate
boost drive.
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PACKAGE PICTURE
Function
Single control power supply due to Internal bootstrap circuit for high
side pre-driver circuit
All control inputs and status outputs are at low voltage levels directly
compatible with microcontrollers.
A single power supply drive is enabled through the use of bootstrap
circuits for upper power supplies
Built-in dead-time for shoot-thru protection
Having open emitter output for low side IGBTs; individual shunt
resistor per phase for OCP
SIP29 56x21.8
Externally accessible embedded thermistor for substrate temperature
measurement
Shutdown function ‘ITRIP’ to disable all operations of the 6 phase
output stage by external input
Certification
UL1557 (File number : E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Remarks
V+ to U-, V-, W-, surge < 500 V
V+ to U, V, W or U, V, W, to U-, V-, W-
V+,U-,V-,W-,U,V,W terminal current
V+,U-,V-,W-,U,V,W terminal current, Tc = 100C
V+,U-,V-,W-,U,V,W terminal current, P.W. = 1 ms
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
HIN1, 2, 3, LIN1, 2, 3
Ratings
Unit
V
V
V
Supply voltage
*1
450
600
CC
Collector-emitter voltage
Output current
V
CE
±15
A
Io
±8
A
Output peak current
Pre-driver voltage
Iop
±30
A
VD1, 2, 3, 4
*2
20
V
0.3 to V
0.3 to V
Input signal voltage
VIN
VFLTEN
Pd
V
DD
DD
FLTEN terminal voltage
Maximum power dissipation
Junction temperature
Storage temperature
Operating case temperature
Tightening torque
FLTEN terminal
V
IGBT per 1 channel
35
W
Tj
IGBT, FRD, Pre-Driver IC
150
C
C
C
Nm
VRMS
Tstg
Tc
40 to +125
40 to +100
0.9
IPM case
A screw part
*3
*4
Withstand voltage
Vis
50 Hz sine wave AC 1 minute
2000
Reference voltage is “V ” terminal voltage unless otherwise specified.
SS
*1 : Surge voltage developed by the switching operation due to the wiring inductance between + and U- (V-, W-) terminal.
*2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = V to V terminal voltage.
DD
SS
*3 : Flatness of the heat-sink should be less than 50m to +100m.
*4 : Test conditions : AC 2500 V, 1 second
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
December 2016 - Rev. 2
1
Publication Order Number :
STK554U392C-E/D
STK554U392C-E
Electrical Characteristics at Tc = 25C, VD1, VD2, VD3, VD4 = 15 V
Test
circuit
Parameter
Power output section
Symbol
Conditions
Min
Typ
Max
Unit
I
V
= 600 V
CE
Collector-emitter cut-off current
Bootstrap diode reverse current
-
-
-
-
-
-
-
-
-
-
100
100
2.4
-
μA
μA
CE
IR(BD)
Fig.1
Fig.2
Fig.3
-
VR(BD) = 600 V
Ic = 15 A, Tj = 25C
Ic = 8 A, Tj = 100C
IF = 15 A, Tj = 25C
IF = 8 A, Tj = 100C
IGBT
1.7
1.4
1.9
1.4
-
V
V
(SAT)
Collector to emitter saturation voltage
Diode forward voltage
V
V
CE
F
2.6
-
θj-c(T)
θj-c(D)
3.5
5
Junction to case thermal resistance
Control (Pre-driver) section
Pre-driver power dissipation
C/W
FWD
-
VD1, 2, 3 = 15 V
VD4 = 15 V
-
0.08
1.6
-
0.4
4
ID
Fig.4
mA
-
2.5
-
-
-
-
-
High level Input voltage
Vin H
Vin L
IIN+
-
V
V
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to V
SS
Low level Input voltage
-
0.8
143
2
Logic 1 input leakage current
Logic 0 input leakage current
FLTEN terminal sink current
FLTEN clearance delay time
VIN = +3.3 V
VIN = 0 V
-
100
-
μA
μA
mA
ms
V
IIN-
-
IoSD
FLTCLR
VEN+
VEN-
VITRIP
tITRIP
FAULT : ON / VFLTEN = 0.1 V
From time fault condition clear
-
-
-
-
-
-
-
-
2
-
1.55
-
1.9
-
2.25
2.5
-
VEN rising
FLTEN Threshold
VEN falling
0.8
0.44
340
250
-
V
ITRIP threshold voltage
ITRIP(16) to VSS(29)
0.49
550
350
0.54
800
-
V
ITRIP to shutdown propagation delay
ITRIP blanking time
ns
ns
tITRIPBL
V
and V
supply undervoltage
supply undervoltage
supply undervoltage
BS
VCCUV+
VBSUV+
CC
protection reset
and V
BS
-
-
-
-
10.5
10.3
0.14
42.3
11.1
10.9
0.2
11.7
11.5
-
V
V
V
VCCUV-
VBSUV-
CC
protection set
and V
BS
V
VCCUVH
VBSUVH
CC
hysteresis
V
Thermistor for substrate temperature
Monitor
Resistance between
TH(27) and VSS(29)
Rt
47
51.7
kΩ
Reference voltage is “V ” terminal voltage unless otherwise specified.
SS
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2
STK554U392C-E
Test
circuit
Parameter
Switching Character
Symbol
Conditions
Min
Typ
Max
Unit
t ON
t OFF
Eon
-
-
-
-
-
-
-
-
-
-
0.45
0.55
410
-
-
-
-
-
-
-
-
-
-
Io = 15 A
Inductive load
Switching time
Fig.5
Fig.5
μs
Io = 15 A, V+ = 300 V,
Turn-on switching loss
μJ
μJ
μJ
μJ
μJ
μJ
μJ
ns
-
V
= 15 V, L = 3.9 mH
Turn-off switching loss
Eoff
390
DD
Tc = 25C
Total switching loss
Etot
800
Io = 8 A, V+ = 300 V,
Turn-on switching loss
Eon
270
V
= 15 V, L = 3.9 mH
Turn-off switching loss
Eoff
Fig.5
280
DD
Tc = 100C
Total switching loss
Etot
550
Io = 8 A, V+ = 400 V, V
= 15 V,
Diode reverse recovery energy
Diode reverse recovery time
Reverse bias safe operating area
Short circuit safe operating area
Erec
Trr
-
-
-
-
12
DD
L=3.9mH, Tc=100C
54
Io = 30 A, V
= 450 V
RBSOA
SCSOA
Full square-
-
CE
= 400 V, Tc = 100C
V
4
-
μs
CE
Between U(V,W) to
U-(V-,W-)
Allowable offset voltage slew rate
dv/dt
-
-
50
V/ns
50
Reference voltage is “V ” terminal voltage unless otherwise specified.
SS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes
1. The pre-drive power supply low voltage protection has approximately 200 mV of hysteresis and operates as follows.
Upper side :
The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will
continue till the input signal will turn ‘low’.
Lower side :
The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input
signal voltage.
2. When assembling the IPM on the heat sink the tightening torque range is 0.6 Nm to 0.9 Nm.
3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction.
4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the
rating of output peak current (Iop).
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3
STK554U392C-E
Module Pin-Out Description
Pin
Name
Description
1
VB3
High Side Floating Supply Voltage 3
Output 3 - High Side Floating Supply Offset Voltage
Without pin
2
3
4
5
6
7
8
9
W, VS3
-
-
Without pin
VB2
High Side Floating Supply voltage 2
Output 2 - High Side Floating Supply Offset Voltage
Without pin
V,VS2
-
-
Without pin
VB1
High Side Floating Supply voltage 1
Output 1 - High Side Floating Supply Offset Voltage
Without pin
10 U,VS1
11
12
-
-
Without pin
13 V+
Positive Bus Input Voltage
14
15
-
-
Without pin
Without pin
16 ITRIP
17 U-
Current protection pin
Low Side Emitter Connection - Phase U
Enable input / Fault output
18 FLTEN
19 V-
Low Side Emitter Connection - Phase V
Logic Input High Side Gate Driver - Phase U
Low Side Emitter Connection - Phase W
Logic Input High Side Gate Driver - Phase V
Logic Input High Side Gate Driver - Phase W
Logic Input Low Side Gate Driver - Phase U
Logic Input Low Side Gate Driver - Phase V
Logic Input Low Side Gate Driver - Phase W
Thermistor output
20 HIN1
21 W-
22 HIN2
23 HIN3
24 LIN1
25 LIN2
26 LIN3
27 TH
28 VDD
29 VSS
+15 V Main Supply
Negative Main Supply
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STK554U392C-E
Equivalent Block Diagram
VB3( 1)
W,VS3( 2)
VB2( 5)
V,VS2( 6)
VB1( 9)
U,VS1(10)
V+ (13)
DB DB DB
U.V.
U.V.
U.V.
U- (17)
V- (19)
W- (21)
Level
Level
Shifter
Level
Shifter
Shifter
HIN1(20)
HIN2(22)
HIN3(23)
LIN1(24)
Logic
Logic
Logic
LIN2(25)
LIN3(26)
Thermistor
TH(27)
Shutdown
ITRIP(16)
VDD(28)
VSS(29)
S
R
Q
+
-
Under voltage
Detect
Timer
Enable/Disable
Vref
Latch time about 2ms
FLTEN(18)
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5
STK554U392C-E
Test Circuit
The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.
I
/ IR(BD)
CE
ICE
U+
13
10
V+
13
6
W+
13
2
U-
10
17
V-
6
19
W-
2
21
M
N
VD1=15V
VD2=15V
VD3=15V
VD4=15V
U(BD)
9
29
V(BD)
W(BD)
1
29
VCE
M
N
5
29
Fig.1
V (SAT) (Test by pulse)
CE
U+
13
10
20
V+
13
6
W+
13
2
U-
10
17
24
V-
6
19
25
W-
2
21
26
VD1=15V
VD2=15V
VD3=15V
M
N
m
22
23
Ic
VCE(SAT)
VD4=15V
5V
Fig.2
V (Test by pulse)
F
U+
13
10
V+
13
6
W+
13
2
U-
10
17
V-
6
19
W-
2
21
M
N
VF
IF
Fig.3
ID
VD1
9
10
VD2
5
6
VD3
1
2
VD4
28
29
ID
M
N
VD*
Fig.4
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6
STK554U392C-E
Switching time (The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5 V)
VD1=15V
VD2=15V
VD3=15V
Vcc
90%
Io
CS
10%
VD4=15V
Io
tOFF
tON
Input signal
Fig.5
RB-SOA (The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5 V)
VD1=15V
VD2=15V
Vcc
Io
CS
VD3=15V
VD4=15V
Io
Input signal
Fig.6
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7
STK554U392C-E
Input / Output Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
VDD undervoltage protection reset voltage
*2
VDD
VBS undervoltage protection reset voltage
*3
VB1,2,3
VIT≥0.54V
*4
ITRIP terminal
Voltage
VIT<0.44V
FLTEN
ON
*1
*1
Upper
U, V, W
OFF
Lower
U ,V, W
Automatically reset after protection
(typ.2ms)
Fig. 7
Notes
*1 : Shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay externally.
*2 : When V
decreases all gate output signals will go low and cut off all 6 IGBT outputs. When V
rises the operation will resume
DD
DD
immediately.
*3 : When the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return to
normal operation immediately after the upper side gate voltage rises.
*4 : When VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2 ms (typ) after over current condition is
removed.
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8
STK554U392C-E
Logic level table
V+
Ho
FLTEN
1
Itrip
0
HIN1,2,3
LIN1,2,3
U,V,W
Vbus
0
HIN1,2,3
1
0
0
1
X
X
0
1
0
1
X
X
(15,16,17)
1
0
IC
U,V,W
(8,5,2)
Driver
1
1
1
0
0
Off
LIN1,2,3
0
Off
(18,19,20)
1
Off
Lo
X
Off
Fig. 8
Sample Application Circuit
STK554U392A-E
VB1: 9
CB1
CB2
CB3
U,VS1:10
V+:3
CI
CS
VB2: 5
Vcc
V,VS2: 6
U-:7
RSU
RSV
RSW
VB3: 1
V-:19
W-:21
W,VS3: 2
Op-Amp,
Controller
HIN1:20
HIN2:22
U,VS1:10
V,VS2: 6
W,VS3: 2
HIN3:23
LIN1:24
LIN2:25
LIN3:26
TH:27
Control
Circuit
(5V)
FLTEN:18
ITRIP:16
RS,
Controller
RP
RTH
VDD:28
VSS:29
CD4
VD4=15V
Fig. 9
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STK554U392C-E
Recommended Operating Condition at Tc = 25C
Item
Symbol
Conditions
Min
Typ
Max
Unit
V
Supply voltage
V
V+ to U-(V-,W-)
VB1 to U, VB2 to V, VB3 to W
to V
0
280
15
450
17.5
16.5
CC
VD1, 2, 3
VD4
12.5
13.5
Pre-driver
V
V
V
*1
15
supply voltage
DD
SS
ON-state input voltage
OFF-state input voltage
PWM frequency
VIN(ON)
VIN(OFF)
fPWM
3.0
0
-
-
-
-
-
-
5.0
0.3
20
-
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
1
kHz
μs
Dead time
DT
Turn-off to turn-on (external)
ON and OFF
0.5
1
Allowable input pulse width
Tightening torque
PWIN
-
μs
‘M3’ type screw
0.6
0.9
Nm
*1 : Pre-drive power supply (VD4 = 15 ±1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precaution
1. This IPM includes internal bootstrap diode and resistor. By adding a bootstrap capacitor “CB”, a high side drive voltage is generated;
each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47 μF, however, this value
needs to be verified prior to production. If selecting the capacitance more than 47 μF (±20%), connect a resistor (about 20 Ω) in series
between each 3-phase upper side power supply terminals (VB1, 2, 3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge
voltages. Recommended value of “CS” is in the range of 0.1 to 10 μF.
3. The “FLTEN” terminal (Pin 18) is I/O terminal; Fault output / Enable input. It is used to indicate an internal fault condition of the module
and also can be used to disable the module operation.
4. Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between V
terminal and TH
SS
terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used. The
temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below.
5. The pull-down resistor (: 33 kΩ (typ)) is connected with the inside of the signal input terminal, but please connect the pull-down
resistor(about 2.2 to 3.3 kΩ) outside to decrease the influence of the noise by wiring etc.
6. As protection of IPM to the unusual current by a short circuit etc., it recommends installing shunt resistors and an over-current protection
circuit outside. Moreover, for safety, a fuse on Vcc line is recommended.
7. Disconnection of terminals U, V, or W during normal motor operation will cause damage to IPM, use caution with this connection.
.
8. The “ITRIP” terminal (Pin 16) is the input terminal to shut down. When VITRIP exceeds threshold (0.44 V to 0.54 V) all IGBT’s are
turned off. And normal operation resumes 2 ms (typ) after over current condition is removed. Therefore, please turn all the input
signals off (Low) in case of detecting error at the “FLTEN” terminal.
9. When input pulse width is less than 1 μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit and does not guarantee a design as the mass production set.
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10
STK554U392C-E
The characteristic of thermistor
Parameter
Resistance
Symbol
R25
Condition
Min
44.6
1.28
4010
40
Typ.
47.0
1.41
4050
Max
49.4
1.53
4091
+125
Unit
kΩ
kΩ
K
T = 25C
T = 125C
Resistance
R125
B
B-Constant (25 to 50C)
Temperature Range
C
Fig. 10 Variation of thermistor resistance with temperature
Condition
Pull-up resistor = 4.7k phm
Pull-up voltage of TH = 5 V
Fig. 11 Variation of temperature sense voltage with thermistor temperature
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STK554U392C-E
Maximum Phase current
Fig. 12 Maximum sinusoidal phase current as function of switching frequency
At Tc = 100C, V = 300 V
CC
Switching waveform
X:100 ns/div
Ic: 5 A/div
Vce: 100 V/div
Fig. 13 IGBT Turn-on. Typical turn-on waveform at Tc = 100C, V
CC
= 300 V, Ic = 15 A
X:100 ns/div
Vce: 100 V/div
Ic: 5 A/div
Fig. 14 IGBT Turn-off. Typical turn-off waveform Tc = 100C, V
CC
= 300 V, Ic = 15 A
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STK554U392C-E
CB capacitor value calculation for bootstrap circuit
Calculate condition
Item
Symbol
VBS
Value
15
Unit
V
Upper side power supply
Total gate charge of output power IGBT at 15 V
Upper side power supply low voltage protection
Upper side power dissipation
Qg
132
12
nC
V
UVLO
IDmax
Ton-max
400
-
μA
s
ON time required for CB voltage to fall from 15V to UVLO
Capacitance calculation formula
CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the upper side is
calculated as follows:
VBS CB – Qg – IDmax Ton-max = UVLO CB
CB = (Qg + IDmax Ton-max) / (VBS – UVLO)
The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated
above. The recommended value of CB is in the range of 1 to 47 μF, however, the value needs to be verified prior to production.
Cb vs Tonmax
Ton-max[ms]
Fig. 15 Ton-max vs CB characteristic
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STK554U392C-E
PACKAGE DIMENSIONS
unit : mm
SIP29 56x21.8
CASE 127BW
ISSUE O
missing pin : 3,4,7,8,11,12,14,15
56.0
R1.7
1
29
+0 . 2
0.05
3.2
6.7−+00.5. 1
0.6−
1.27
1.27 × 28=35.56
46.2
50.0
62.0
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14
STK554U392C-E
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
8 / Tube
SIP29 56x21.8
(Pb-Free)
STK554U392A-E
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
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